LINER LTC4361IDC-1-TRPBF Overvoltage/overcurrent protection controller Datasheet

LTC4361-1/LTC4361-2
Overvoltage/Overcurrent
Protection Controller
FEATURES
DESCRIPTION
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The LTC®4361 overvoltage/overcurrent protection controller safeguards 2.5V to 5.5V systems from input supply
overvoltage. It is designed for portable devices with
multiple power supply options including wall adaptors,
car battery adaptors and USB ports.
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2.5V to 5.5V Operation
Overvoltage Protection Up to 80V
No Input Capacitor or TVS Required for Most
Applications
2% Accurate 5.8V Overvoltage Threshold
10% Accurate 50mV Overcurrent Circuit Breaker
<1μs Overvoltage Turn-Off, Gentle Shutdown
Controls N-Channel MOSFET
Adjustable Power-Up dV/dt Limits Inrush Current
Reverse Voltage Protection
Power Good Output
Low Current Shutdown
Latchoff (LTC4361-1) or Auto-Retry (LTC4361-2)
After Overcurrent
Available in 8-Lead ThinSOT™ and 8-Lead
(2mm × 2mm) DFN Packages
APPLICATIONS
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USB Protection
Handheld Computers
Cell/Smart Phones
MP3/MP4 Players
Digital Cameras
The LTC4361 controls an external N-channel MOSFET in
series with the input power supply. During overvoltage
transients, the LTC4361 turns off the MOSFET within
1μs, isolating downstream components from the input
supply. Inductive cable transients are absorbed by the
MOSFET and load capacitance. In most applications, the
LTC4361 provides protection from transients up to 80V
without requiring transient voltage suppressors or other
external components.
The LTC4361 has a delayed start-up and adjustable dV/dt
ramp-up for inrush current limiting. A PWRGD pin provides
power good monitoring for VIN. The LTC4361 features a soft
shutdown controlled by the ON pin and drives an optional
external P-channel MOSFET for negative voltage protection.
Following an overvoltage condition, the LTC4361 automatically restarts with a start-up delay. After an overcurrent
fault, the LTC4361-1 remains off while the LTC4361-2
automatically restarts after a 130ms start-up delay.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT, Hot Swap, No RSENSE and PowerPath are trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Protection from Overvoltage and Overcurrent
VIN
5V
0.025Ω
Si1470DH
COUT
Output Protected from Overvoltage at Input
VIN
VOUT
5V
1.5A
GATE
SENSE OUT
VOUT
VIN, VOUT
5V/DIV
IN
LTC4361
ON
VGATE
10V/DIV
PWRGD
GND
436112 TA01a
0.5μs/DIV
Si1470DH
COUT = 10μF
436112 TA01b
436112f
1
LTC4361-1/LTC4361-2
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Bias Supply Voltage (IN) ............................ –0.3V to 85V
Input Voltages
SENSE ................................................... –0.3V to 85V
OUT, ON ................................................... –0.3V to 9V
Output Voltages
PWRGD.................................................... –0.3V to 9V
GATE (Note 3) ........................................ –0.3V to 15V
GATEP.................................................... –0.3V to 85V
IN to GATEP ........................................... –0.3V to 10V
Operating Temperature Range
LTC4361C ................................................ 0°C to 70°C
LTC4361I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
TSOT................................................................. 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
ON 1
OUT 2
GATEP 3
GND 4
8 IN
GND 1
8 PWRGD
7 GATE
6 SENSE
5 IN
GATEP 2
9
OUT 3
ON 4
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
7 SENSE
6 GATE
5 PWRGD
DC PACKAGE
8-LEAD (2mm s 2mm) PLASTIC DFN
TJMAX = 125°C, θJA = 195°C/W
TJMAX = 125°C, θJA = 102°C/W
EXPOSED PAD (PIN 9) IS GND, CONNECTION OPTIONAL
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4361CTS8-1#TRMPBF
LTC4361CTS8-1#TRPBF
LTDWN
8-Lead Plastic TSOT-23
0°C to 70°C
LTC4361CTS8-2#TRMPBF
LTC4361CTS8-2#TRPBF
LTFMN
8-Lead Plastic TSOT-23
0°C to 70°C
LTC4361ITS8-1#TRMPBF
LTC4361ITS8-1#TRPBF
LTDWN
8-Lead Plastic TSOT-23
–40°C to 85°C
LTC4361ITS8-2#TRMPBF
LTC4361ITS8-2#TRPBF
LTFMN
8-Lead Plastic TSOT-23
–40°C to 85°C
LTC4361CDC-1#TRMPBF
LTC4361CDC-1#TRPBF
LDWP
8-Lead (2mm × 2mm) Plastic DFN
0°C to 70°C
LTC4361CDC-2#TRMPBF
LTC4361CDC-2#TRPBF
LFMP
8-Lead (2mm × 2mm) Plastic DFN
0°C to 70°C
LTC4361IDC-1#TRMPBF
LTC4361IDC-1#TRPBF
LDWP
8-Lead (2mm × 2mm) Plastic DFN
–40°C to 85°C
LTC4361IDC-2#TRMPBF
LTC4361IDC-2#TRPBF
LFMP
8-Lead (2mm × 2mm) Plastic DFN
–40°C to 85°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
436112f
2
LTC4361-1/LTC4361-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VON = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supplies
VIN
Input Voltage Range
VIN(UVL)
Input Undervoltage Lockout
IIN
Input Supply Current
l
2.5
VIN Rising
l
1.8
2.1
2.45
V
VON = 0V
l
220
400
μA
VON = 2.5V
l
1.5
10
μA
VIN Rising
l
5.684
5.8
5.916
V
80
V
Thresholds
VIN(OV)
IN Pin Overvoltage Threshold
ΔVOV
Overvoltage Hysteresis
l
25
100
200
mV
Overcurrent Threshold
VIN – VSENSE
l
45
50
55
mV
2.5V ≤ VIN < 3V, IGATE = –1μA
3V ≤ VIN < 5.5V, IGATE = –1μA
l
l
3.5
4.5
4.5
6
6
7.9
V
V
ΔVOC
External Gate Drive
ΔVGATE
External N-Channel MOSFET Gate Drive
(VGATE – VOUT)
VGATE(TH)
GATE High Threshold for PWRGD Status VIN = 3.3V
VIN = 5V
l
l
5.7
6.7
6.3
7.2
6.8
7.8
V
V
IGATE(UP)
GATE Pull-Up Current
VGATE = 1V
l
–5
–10
–15
μA
VGATE(UP)
GATE Ramp-Up
VGATE = 1V to 7V
l
1.5
3
4.5
V/ms
IGATE(FST)
GATE Pull-Down Current
Fast Turn-Off, VIN = 6V, VGATE = 9V
l
15
30
60
mA
IGATE(DN)
GATE Pull-Down Current
VON = 2.5V, VGATE = 9V
l
10
40
80
μA
IOUT(IN)
OUT Input Current
VOUT = 5V, VON = 0V
VOUT = 5V, VON = 2.5V
l
l
5
10
0
20
±3
μA
μA
VON(TH)
ON Input Threshold
l
0.4
1.5
V
ION
ON Pull-Down Current
l
2.5
5
10
μA
l
5
5.8
7.5
V
0.8
Input Pins
VON = 2.5V
Output Pins
VGATEP(CLP)
IN to GATEP Clamp Voltage
RGATEP
GATEP Resistive Pull-Down
VGATEP = 3V
l
VPWRGD(OL)
PWRGD Output Low Voltage
VIN = 5V, IPWRGD = 3mA
l
RPWRGD
PWRGD Pull-Up Resistance to OUT
VIN = 6.5V, VPWRGD = 1V
l
tON
GATE On Delay
VIN High to IGATE = –5μA
tOFF
GATE Off Propagation Delay
2
3.2
MΩ
0.23
0.4
V
250
500
800
kΩ
l
50
130
200
ms
VIN = Step 5V to 6.5V
VIN – VSENSE = Step 0mV to 100mV
l
l
5
0.25
10
1
20
μs
μs
VIN = Step 5V to 6.5V
VGATE > VGATE(TH) to PWRGD Low
l
l
25
0.25
65
1
100
μs
ms
VON = Step 0V to 2.5V
l
2
5
μs
Delay
tPWRGD
tON(OFF)
PWRGD Delay
ON High to GATE Off
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 3: An internal clamp limits VGATE to a minimum of 4.5V above VOUT.
Driving this pin to voltages beyond this clamp may damage the device.
436112f
3
LTC4361-1/LTC4361-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 5V, VON = 0V, unless otherwise noted.
Input Supply Current
vs Input Voltage
GATE Fast Pull-Down Current
vs Temperature
GATE Drive vs GATE Current
10000
40
8
7
1000
100
VON = 2.5V
10
VIN = 5V
5
IGATE(FST) (mA)
$VGATE (V)
IIN (μA)
35
6
VON = 0V
VIN = 6V
VGATE = 9V
VIN = 3V
4
3
VIN = 2.5V
2
30
25
1
1
0.1
0
100
2
4
6
8
10
12
500
8
tOFF (μs)
200
7
11
6
10
5
4
0
2
3
IPWRGD (mA)
4
0
5
9
8
VGATE(TH)
7
6
5
1
0
VIN = VOUT
VGATE
2
100
12
VIN = STEP 5V TO (VIN(OV) + VOVDRV)
3
1
436112 G03
VGATE /VGGATE(TH) (V)
400
0.5
1
1.5
VOVDRV (V)
436112 G04
2
2.5
4
2.5
3
3.5
4
4.5
VIN (V)
436012 G05
Normal Start-Up Sequence
100
GATE Voltage and GATE High
Threshold (for PWRGD Status)
vs Input Voltage
GATE Off Propagation Delay
vs Overdrive
300
75
436112 G02
PWRGD Voltage
vs PWRGD Current
0
50
0
25
TEMPERATURE (°C)
–25
IGATE (μA)
436112 G01
VPWRGD(OL) (mV)
20
–50
0
10
VIN (V)
1
5
5.5
6
436112 G06
GATE Slow Ramp-Up
Entering Sleep Mode
VON
5V/DIV
VIN
5V/DIV
VOUT
5V/DIV
VIN
5V/DIV
VOUT
5V/DIV
VOUT
5V/DIV
VGATE
10V/DIV
VGATE
10V/DIV
VGATE
10V/DIV
ICABLE
0.5A/DIV
ICABLE
0.5A/DIV
ICABLE
0.5A/DIV
20ms/DIV
FIGURE 5 CIRCUIT
RIN = 150mΩ, LIN = 0.7μH
RSENSE = 25mΩ
LOAD = 10Ω, COUT = 10μF
436112 G07
1ms/DIV
FIGURE 5 CIRCUIT
RIN = 150mΩ, LIN = 0.7μH
RSENSE = 25mΩ
LOAD = 10Ω, COUT = 10μF
436112 G08
50μs/DIV
FIGURE 5 CIRCUIT
RIN = 150mΩ, LIN = 0.7μH
RSENSE = 25mΩ
LOAD = 10Ω, COUT = 10μF
436112 G09
436112f
4
LTC4361-1/LTC4361-2
PIN FUNCTIONS
Exposed Pad (DFN): Ground. Connection to PCB is
optional.
GATE: Gate Drive for External N-Channel MOSFET. An
internal charge pump provides a 10μA pull-up current
to charge the gate of the external N-channel MOSFET. An
additional ramp circuit limits the GATE ramp rate when
turning on to 3V/ms. For slower ramp rates, connect an
external capacitor from GATE to GND. An internal clamp
limits GATE to 6V above the OUT pin voltage. An internal
GATE high comparator controls the PWRGD pin.
GATEP: Gate Drive for External P-Channel MOSFET. GATEP
connects to the gate of an optional external P-channel
MOSFET to protect against negative voltages at IN. This
pin is internally clamped to 5.8V below VIN. An internal
2M resistor connects this pin to ground. Connect to IN
if not used.
ON: On Control Input. A logic low at ON enables the
LTC4361. A logic high at ON activates a low current pulldown at the GATE pin and causes the LTC4361 to enter
a low current sleep mode. An internal 5μA current pulls
ON down to ground. Connect to ground or leave open if
unused.
OUT: Output Voltage Sense Input for GATE Clamp. Connect
to the source of the external N-channel MOSFET to sense
the output voltage for GATE to OUT clamp.
PWRGD: Power Good Status. Open-drain output with
internal 500k resistive pull-up to OUT. Pulls low 65ms
after GATE ramps above VGATE(TH).
SENSE: Current Sense Input. Connect a sense resistor
between IN and SENSE. An overcurrent protection circuit
turns off the N-channel MOSFET when the voltage across
the sense resistor exceeds 50mV for more than 10μs.
GND: Device Ground.
IN: Supply Voltage Input. Connect this pin to the input
power supply. This pin has an overvoltage threshold of
5.8V. After an overvoltage event, this pin must fall below
VIN(OV) – ΔVOV to release the overvoltage lockout. During lockout, GATE is held low and the PWRGD pull-down
releases.
436112f
5
LTC4361-1/LTC4361-2
BLOCK DIAGRAM
GATEP
IN
5.8V
200k
CHARGE
PUMP
SENSE
1.8M
10μA
GATE
ON
1V
5.8V
GATE HIGH
COMPARATOR
+
–
5μA
+
–
OVERCURRENT
COMPARATOR
OUT
VGATE(TH)
+
OVERVOLTAGE
COMPARATOR
+
CONTROL
50mV
–
–
500k
+
5.8V
–
5.7V
PWRGD
GND
436112 BD
436112f
6
LTC4361-1/LTC4361-2
OPERATION
Mobile devices like cell phones and MP3/MP4 players have
highly integrated subsystems fabricated from deep submicron CMOS processes. The small form factor is accompanied
by low absolute maximum voltage ratings. The sensitive
electronics are susceptible to damage from transient or DC
overvoltage conditions from the power supply.
Failures or faults in the power adaptor can cause an overvoltage event. So can hot-plugging an AC adaptor into the
power input of the mobile device (see LTC Application Note
88). Today’s mobile devices derive their power supply or
recharge their internal batteries from multiple alternative
inputs like AC wall adaptors, car battery adaptors and USB
ports. A user may unknowingly plug in the wrong adaptor,
damaging the device with a high or even a negative power
supply voltage.
The LTC4361 protects low voltage electronics from these
overvoltage conditions by controlling a low cost external
N-channel MOSFET configured as a pass transistor. At
power-up (VIN > 2.1V), a start-up delay cycle begins. Any
overvoltage condition causes the delay cycle to continue
until a safe voltage is present. When the delay cycle
completes, an internal high side switch driver slowly
ramps up the MOSFET gate, powering up the output at
a controlled rate and limiting the inrush current to the
output capacitor.
If the voltage at the IN pin exceeds 5.8V (VIN(OV)),
GATE is pulled low quickly to protect the load. The
incoming power supply must remain below 5.7V
(VIN(OV) – ΔVOV) for the duration of the start-up delay to
restart the GATE ramp-up.
A sense resistor placed between IN and SENSE implements
an overcurrent protection with a 50mV trip threshold and
a 10μs glitch filter. After an overcurrent, the LTC4361-1
latches off while the LTC4361-2 restarts following a 130ms
delay.
The LTC4361 has a CMOS compatible ON input. When
driven low, the part is enabled. When driven high, the
external N-channel MOSFET is turned off and the supply
current of the LTC4361 drops to 1.5μA. The PWRGD pulldown releases during this low current sleep mode, UVLO,
overvoltage or overcurrent and the subsequent 130ms
start-up delay. After the start-up delay, GATE starts its
slow ramp-up and ramps higher than VGATE(TH) to trigger
a 65ms delay cycle. When that completes, PWRGD pulls
low.The LTC4361 has a GATEP pin that drives an optional
external P-channel MOSFET to provide protection against
negative voltages at IN.
436112f
7
LTC4361-1/LTC4361-2
APPLICATIONS INFORMATION
The typical LTC4361 application protects 2.5V to 5.5V
systems in portable devices from power supply overvoltage. The basic application circuit is shown in Figure 1.
Device operation and external component selection is
discussed in detail in the following sections.
VIN
5V
M1
Si1470DH
RSENSE
0.025Ω
COUT
10μF
VOUT
5V
1.5A
GATE
SENSE OUT
LTC4361
IN
ON
PWRGD
GND
436112 F01
Figure 1. Protection from Input Overvoltage and Overcurrent
The GATE ramp rate is limited to 3V/ms. VOUT follows at
a similar rate which results in an inrush current into the
load capacitor COUT of:
IINRUSH = COUT •
The servo loop is compensated by the parasitic capacitance of the external MOSFET. No further compensation
components are normally required. In the case where
the parasitic capacitance is less than 100pF, a 100pF
compensation capacitor between GATE and ground may
be required.
An even slower GATE ramp and lower inrush current
can be achieved by connecting an external capacitor, CG,
from GATE to ground. The voltage at GATE then ramps
up with a slope equal to 10μA/CG [V/s]. Choose CG using
the formula:
CG =
Start-Up
When VIN is less than the undervoltage lockout level of
2.1V, the GATE driver is held low and the PWRGD pull-down
is high impedance. When VIN rises above 2.1V and ON is
held low, a 130ms delay cycle starts. Any undervoltage or
overvoltage event at IN (VIN < 2.1V or VIN > 5.7V) restarts
the delay cycle. This delay allows the N-channel MOSFET
to isolate the output from any input transients that occur
at start-up. When the delay cycle completes, GATE starts
its slow ramp-up.
GATE Control
An internal charge pump enhances the external N-channel
MOSFET with 6V from GATE to OUT. This allows the use
of logic-level N-channel MOSFETs. An internal 6V clamp
between GATE and OUT protects the MOSFET gate.
dVGATE
= COUT • 3 [mA/µF ]
dt
10µA
IINRUSH
• COUT
Overvoltage
When power is first applied, VIN must remain below 5.7V
(VIN(OV) – ΔVOV) for more than 130ms before GATE is
ramped up to turn on the MOSFET. If VIN then rises above
5.8V (VIN(OV)), the overvoltage comparator activates the
30mA fast pull-down on GATE within 1μs. After an overvoltage condition, the MOSFET is held off until VIN once
again remains below 5.7V for 130ms.
Overcurrent
The overcurrent comparator protects the MOSFET from
excessive current. It trips when the SENSE pin falls more
than 50mV below IN for more than 10μs. When the overcurrent comparator trips, GATE is pulled low quickly and the
PWRGD pull-down releases. The LTC4361-2 automatically
tries to apply power again after a 130ms start-up delay.
436112f
8
LTC4361-1/LTC4361-2
APPLICATIONS INFORMATION
The LTC4361-1 has an internal latch that maintains this
off state until it is reset. To reset this latch, cycle IN below 2.1V (VIN(UVL)) or ON above 1.5V (VON(TH)) for more
than 500μs. After reset, the LTC4361-1 goes through the
start-up cycle.
In applications not requiring the overcurrent protection, tie
the SENSE pin to the IN pin. To implement an overcurrent
threshold ITRIP , choose RSENSE using the formula:
RSENSE =
ΔVOC
I TRIP
After choosing the RSENSE, keep in mind that:
ITRIP(MAX) =
ITRIP(MIN) =
ΔVOC(MAX)
RSENSE(MIN)
ΔVOC(MIN)
PWRGD Output
PWRGD is an active low output with a MOSFET pull-down
to ground and a 500k resistive pull-up to OUT. The PWRGD
pin pull-down releases during the low current sleep mode
(invoked by ON high), UVLO, overvoltage or overcurrent
and the subsequent 130ms start-up delay. After the startup delay, GATE starts its slow ramp-up and control of the
PWRGD pull-down passes on to the GATE high comparator.
VGATE > VGATE(TH) for more than 65ms asserts the PWRGD
pull-down and VGATE < VGATE(TH) releases the pull-down.
The PWRGD pull-down is capable of sinking up to 3mA
of current allowing it to drive an optional LED. To interface PWRGD to another I/O rail, connect a resistor from
PWRGD to the I/O rail with a resistance low enough to
override the internal 500k pull-up to OUT. Figure 2 details
PWRGD behavior for a LTC4361-2 with 1k pull-up to 5V
at PWRGD.
RSENSE(MAX)
START-UP
FROM UVLO
OV
RESTART
FROM OV
ON
OC
RESTART
FROM ON
RESTART
FROM OC
OC
THRESHOLD
ICABLE
VIN(OV)
VIN(OV)–$VOV
VIN(UVL)
IN
OUT
VGATE(TH)
VGATE(TH)
VGATE(TH)
VGATE(TH)
VGATE(TH)
GATE
ON
PWRGD
130ms
65ms
130ms
65ms
130ms
65ms
130ms
65ms
10μs (NOT TO SCALE)
436112 F02
Figure 2. PWRGD Behavior
436112f
9
LTC4361-1/LTC4361-2
APPLICATIONS INFORMATION
ON Input
ON is a CMOS compatible, active low enable input. It has
a default 5μA pull-down to ground. Connect this pin to
ground or leave open to enable normal device operation.
If it is driven high while the external MOSFET is turned on,
GATE is pulled low with a weak pull-down current (40μA)
to turn off the external MOSFET gradually, minimizing input
voltage transients. The LTC4361 then goes into a low current sleep mode, drawing only 1.5μA at IN. When ON goes
back low, the part restarts with a 130ms delay cycle.
GATEP Control
GATEP has a 2M resistive pull-down to ground and a 5.8V
Zener clamp in series with a 200k resistor to IN. It controls the gate of an optional external P-channel MOSFET
to provide negative voltage protection. The 2M resistive
pull-down turns on the MOSFET once VIN – VGATEP is
more than the MOSFET gate threshold voltage. The IN to
GATEP Zener protects the MOSFET from gate overvoltage
by clamping its VGS to 5.8V when VIN goes high.
MOSFET Configurations and Selection
The LTC4361 can be used with various external MOSFET
configurations (see Figure 3). The simplest configuration
is a single N-channel MOSFET. It has the lowest RDS(ON)
and voltage drop and is thus the most power efficient
solution. When GATE is pulled to ground, the N-channel
MOSFET can isolate OUT from a positive voltage at IN up
to the BVDSS of the N-channel MOSFET. However, reverse
current can still flow from OUT to IN via the parasitic body
diode of the N-channel MOSFET.
For near zero reverse-leakage current protection when GATE
is pulled to ground, back-to-back N-channel MOSFETs
can be used. Adding an additional P-channel MOSFET
controlled by GATEP provides negative input voltage
protection down to the BVDSS of the P-channel MOSFET.
Another configuration consists of a P-channel MOSFET
controlled by GATEP and a N-channel MOSFET controlled
by GATE. This provides protection against overvoltage and
negative voltage but not reverse current.
RSENSE
SUPPLY
IN
OVERVOLTAGE
PROTECTION
M1
OUT
SENSE
GATE
RSENSE
SUPPLY
IN
OVERVOLTAGE, REVERSECURRENT PROTECTION
M1
M3
OUT
SENSE
GATE
SUPPLY
NEGATIVE
VOLTAGE
PROTECTION
M2
RSENSE
IN
GATE
NEGATIVE
VOLTAGE
PROTECTION
M2
RSENSE
IN
GATEP
OUT
SENSE
GATEP
SUPPLY
OVERVOLTAGE, REVERSECURRENT PROTECTION
M1
M3
OVERVOLTAGE
PROTECTION
M1
OUT
SENSE
GATE
436112 F03
Figure 3. MOSFET Configurations
436112f
10
LTC4361-1/LTC4361-2
APPLICATIONS INFORMATION
WALL ADAPTOR
AC/DC
RIN
LIN
MOBILE
DEVICE
IN
ICABLE
VIN
10V/DIV
COUT
+
CABLE
LOAD
ICABLE
20A/DIV
436112 F04a
5μs/DIV
RIN = 150mΩ,
LIN = 0.7μH
LOAD = 10Ω, COUT = 10μF
436112 F04b
5μs/DIV
RIN = 150mΩ,
LIN = 0.7μH, RSENSE = 25mΩ
LOAD = 10Ω, COUT = 10μF
436112 F05b
Figure 4. 20V Hot-Plug into a 10μF Capacitor
WALL ADAPTOR
AC/DC
RIN
LIN
IN
RSENSE
M1
Si1470DH
OUT
MOBILE
DEVICE
VIN
10V/DIV
ICABLE
+
GATE
CABLE
COUT
SENSE OUT
LOAD
LTC4361
IN
VOUT
1V/DIV
ICABLE
20A/DIV
GND
436112 F05a
Figure 5. 20V Hot-Plug into the LTC4361
Input Transients
Figure 4 shows a typical setup when an AC wall adaptor
charges a mobile device. The inductor LIN represents the
lumped equivalent inductance of the cable and the EMI filter
found in some wall adaptors. RIN is the lumped equivalent
resistance of the cable, adaptor output capacitor ESR and
the connector contact resistance.
LIN and RIN form an LC tank circuit with any capacitance
at IN. If the wall adaptor is powered up first, plugging the
wall adaptor output to IN does the equivalent of applying
a voltage step to this LC circuit. The resultant voltage
overshoot at IN can rise to twice the DC output voltage
of the wall adaptor as shown in Figure 4. Figure 5 shows
the 20V adaptor output applied to the LTC4361. Due to
the low capacitance at the IN pin, the plug-in transient has
been brought down to a manageable level.
436112f
11
LTC4361-1/LTC4361-2
APPLICATIONS INFORMATION
As the IN pin can withstand up to 80V, a high voltage Nchannel MOSFET can be used to protect the system against
rugged abuse from high transient or DC voltages up to the
BVDSS of the MOSFET. Figure 6 shows a 50V input plugged
into the LTC4361 controlling a 60V rated MOSFET.
Input transients also occur when the current through the
cable inductance changes abruptly. This can happen when
the LTC4361 turns off the N-channel MOSFET rapidly in an
overvoltage or overcurrent event. Figure 7 shows an input
transient after an overcurrent. The current in LIN will cause
VIN to overshoot and avalanche the N-channel MOSFET to
COUT . Typically, IN will be clamped to a voltage of VOUT +
1.3 • (BVDSS of Si1470DH) = 45V. This is well below the
85V absolute maximum voltage rating of the LTC4361.
The single, nonrepetitive, pulse of energy (EAS) absorbed
by the MOSFET during this avalanche breakdown with a
peak current IAS is approximated by the formula:
EAS = 0.5 • LIN • IAS2
For LIN = 0.7μH and IAS = 4A, then EAS = 5.6μJ. This is within
the IAS and EAS capabilities of most MOSFET’s including
the Si1470DH. So in most instances, the LTC4361 can
ride through such transients without a bypass capacitor,
transient voltage suppressor or other external components
at IN. Note that if an IN bypass capacitor is used, the VIN
transients will overshoot less but last longer. If VIN dips
below VIN(UVL) for more than 10μs, the internal latch-off
latch in the LTC4361-1 could be inadvertently reset.
VIN
20V/DIV
VIN
20V/DIV
VOUT
5V/DIV
VGATE
10V/DIV
VOUT
1V/DIV
ICABLE
5A/DIV
ICABLE
5A/DIV
436112 F06
5μs/DIV
FDC5612
RIN = 150mΩ, LIN = 0.7μH
RSENSE = 25mΩ, LOAD = 10Ω, COUT = 10μF
Figure 6. 50V Hot-Plug into the LTC4361
436112 F07
2μs/DIV
FIGURE 5 CIRCUIT
RIN = 150mΩ, LIN = 0.7μH
RSENSE = 25mΩ, LOAD = 10Ω, COUT = 10μF
Figure 7. Overcurrent Turn-Off and Resulting Input Transient
436112f
12
LTC4361-1/LTC4361-2
APPLICATIONS INFORMATION
Figure 8 shows a particularly severe situation which can
occur in a mobile device with dual power inputs. A 20V wall
adaptor is mistakenly hot-plugged into the 5V device with
the USB input already live. As shown in Figure 9, a large
current can build up in LIN to charge up COUT . When the
N-channel MOSFET shuts off, the energy stored in LIN is
dumped into COUT, causing a large 40V input transient. The
LTC4361 limits this to a 1V rise in the output voltage.
MOSFET before VOUT overshoots to a dangerous voltage.
A larger COUT also helps to lower the ΔVOUT due to the
discharge of the energy in LIN if the MOSFET BVDSS is
used as an input clamp.
Layout Considerations
Figure 10 shows an example PCB layout for the LTC4361
(TS8 package) with a single N-channel MOSFET (SC70
package) and a 0603 size sense resistor. Keep the traces
to the N-channel MOSFET wide and short. The PCB traces
associated with the power path through the N-channel
MOSFET should have low resistance. Use Kelvin connections to RSENSE for an accurate overcurrent threshold.
If the ΔVOUT due to the discharge of the energy in LIN into
COUT is not acceptable or the avalanche capability of the
MOSFET is exceeded, an additional external clamp such
as the SMAJ24A can be placed between IN and GND. COUT
is the decoupling capacitor of the protected circuits and
its value will largely be determined by their requirements.
Using a larger COUT will work with LIN to slow down the
dV/dt at OUT, allowing time for the LTC4361 to shut off the
RIN
20V
WALL
ADAPTER
+
VIN
20V/DIV
LIN
ICABLE
IN RSENSE
–
OUT
GATE
LTC4361
SENSE
+
–
VOUT
5V/DIV
VGATE
10V/DIV
D1
B160
5V
USB
M1
Si1470DH
IN
R1
100k
COUT
ICABLE
10A/DIV
LOAD
OUT
436112 F09
1μs/DIV
FIGURE 8 CIRCUIT
RIN = 150mΩ
LIN = 2μH, RSENSE = 25mΩ, LOAD = 10Ω
COUT = 10μF (16V, SIZE 1210)
GND
436112 F08
Figure 8. Setup for Testing 20V Plugged into 5V System
Figure 9. Overvoltage Protection Waveforms
When 20V Plugged into 5V System
1
2
3
4
LTC4361
GND
4
5
6
3
Si1470DH
2
RSENSE
OUT
1
SUPPLY
8
7
6
5
IN
436112 F10
Figure 10. Layout for N-Channel MOSFET Configuration
436112f
13
LTC4361-1/LTC4361-2
PACKAGE DESCRIPTION
DC Package
8-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1719 Rev A)
0.70 p0.05
2.55 p0.05
1.15 p0.05 0.64 p0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 p 0.05
0.45 BSC
1.37 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.05
TYP
2.00 p0.10
(4 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
R = 0.115
TYP
5
8
0.40 p 0.10
0.64 p 0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.25 s 45o
CHAMFER
(DC8) DFN 0106 REVØ
4
0.200 REF
1
0.23 p 0.05
0.45 BSC
0.75 p0.05
1.37 p0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
436112f
14
LTC4361-1/LTC4361-2
PACKAGE DESCRIPTION
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637)
0.52
MAX
2.90 BSC
(NOTE 4)
0.65
REF
1.22 REF
1.4 MIN
3.85 MAX 2.62 REF
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.22 – 0.36
8 PLCS (NOTE 3)
0.65 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
1.95 BSC
TS8 TSOT-23 0802
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
436112f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC4361-1/LTC4361-2
TYPICAL APPLICATION
5V System Protected from ±24V Power Supplies and Overcurrent
VIN
5V
M2
5V System Protected from ±24V Power Supplies,
Overcurrent and Reverse Current
Si3590DV
RSENSE
0.05Ω
M1
COUT
10μF
VOUT
5V
0.5A
VIN
5V
M2
Si1471DH
FDC6561AN
RSENSE
0.05Ω
M1
VOUT
5V
0.5A
M3
COUT
10μF
GATE
GATE
SENSE
OUT
SENSE
VIO
5V
LTC4361
OUT
VIO
5V
LTC4361
IN
IN
R1
1k
GATEP
ON
D1
LN1351CTR
PWRGD
GND
R1
1k
GATEP
ON
GND
436112 TA02
D1
LN1351CTR
PWRGD
436112 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Ultralow Power Supervisor with Eight Pin-Selectable
Thresholds
500nA Quiescent Current, 2mm × 2mm 8-Lead DFN and TSOT-23 Packages
LT3008
20mA, 45V, 3μA IQ Micropower LDO
280mV Dropout Voltage, Low IQ: 3μA, VIN = 2.0V to 45V, VOUT = 0.6V to 39.5V;
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LT3009
20mA, 3μA IQ Micropower LDO
280mV Dropout Voltage, Low IQ: 3μA, VIN = 1.6V to 20V, VOUT = 0.6V to 19.5V;
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Single Channel, Low Voltage Hot Swap™ Controller
Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6
LTC4213
No RSENSE™ Electronic Circuit Breaker
Controls Load Voltages from 0V to 6V. 3 Selectable Circuit Breaker Thresholds.
Dual Level Overcurrent Fault Protection
LT4356
Surge Stopper- Overvoltage/Overcurrent Protection
Regulator
Wide Operation Range: 4V to 80V. Reverse Input Protection to –60V.
Adjustable Output Clamp Voltage
LTC4411
SOT-23 Ideal Diode
2.6A Forward Current, 28mV Regulated Forward Voltage
LTC4412
2.5V to 28V, Low Loss PowerPath™ Controller in
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More Efficient than Diode-ORing, Automatic Switching Between DC Sources,
Simplified Load Sharing
LTC4413-1/
LTC4413-2
Dual 2.6A, 2.5V to 5.5V Fast Ideal Diodes in
3mm × 3mm DFN
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436112f
16 Linear Technology Corporation
LT 0410 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
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