Philips Semiconductors Product specification 8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver FB2033 • Built-in precision band-gap reference provides accurate receiver FEATURES • 8-bit transceivers • Latched, registered or straight through in either A to B or B to A thresholds and improved noise immunity • Compatible with IEEE Futurebus+ or proprietary BTL backplanes • Each BTL driver has a dedicated Bus GND for a signal return • Controlled output ramp and multiple GND pins minimize ground path • Drives heavily loaded backplanes with equivalent load impedances down to 10Ω. bounce • High drive 100mA BTL Open Collector drivers on B-port • Allows incident wave switching in heavily loaded backplane buses • Reduced BTL voltage swing produces less noise and reduces • Glitch-free power up/power down operation • Low ICC current • Tight output skew • Supports live insertion power consumption QUICK REFERENCE DATA SYMBOL tPLH tPHL tPLH tPHL COB IOL PARAMETER Propagation delay AIn to Bn Propagation delay Bn to AOn Output capacitance (B0 – Bn only) Output current (B0 – Bn only) AIn to Bn (outputs Low or High) Supply current Bn to AOn (outputs Low) Bn to AOn (outputs High) ICC TYPICAL 3.0 3.0 4.3 4.1 6 100 UNIT ns ns pF mA 24 45 22 mA ORDERING INFORMATION COMMERCIAL RANGE VCC = 5V±10%; Tamb = 0°C to +70°C FB2033BB PACKAGES 52-pin Plastic Quad Flat Pack (QFP) NOTE: Thermal mounting or forced air is recommended DRAWING NUMBER SOT379-1 BIAS V B0 BG GND BG VCC OEA SBA0 SBA1 VCC LCAB LOGIC GND AI0 AI1 AO0 PIN CONFIGURATION 52 51 50 49 48 47 46 45 44 43 42 41 40 LOGIC GND 1 39 AO1 2 38 B1 AI2 3 37 BUS GND AO2 4 36 B2 35 BUS GND 34 B3 33 BUS GND 32 B4 31 BUS GND 8-Bit Universal Transceiver BUS GND AI3 5 AO3 6 LOOPBACK 7 AI4 8 AO4 9 AI5 10 30 B5 AO5 11 29 BUS GND AI6 12 28 B6 LOGIC GND 13 27 BUS GND FB2033 52-lead PQFP 1995 May 25 B7 OEB1 BUS GND OEB0 VCC SAB1 SAB0 LCBA VCC AO7 LGOIC GND AI7 AO6 14 15 16 17 18 19 20 21 22 23 24 25 26 SG00068 1 853-1717 15279 Philips Semiconductors Product specification 8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver FB2033 by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. DESCRIPTION The FB2033 is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level side. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two pairs of mode select inputs (SBA0 and SBA1 for B-to-A, SAB0 and SAB1 for A-to-B). It can be configured as a buffer, a register, or a D-type latch. Output clamps are provided on the BTL outputs to further reduce switching noise. The “VOH” clamp reduces inductive ringing effects during a Low-to-High transition. The “VOH” clamp is always active. The other clamp, the “trapped reflection” clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition. When configured in the buffer mode, the inverse of the input data appears at the output port. In the flip-flop mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-High latch enables. Regardless of the mode, data is inverted from input to output. To support live insertion, OEB0 is held Low during power on/off cycles to ensure glitch- free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the Loopback input. When the Loopback input is High the output of the selected A-to-B logic element (not inverted) becomes the B-to-A input. The 3-State AO port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled. When either OEB0 is Low or OEB1 is High, the B-port is inactive and is pulled to the level of the pull-up voltage. New data can be entered in the flip-flop and latched modes or can be retained while the associated outputs are in 3-State (AO port) or inactive (B port). The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble- shoot. The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port ensure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. As with any high power device thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature. The B-port interfaces to “Backplane Transceiver Logic” (see the IEEE 1194.1 BTL standard). BTL features low power consumption PIN DESCRIPTION SYMBOL PIN NUMBER TYPE NAME AND FUNCTION AI0 – AI7 50, 52, 3, 5, 8, 10, 12, 15 Input AO0 – AO7 51, 2, 4, 6, 9, 11, 14, 16 Output B0 – B7 40, 38, 36, 34, 32, 30, 28, 26 I/O OEB0 23 Input Enables the B outputs when High OEB1 24 Input Enables the B outputs when Low OEA 43 Input Enables the AO outputs when High BUS GND 39, 37, 35, 33, 31, 29, 27, 25 GND Bus ground (0V) LOGIC GND 1, 13, 17, 49 GND Logic ground (0V) VCC 18, 22, 48 Power Positive supply voltage Data inputs (TTL) 3-State outputs (TTL) Data inputs/Open Collector outputs, High current drive (BTL) BIAS V 41 Power Live insertion pre-bias pin BG VCC 44 Power Band Gap threshold voltage reference BG GND 42 GND Band Gap threshold voltage reference ground SABn 20, 21 Input Mode select from AI to B SBAn 45, 46 Input Mode select from B to AO LCAB 47 Input A-to-B clock/latch enable (transparent latch when High) LCBA 19 Input B-to-A clock/latch enable (transparent latch when High) Loopback 7 Input Enables loopback function when High (from AIn to AOn) 1995 May 25 2 Philips Semiconductors Product specification 8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver FB2033 FUNCTION TABLE INPUTS MODE AIn to Bn thru mode AIn to Bn transparent latch AIn to Bn latch and read AIn to Bn register Bn outputs latched and read (preconditioned latch) Bn to AOn thru mode Bn to AOn transparent latch Bn to AOn latch and read Bn to AOn register AOn outputs latched and read (preconditioned latch) Disable Bn outputs Disable AOn outputs OUTPUTS AIn Bn* OEB0 OEB1 OEA LCAB LCBA SAB1 SBA1 0 0 L — H L L X X LL H — H L L X X AOn Bn XX Z H** LL XX Z L L — H L L H X HX XX Z H** H — H L L H X HX XX Z L l — H L L ↓ X HX XX Z H** h — H L L ↓ X HX XX Z L L — H L L ↑ X LH XX Z H** H — H L L ↑ X LH XX Z L X — H L L L X HX XX Z latched data X L L H H X X XX LL H input X H L H H X X XX LL L input X L L H H X H XX HX H input X H L H H X H XX HX L input X l L H H X ↓ XX HX H input X h L H H X ↓ XX HX L input X L L H H X ↑ XX LH H input X H L H H X ↑ XX LH L input X X L H H X L XX HX latched data X X X L X X X X XX XX X H** X X X H X X X XX XX X H** X X X X L X X XX XX Z X FUNCTION SELECT TABLE MODE SELECTED SXX1 SXX0 L L Register mode L H Latch mode H X Thru mode NOTES: H = L = h = l = X = Z = — = ↑ = ↓ = H** = Bn* = High voltage level Low voltage level High voltage level one set-up time prior to the High-to-Low LCXX transition Low voltage level one set-up time prior to the High-to-Low LCXX transition Don’t care High-impedance (OFF) state Input not externally driven Low-to-High transition High-to-Low transition Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. NOTE: In Loopback mode (Loopback = High), AIn inputs are routed to the AOn outputs. The Bn inputs are blocked out. 1995 May 25 3 Philips Semiconductors Product specification 8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver FB2033 LOGIC DIAGRAM 23 OEB0 24 OEB1 SAB0 SAB1 LCAB AIn 20 21 47 50 D En 52, 2, 5, 8, 10, 12, 15 40 Bn 38, 36, 34, 32, 30, 28, 26 D Clk 1 of 8 cells LCBA SBA0 SBA1 OEA 19 45 46 43 D En AOn 51 2, 4, 6, 9, 11, 14, 16 D Clk 1 of 8 cells BGref Loopback 7 BGGnd 42 SG00069 1995 May 25 4 Philips Semiconductors Product specification 8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver FB2033 ABSOLUTE MAXIMUM RATINGS Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL VCC PARAMETER Supply voltage VIN Input voltage IIN Input current VOUT Current applied to output in Low output state TSTG Storage temperature UNIT -0.5 to +7.0 V All inputs except B0 – Bn -1.2 to +7.0 B0 – Bn -1.2 to +3.5 Voltage applied to output in High output state IOUT RATING V -40 to +5.0 mA -0.5 to +VCC V AO0 – AOn 48 B0 – Bn 200 -65 to +150 mA °C RECOMMENDED OPERATING CONDITIONS SYMBOL VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage IIK Input clamp current IOH High-level output current IOL Low-level output current IIA Off device input current COB Output capacitance of B port Tamb Operating free-air temperature range 1995 May 25 LIMITS PARAMETER MIN NOM MAX 4.5 5.0 5.5 Except B0 – Bn 2.0 B0 – Bn 1.62 UNIT V V 1.55 Except B0 – Bn 0.8 B0 – Bn 1.47 Except B0 – Bn -40 B0 – Bn -50 V mA AO0 – AOn -3 AO0 – AOn 24 B0 – Bn 100 Except B0 – Bn, VI = 0 to 5.5V, VCC = 0V 100 µA 7 pF +70 °C 6 0 5 mA mA Philips Semiconductors Product specification 8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver FB2033 DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range unless otherwise noted. SYMBOL TEST CONDITIONS1 PARAMETER LIMITS MIN TYP2 MAX UNIT IOH High level output current B0 – Bn VCC = MAX, VIL = MAX, VIH = MIN, VOH = 1.9V 100 µA IOFF Power-off output current B0 – Bn VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 1.9V 100 µA VOH VOL High-level output voltage Low-level output voltage 4 VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA AO0 – AOn 4 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA AO0 – AOn B0 – Bn Except B0–Bn VIK Input clamp voltage B0 – Bn II IIH Input current at maximum input voltage VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA .75 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 4mA 0.5 1.0 VCC = MIN, II = IIK VCC = MIN, II = IIK 6 V 0.5 1.15 V 0.3 -1.2 VCC = MAX, VI = 0.0V or 5.5V ±50 Except B0–Bn VCC = MAX, VI = 2.7V, Bn = AIn = 0V 20 VCC = MAX, VI = 1.9V 100 VCC = MAX, VI = 3.5V 5 V -0.5 VCC = MIN, II = -18mA High-level input current Low-level input current 2.85 Except B0–Bn B0 – Bn IIL 2.5 100 µA µA mA Except B0–Bn VCC = MAX, VI = 0.5V -20 B0 – Bn VCC = MAX, VI = 0.75V -100 µA IOZH Off-state output current AO0 – AOn VCC = MAX, VO = 2.7V 50 µA IOZL Off-state output current AO0 – AOn VCC = MAX, VO = 0.5V -50 µA IOS Short-circuit output current 3 AO0 – AOn only VCC = MAX, VO = 0.0V -150 mA AIn to Bn VCC = MAX, outputs Low or High 24 50 Bn to AOn VCC = MAX, outputs Low 45 75 Bn to AOn VCC = MAX, outputs High 22 44 ICC Supply current (total) -45 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 5. For B port input voltage between 3 and 5 volts IIH will be greater than 100µA, but the parts will continue to function normally. 6. B0 – B7 clamps remain active for a minimum of 80ns following a High-to-Low transition. 1995 May 25 6 Philips Semiconductors Product specification 8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver FB2033 LIVE INSERTION SPECIFICATIONS SYMBOL VBIASV IBIASV LIMITS PARAMETER Bias pin voltage Bias pin DC current MIN VCC = 0 to 5.25V, Bn = 0 to 2.0V NOM 4.5 MAX UNIT 5.5 V VCC = 0 to 4.75V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V 1 mA VCC = 4.5 to 5.5V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V 10 µA VBn Bus voltage during pre-bias B0 – B8 = 0V, Bias V = 5.0V ILM Fall current during pre-bias B0 – B8 = 2V, Bias V = 4.5 to 5.5V 1 µA IHM Rise current during pre-bias B0 – B8 = 1V, Bias V = 4.5 to 5.5V -1 µA IBn Peak bus current during insertion VCC = 0 to 5.25V, B0 – B8 = 0 to 2.0V, Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns 10 IOL Power up current VCC = 0 to 5.25V, OEB0 = 0.8V 100 VCC = 0 to 2.2V, OEB0 = 0 to 5V 100 tGR Input glitch rejection 1.62 VCC = 5.0V 1.0 2.1 V mA µA 1.35 ns AC ELECTRICAL CHARACTERISTICS A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, CL = 50pF, RL = 500Ω MIN TYP 100 150 Propagation delay (thru mode) Bn to AOn Waveform 1, 2 2.2 2.0 4.3 4.1 6.0 6.0 2.0 1.8 7.0 7.0 ns tPLH tPHL Propagation delay (transparent latch) Bn to AOn Waveform 1, 2 1.5 2.4 4.5 4.4 6.5 6.5 1.0 2.0 7.5 7.5 ns tPLH tPHL Propagation delay LCBA to AOn Waveform 1, 2 2.0 2.2 3.8 4.3 5.5 6.0 1.8 1.7 6.0 6.5 ns tPLH tPHL Propagation delay SBAn to AOn Waveform 1, 2 1.4 1.4 2.9 3.1 5.0 5.5 1.0 1.0 6.0 6.5 ns tPLH tPHL Propagation delay (Loopback mode) AIn to AOn Waveform 1, 2 2.0 2.0 3.8 3.9 6.0 6.0 2.8 2.3 7.0 7.0 ns tPLH tPHL Propagation delay (Loopback mode) Loopback to AOn Waveform 1, 2 1.2 1.2 3.4 3.2 5.0 5.5 1.0 1.0 6.0 6.5 ns tPZH tPZL Output enable time from High or Low OEA to AOn Waveform 5, 6 1.0 2.6 3.1 4.0 5.1 5.5 1.0 2.4 5.5 5.8 ns tPHZ tPLZ Output disable time to High or Low OEA to AOn Waveform 5, 6 1.0 1.0 3.5 3.3 5.0 4.6 1.7 1.7 5.6 5.2 ns tTLH tTHL Output transition time, AOn Port 10% to 90%, 90% to 10% Test Circuit and Waveforms 2.0 2.0 5.0 5.0 ns tSK(o) Output to output skew, A port 1 Waveform 3 0.5 1.0 1.5 ns tSK(p) Pulse skew 2 tPHL – tPLH MAX Waveform 2 0.3 1.0 1.5 ns Maximum clock frequency tPLH tPHL MIN UNIT Waveform 4 fMAX MAX Tamb = 0 to 70°C, VCC = 5V±10%, CL = 50pF, RL = 500Ω MAX 100 MHz NOTES: 1. Bn to AOn propagation delays are extended for 5 nanoseconds following B port excursions above 3.1 volts. 2. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 3. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only). 1995 May 25 7 Philips Semiconductors Product specification 8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver FB2033 AC ELECTRICAL CHARACTERISTICS (Continued) B PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, CD = 30pF, RU = 9Ω Tamb = 0 to 70°C, VCC = 5V±10%, CD = 30pF, RU = 9Ω MIN TYP MAX MIN MAX UNIT tPLH tPHL Propagation delay (thru mode) AIn to Bn Waveform 1, 2 1.2 1.0 2.9 2.9 4.3 4.4 1.0 1.0 4.8 4.6 ns tPLH tPHL Propagation delay (transparent latch) AIn to Bn Waveform 1, 2 1.4 1.0 3.1 3.3 4.5 4.8 1.0 1.0 5.1 5.1 ns tPLH tPHL Propagation delay LCAB to Bn Waveform 1, 2 2.7 2.2 4.4 5.1 5.7 6.6 2.4 2.0 6.4 7.1 ns tPLH tPHL Propagation delay SABn to Bn Waveform 1, 2 1.8 1.0 3.6 3.3 5.0 4.9 1.4 1.0 5.7 5.2 ns tPZH tPZL Enable/disable time OEB0 or OEB1 to Bn Waveform 1, 2 1.4 1.0 3.0 3.1 4.5 5.0 1.0 1.0 5.0 5.6 ns ∆V/∆t Output transition rate, Bn Port 20% to 80%, 80% to 20% Test Circuit and Waveforms 0.4 1.2 V/ns tSK(o) Output to output skew, B port 1 Waveform 3 0.8 1.5 2.0 ns tSK(p) Pulse skew 2 tPHL – tPLH MAX Waveform 2 0.3 1.5 TEST CONDITION RU = 16.5Ω SYMBOL PARAMETER ns RU = 16.5Ω UNIT tPLH tPHL Propagation delay (thru mode) AIn to Bn Waveform 1, 2 1.2 1.0 3.0 3.0 4.4 4.5 1.0 1.0 4.9 4.7 ns tPLH tPHL Propagation delay (transparent latch) AIn to Bn Waveform 1, 2 1.4 1.0 3.2 3.4 4.6 4.9 1.0 1.0 5.2 5.2 ns tPLH tPHL Propagation delay LCAB to Bn Waveform 1, 2 2.7 2.2 4.5 5.2 5.8 6.7 2.4 2.0 6.5 7.2 ns tPLH tPHL Propagation delay SABn to Bn Waveform 1, 2 1.8 1.0 3.7 3.4 5.1 5.0 1.4 1.0 5.8 5.3 ns tPZH tPZL Enable/disable time OEB0 or OEB1 to Bn Waveform 1, 2 1.4 1.0 3.1 3.2 4.6 5.1 1.0 1.0 5.1 5.7 ns ∆V/∆t Output transition rate, Bn Port 20% to 80%, 80% to 20% Test Circuit and Waveforms 0.2 0.6 V/ns tSK(o) Output to output skew, B port 1 Waveform 3 0.5 1.0 1.5 ns Waveform 2 0.3 1.0 1.5 ns tSK(p) 2 Pulse skew tPHL – tPLH MAX NOTES: 1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only). 1995 May 25 8 Philips Semiconductors Product specification 8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver FB2033 AC SETUP REQUIREMENTS LIMITS SYMBOL TEST CONDITION PARAMETER Setup time AIn to LCAB or Bn to LCBA th(H) th(L) tw(H) tw(L) UNIT CL = 50pF (A side) / CD = 30pF (B side) RL = 500Ω (A side) / RU = 9Ω (B side) MIN ts(H) ts(L) Tamb = 0 to 70°C, VCC = 5V±10% Tamb = +25°C, VCC = 5V TYP MAX MIN MAX Waveform 4 3.0 3.0 4.0 4.0 ns Hold time AIn to LCAB or Bn to LCBA Waveform 4 1.0 1.0 1.3 1.3 ns Pulse width, High or Low LCAB or LCBA Waveform 4 3.0 3.0 4.0 4.0 ns PARAMETER TEST CONDITION ts(H) ts(L) Setup time AIn to LCAB or Bn to LCBA Waveform 4 3.0 3.0 4.0 4.0 ns th(H) th(L) Hold time AIn to LCAB or Bn to LCBA Waveform 4 1.0 1.0 1.3 1.3 ns tw(H) tw(L) Pulse width, High or Low LCAB or LCBA Waveform 4 3.0 3.0 4.0 4.0 ns SYMBOL CL = 50pF (A side) / CD = 30pF (B side) RL = 500Ω (A side) / RU = 16.5Ω (B side) UNIT AC WAVEFORMS VM Input tPLH VM tPLH Output VM VM ÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍ Waveform 2. Propagation Delay for Data or Output Enable to Output AIn, Bn VM VM ts tSK(o) AOn, Bn VM tPHL Waveform 1. Propagation Delay for Data or Output Enable to Output AIn, Bn VM tPHL VM Output Input VM LCAB, LCBA VM th VM ts tw(L) tw(H) th VM 1/fMAX Waveform 3. Output to Output Skew OEA VM VM tPZH AOn Waveform 4. Setup and Hold Times, Pulse Widths and Maximum Frequency OEA tPHZ VM VOH -0.3V VM VM tPZL OV AOn Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level tPLZ VM Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. 1995 May 25 VOL +0.3V 9 SG00070 Philips Semiconductors Product specification 8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver FB2033 TEST CIRCUIT AND WAVEFORMS VCC VIN RL VOUT PULSE GENERATOR tW 90% 7.0V NEGATIVE PULSE VM VM 10% D.U.T. RT CL AMP (V) 90% RL 10% tTHL (tf) tTLH (tr) LOW V tTLH (tr) tTHL (tf) AMP (V) 90% 90% POSITIVE PULSE Test Circuit for 3-State Outputs on A Port LOW V VM = 1.55V for Bn, VM = 1.5V for all others. Input Pulse Definitions SWITCH tPLZ, tPZL All other closed open VCC BIAS V VIN 2.0V (for RU = 9 Ω) 2.1V (for RU = 16.5 Ω) VOUT PULSE GENERATOR RU D.U.T. RT Test Circuit for Outputs on B Port 1995 May 25 10% tW SWITCH POSITION TEST VM VM 10% CD INPUT PULSE REQUIREMENTS Family FB+ Amplitude Low V Rep. Rate A Port 3.0V 0.0V 1MHz 500ns 2.5ns 2.5ns B Port 2.0V 1.0V 1MHz 500ns 2.0ns 2.0ns tW tTLH tTHL DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value. SG00063 10