PHILIPS ISP1301BS

ISP1301
Universal Serial Bus On-The-Go transceiver
Rev. 01 — 14 April 2004
Product data
1. General description
The ISP1301 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver device
that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and On-The-Go
Supplement to the USB Specification Rev. 1.0a. The ISP1301 can transmit and
receive serial data at both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data
rates.
It is ideal for use in portable electronics devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application Specific Integrated Circuits (ASICs),
Programmable Logic Devices (PLDs) and any system chip set (with the USB host or
device function built-in but without the USB physical layer) to interface to the physical
layer of the USB.
The ISP1301 can interface to devices with digital I/O voltages in the range of
1.65 V to 3.6 V.
The ISP1301 is available in HVQFN24 package.
2. Features
■ Fully complies with:
◆ Universal Serial Bus Specification Rev. 2.0
◆ On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a
◆ On-The-Go Transceiver Specification (CEA–2011) Rev. 1.0
■ Can transmit and receive serial data at both full-speed (12 Mbit/s) and low-speed
(1.5 Mbit/s) data rates
■ Ideal for system ASICs or chip sets with built-in USB OTG dual-role core
■ Supports mini USB analog car kit interface
■ Supports various serial data interface protocols; transparent general-purpose
buffer mode allows you to control the direction of data transfer
■ Supports data line and VBUS pulsing session request
■ Contains Host Negotiation Protocol (HNP) command and status registers
■ Supports serial I2C-bus™ interface for OTG status and command controls
■ 2.7 V to 4.5 V power supply input range for the ISP1301
■ Built-in charge pump regulator outputs 5 V at current greater than 8 mA
■ Supports external charge pump
■ Supports wide range interfacing I/O voltage (VDD_LGC = 1.65 V to 3.6 V) for digital
control logics
ISP1301
Philips Semiconductors
USB OTG transceiver
■ 8 kV built-in electrostatic discharge (ESD) protection on the DP, DM, VBUS and ID
lines
■ Full industrial grade operation from −40 °C to +85 °C
■ Available in a small HVQFN24 (4 × 4 mm2) halogen-free and lead-free package.
3. Applications
■
■
■
■
Mobile phone
Digital camera
Personal digital assistant
Digital video recorder.
4. Abbreviations
ASIC — Application-Specific Integrated Circuit
ATX — Analog USB transceiver
HNP — Host Negotiation Protocol
ESD — ElectroStatic Discharge
I2C-bus — Inter IC-bus
IC — Integrated Circuit
OTG — On-The-Go
PDA — Personal Digital Assistant
SE0 — Single-Ended zero
SOF — Start-of-Frame
SRP — Session Request Protocol
USB — Universal Serial Bus
USB-IF — USB Implementers Forum.
5. Ordering information
Table 1:
Type
number
Ordering information
Package
Name
Description
ISP1301BS HVQFN24
plastic thermal enhanced very thin quad flat package; SOT616-1
no leads; 24 terminals; body 4 × 4 × 0.85 mm
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9397 750 11355
Product data
Version
Rev. 01 — 14 April 2004
2 of 46
ISP1301
Philips Semiconductors
USB OTG transceiver
6. Block diagram
VDD_LGC
VREG(3V3)
24
VBAT
7
20
3.3 V DC-DC
REGULATOR
C2
C1
22
21
23
VBUS
CHARGE PUMP
19
CGND
VBUS
ISP1301
SCL
SDA
ADR/PSW
INT_N
VBUS
COMPARATORS
3
2
1
5
SERIAL
CONTROLLER
OE_N/INT_N
DAT/VP
SE0/VM
RCV
VP
VM
SPEED
SUSPEND
9
14
13
12
11
10
6
ID DETECTOR
LEVEL
SHIFTER
18
PULL-UP AND
PULL-DOWN
RESISTORS
8
CARKIT
INTERRUPT
DETECTOR
15
RESET_N
ID
4
USB
TRANSCEIVER
16
DM
DP
exposed die pad
17
004aaa195
DGND
AGND
Fig 1. Block diagram.
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ISP1301
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USB OTG transceiver
7. Pinning information
VDD_LGC
CGND
C2
C1
VBAT
VBUS
7.1 Pinning
24
23
22
21
20
19
ADR/PSW
1
18
ID
SDA
2
17
AGND
SCL
3
16
DP
ISP1301BS
RESET_N
4
15
DM
INT_N
5
14
DAT/VP
SPEED
6
13
SE0/VM
7
8
9
10
11
12
RCV
VP
VM
OE_N/INT_N
SUSPEND
VREG(3V3)
004aaa542
SPEED
6
INT_N
5
RESET_N
4
VREG(3V3)
SUSPEND
OE_N/INT_N
VM
VP
RCV
Fig 2. Pin configuration HVQFN24 (top view).
7
8
9
10
11
12
DGND
(exposed die pad)
13
SE0/VM
14
DAT/VP
15
DM
16
DP
ISP1301BS
SCL
3
terminal 1
SDA
2
17
AGND
ADR/PSW
1
18
ID
24
22
21
20
19
VBUS
VBAT
C1
C2
CGND
004aaa196
VDD_LGC
Bottom view
23
Fig 3. Pin configuration HVQFN24 (bottom view).
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9397 750 11355
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ISP1301
Philips Semiconductors
USB OTG transceiver
7.2 Pin description
Table 2:
Pin description[1]
Symbol[2]
Pin
Type[3]
Reset
value
Description
ADR/PSW
1
I/O
high-Z
ADR input — sets the least-significant I2C-bus
address bit of the ISP1301; latched-on reset
(including power-on reset)
PSW output — enables or disables the external
charge pump after reset
bidirectional; push-pull input; three-state output
SDA
2
I/OD
high-Z
serial I2C-bus data input and output
SCL
3
I/OD
high-Z
serial I2C-bus clock input and output
bidirectional; push-pull input; open-drain output
bidirectional; push-pull input; open-drain output
RESET_N
4
I
-
asynchronous reset; active LOW
push-pull input
INT_N
5
OD
high-Z
interrupt output; active LOW
SPEED
6
I
-
speed selection input for the ATX; effective when
bit SPD_SUSP_CTRL = 0:
open-drain output
•
•
LOW: low-speed
HIGH: full-speed.
push-pull input
VREG(3V3)
7
P
-
output of the internal voltage regulator; an
external decoupling capacitor of 0.1 µF is
required
SUSPEND
8
I
-
suspend selection input for ATX; effective when
bit SPD_SUSP_CTRL = 0:
•
•
LOW: normal operating
HIGH: suspend.
push-pull input
OE_N/
INT_N
9
I/O
high-Z
OE_N input — enable driving DP and DM when
in the USB mode
INT_N output — interrupt (push pull) when
suspended and bit OE_INT_EN = 1
bidirectional; push-pull input; three-state output
VM
10
O
-
single-ended DM receiver output
VP
11
O
-
single-ended DP receiver output
push-pull output
push-pull output
RCV
12
O
0
differential receiver output; reflects the
differential value of DP and DM
push-pull output
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9397 750 11355
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ISP1301
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USB OTG transceiver
Table 2:
Pin description[1]…continued
Symbol[2]
Pin
Type[3]
Reset
value
Description
SE0/VM
13
I/O
-[4]
SE0 (input and output) — SE0 function in
DAT_SE0 USB mode
VM (input and output) — VM function in
VP_VM USB mode
bidirectional; push-pull input; three-state output
DAT/VP
14
I/O
-[4]
DAT (input and output) — DAT function in
DAT_SE0 USB mode
VP (input and output) — VP function in VP_VM
USB mode
bidirectional; push-pull input; three-state output
DM
15
AI/O
-
USB data minus pin (D−)
DP
16
AI/O
-
USB data plus pin (D+)
AGND
17
P
-
analog ground
ID
18
AI/O
-
identification detector input and output;
connected to the ID pin of the USB mini
receptacle
VBUS
19
AI/O
-
VBUS line input and output of the USB interface;
place an external decoupling capacitor of 0.1 µF
close to this pin
VBAT
20
P
-
supply voltage (2.7 V to 4.5 V)
C1
21
AI/O
-
charge pump capacitor pin 1; typically use a
100 nF capacitor between pins C1 and C2
C2
22
AI/O
-
charge pump capacitor pin 2; typically use a
100 nF capacitor between pins C1 and C2
CGND
23
P
-
ground for the charge pump
VDD_LGC
24
P
-
supply voltage for the interface logic signals
(1.65 V to 3.6 V)
DGND
exposed P
die pad
-
digital ground
[1]
[2]
[3]
[4]
A detailed description of these pins can be found in Section 8.9.
Symbol names ending with underscore N (for example, NAME_N) indicate active LOW signals.
I = input; O = output; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output;
P = power or ground pin.
High-Z when pin OE_N/INT_N is LOW. Driven LOW when pin OE_N/INT_N is HIGH.
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ISP1301
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USB OTG transceiver
8. Functional description
8.1 Serial controller
The serial controller includes the following functions:
•
•
•
•
•
•
I2C-bus slave interface
Interrupt generator
Mode Control registers
OTG registers
Interrupt related registers
Device identification registers.
The serial controller acts as an I2C-bus slave, and uses the SCL and SDA pins to
communicate with the OTG controller.
For more details on serial controller, see Section 11.
8.2 VBUS charge pump
The charge pump supplies current to the VBUS line. It can operate in any of the
following modes:
• Output 5 V at current greater than 8 mA
• Pull-up VBUS to 3.3 V through a resistor (RVBUS(PU)) for initiating VBUS pulsing SRP
• Pull-down VBUS to ground through a resistor (RVBUS(PD)) for discharging VBUS
before initiating SRP.
8.3 VBUS comparators
VBUS comparators provide indications regarding the voltage level on VBUS.
8.3.1
VBUS valid comparator
This comparator is used by an A-device to determine whether or not the voltage on
VBUS is at a valid level for operation. The minimum threshold for the VBUS valid
comparator is 4.4 V. Any voltage on VBUS below this threshold is considered to be a
fault. During power up, it is expected that the comparator output will be ignored.
8.3.2
Session valid comparator
The session valid comparator is a TTL-level input that determines when VBUS is high
enough for a session to start. Both the A-device and the B-device use this comparator
to detect when a session is being started. The A-device also uses this comparator to
indicate when a session is completed. The session valid threshold of the ISP1301 is
between 0.8 V and 2.0 V.
8.3.3
Session end comparator
The session end comparator determines when VBUS is below the B-device session
end threshold of 0.2 V to 0.8 V.
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ISP1301
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USB OTG transceiver
8.4 ID detector
In either the active or suspended power mode, the ID detector senses the condition of
the ID line and differentiates between the following three conditions:
• Pin ID is floating; bit ID_FLOAT = 1
• Pin ID is shorted to ground; bit ID_GND = 1
• Pin ID is connected to ground through resistor RACC_ID; bit ID_FLOAT = 0 and bit
ID_GND = 0.
The ID detector also has a switch that can be used to ground pin ID. This switch is
controlled by bit ID_PULLDOWN in the serial controller.
8.5 Pull-up and pull-down resistors
The pull-up and pull-down resistors include the following switchable resistors:
•
•
•
•
Pin DP pull-up
Pin DP pull-down
Pin DM pull-up
Pin DM pull-down.
The pull-up resistor is a context variable as described in the ECN_27%_Resistor
document. The variable pull-up resistor hardware is implemented to meet the USB
ECN_27% specification.
8.6 USB transceiver (ATX)
The behavior of the USB transceiver depends on the operation mode of the ISP1301:
• In the USB mode, the USB transceiver block performs USB full-speed or
low-speed transceiver functions. This includes differential driver, differential
receiver and single-ended receivers.
• In the transparent general purpose buffer mode or the UART mode, the USB
transceiver block functions as a level shifter between the pins DAT/VP and SE0/VM
and the pins DP and DM.
8.7 3.3 V DC-DC regulator
The built-in 3.3 V DC-DC regulator conditions the supply voltage (VBAT) for use in the
ISP1301:
• VBAT = 3.6 V to 4.5 V: the regulator will output 3.3 V ± 10 %
• VBAT < 3.6 V: the regulator will be bypassed.
The output of the regulator can be monitored on the VREG(3V3) pin.
8.8 Car kit interrupt detector
The car kit interrupt detector is a comparator that detects when the DP line is below
the car kit interrupt threshold VPH_CR_INT (0.4 V to 0.6 V). The car kit interrupt
detector is enabled in the audio mode only (bit AUDIO_EN = 1).
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ISP1301
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USB OTG transceiver
8.9 Detailed description of pins
8.9.1
ADR/PSW
The ADR/PSW pin has two functions. On reset (including power-on reset), the level
on this pin is latched as ADR_REG, which represents the least significant bit (LSB) of
the I2C address of the ISP1301. If bit ADR_REG = 0, the I2C-bus address for the
ISP1301 is 0101100 (0x2C); if bit ADR_REG = 1, the I2C-bus address for the
ISP1301 is 0101101 (0x2D).
After reset, the ADR/PSW pin can be programmed as an output. If in the Mode
Control 2 register bit PSW_OE = 1, then the ADR/PSW output will be enabled. The
logic level will be determined by bit ADR_REG. If bit ADR_REG = 0, then the
ADR/PSW pin will drive HIGH. If bit ADR_REG = 1, then the ADR/PSW pin will drive
LOW.
The ADR/PSW pin can be used to turn on or off the external charge pump. The
ISP1301 built-in charge pump supports VBUS current at 8 mA. If the application needs
more current support (for example, 50 mA), an external charge pump may be
needed. In this case, the ADR/PSW pin can act as a power switch for the external
charge pump. Figure 4 shows an example of using external charge pump.
+3.3 V
100 kΩ
VBAT
ADR/PSW
VIN
VOUT
VBUS
4.7 µF
CHARGE PUMP
ISP1301
ID
DM
DP
VBUS
ON/OFF
GND
004aaa437
Fig 4. Using external charge pump.
8.9.2
SCL and SDA
The SCL (serial clock) and SDA (serial data) signals implement a two-wire serial
I2C-bus.
8.9.3
RESET_N
Active LOW asynchronous reset for all digital logic. Either connect this pin to VDD_LGC
for power-on reset or apply a minimum of 10 µs LOW pulse for hardware reset.
8.9.4
INT_N
The INT_N (interrupt) pin is asserted while an interrupt condition exists. It is
deasserted when the Interrupt Latch register is cleared. The INT_N pin is open-drain,
and, therefore, can be connected using a wired-AND with other interrupt signals.
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USB OTG transceiver
8.9.5
OE_N/INT_N
Pin OE_N/INT_N is normally an input to the ISP1301.
When bit TRANSP_EN = 0 and bit UART_EN = 0, the OE_N/INT_N pin controls the
direction of DAT/VP, SE0/VM, DP and DM as indicated in Table 4.
When suspended (either pin SUSPEND = HIGH or bit SUSPEND_REG = 1) and bit
OE_INT_EN = 1, pin OE_N/INT_N becomes a push-pull output (active LOW) to
indicate the interrupt condition.
8.9.6
SE0/VM, DAT/VP, RCV, VM and VP
The ISP1301 transmits USB data on the USB line under the following conditions:
• Bit TRANSP_EN = 0
• Bit UART_EN = 0
• Pin OE_N/INT_N = LOW.
Table 10 shows the operation of the SE0/VM and DAT/VP pins during the transmit
operation. The RCV pin is not used during transmit.
The ISP1301 receives USB data from the USB line under the following conditions:
• Bit TRANSP_EN = 0
• Bit UART_EN = 0
• Pin OE_N/INT_N = HIGH.
Table 12 shows the operation of the SE0/VM, DAT/VP and RCV pins during the
receive operation.
The VP and VM pins are single-ended receiver outputs of the DP and DM pins,
respectively.
8.9.7
DP and DM
The DP (data plus) and DM (data minus) pins implement the USB data signals. When
in the transparent general-purpose buffer mode, the ISP1301 operates as a level
shifter between the (DAT/VP, SE0/VM) and (DP, DM) pins.
8.9.8
ID
The ID (identification) pin is connected to the ID pin on the USB mini receptacle. An
internal pull-up resistor (to VREG(3V3)) is connected to this pin. When bit
ID_PULLDOWN is set, the ID pin will be shorted to ground.
8.9.9
VBUS
This pin acts as an input to the VBUS comparator or an output from the charge pump.
When the VBUS_DRV bit of the OTG Control register is asserted, the ISP1301 tries
to drive VBUS to a voltage of 4.4 V to 5.25 V with an output current capability of at
least 8 mA.
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ISP1301
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USB OTG transceiver
8.9.10
VBAT
This pin is an input and supplies power to the ISP1301. The ISP1301 operates when
VBAT is between 2.7 V and 4.5 V.
8.9.11
C1 and C2
The C1 and C2 pins are for connecting the flying capacitor of the charge pump. The
output current capacity of the charge pump depends on the value of the capacitor.
For maximum efficiency, place capacitors as close as possible to the pins.
C1
Cext
C2
ISP1301
VBUS
IL
004aaa278
Fig 5. Charge pump capacitor.
Table 3:
IL (max)[1]
47 nF
8 mA
100 nF
18 mA[2]
[1]
[2]
8.9.12
Recommended charge pump capacitor value
Cext
For output voltage VBUS > 4.7 V (bit VBUS_VLD = 1).
For VBAT = 3.0 V to 4.5 V.
VDD_LGC
This pin is an input and sets logic thresholds. It also powers the pads of the following
logic pins:
•
•
•
•
•
•
•
•
•
8.9.13
ADR/PSW
DAT/VP, SE0/VM and RCV
VM and VP
INT_N
OE_N/INT_N
RESET_N
SPEED
SUSPEND
SCL and SDA.
AGND, CGND and DGND
AGND, CGND and DGND are ground pins for analog, charge pump and digital
circuits, respectively. These pins can be connected separately or together depending
on the system performance requirements.
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USB OTG transceiver
9. Modes of operation
There are four types of modes in the ISP1301:
•
•
•
•
Power modes
Direct I2C-bus mode
USB modes
Transparent modes.
9.1 Power modes
The power modes of the ISP1301 are as follows:
• Active power mode: power is on.
• USB suspend mode: to reduce power consumption, the USB differential receiver is
powered down.
• Global power-down mode: set bit GLOBAL_PWR_DN = 1 of the Mode Control 2
register; the differential transmitter and receiver, clock generator, charge pump,
and all biasing circuits are turned off to reduce power consumption to the minimum
possible; for details on waking up the clock, see Section 12.
9.2 Direct I2C-bus mode
In the direct I2C-bus mode, an external I2C-bus master (OTG controller) directly
communicates with the serial controller through the SCL and SDA lines. The serial
controller has a built-in I2C-bus slave function.
In this mode, an external I2C-bus master can access the internal registers of the
device (Status, Control, Interrupt, and so on) through the I2C-bus interface.
The supported I2C-bus bit rate is 100 kbit/s (maximum).
The ISP1301 is in the direct I2C-bus mode when either bit TRANSP_EN bit = 0 or pin
OE_N/INT_N is deasserted.
9.3 USB modes
The four USB modes of the ISP1301 are:
•
•
•
•
VP_VM unidirectional mode
VP_VM bidirectional mode
DAT_SE0 unidirectional mode
DAT_SE0 bidirectional mode.
In the VP_VM USB mode, the DAT/VP pin is used for the VP function, the SE0/VM
pin is used for the VM function, and the RCV pin is used for the RCV function.
In the DAT_SE0 USB mode, the DAT/VP pin is used for the DAT function, the SE0/VM
pin is used for the SE0 function, and the RCV pin is not used.
In the unidirectional mode, the DAT/VP and SE0/VM pins are always inputs. In the
bidirectional mode, the direction of these signals depends on the OE_N/INT_N input.
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USB OTG transceiver
Table 6 specifies the functionality of the device during the four USB modes.
The ISP1301 is in the USB mode when both the TRANSP_EN and UART_EN bits
are cleared.
9.4 Transparent modes
9.4.1
Transparent general-purpose buffer mode
In the transparent general-purpose buffer mode, the DAT/VP and SE0/VM pins are
connected to the DP and DM pins, respectively. Using bits TRANSP_BDIR1 and
TRANSP_BDIR0 of the Mode Control 2 register as specified in Table 8, you can
control the direction of data transfer. The ISP1301 is in the transparent
general-purpose buffer mode if bit TRANSP_EN = 1 and bit DAT_SE0 = 1.
9.4.2
Transparent UART mode
When in the transparent UART mode, the ATX behaves as two logic level translator
between the following pins:
• For TxD signal: from SE0/VM (VDD_LGC level) to DM (+3.3 V level)
• For RxD signal: from DP (+3.3 V level) to DAT/VP (VDD_LGC level).
In the UART mode, the OTG controller is allowed to connect a UART to the DAT/VP
and SE0/VM pins of the ISP1301.
The UART mode is entered by setting the UART_EN bit in the Mode Control 1
register. The UART mode is equivalent to one of the transparent general purpose
buffer mode (bit TRANSP_BDIR1 = 1, bit TRANSP_BDIR0 = 0).
9.4.3
Table 4:
Summary tables
Device operating modes
Mode
USB
Bit
suspend
DAT
condition[1] _SE0
Pin
OE_N/
INT_N
Bit
Bit
TRANSP UART
_EN
_ EN
Description
Direct I2C-bus mode
Direct I2C-bus mode
X
X
X
0
X
X
X
HIGH
1
X
X
1
X
1
X
USB modes
USB suspend mode
1
X
X
0
0
see Table 5 and Table 7
USB functional mode
0
X
X
0
0
ATX is fully functional; see Table 6
Transparent general-purpose
buffer mode
X
1
X
1
0
ATX is not functional; see Table 8
Transparent UART mode
X
X
X
X
1
DAT/VP <= DP (RxD signal of UART)
Transparent modes
SE0/VM => DM (TxD signal of UART);
ATX is not functional
[1]
Conditions:
a) bit SPD_SUSP_CTRL = 0 and pin SUSPEND = HIGH, or
b) bit SPD_SUSP_CTRL = 1 and bit SUSPEND_REG = 0.
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ISP1301
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USB OTG transceiver
Table 5:
Pin
Function
DP as output
can be driven if pin OE_N/INT_N is active LOW, otherwise high-Z[1]
DM as output
can be driven if pin OE_N/INT_N is active LOW, otherwise high-Z[1]
VBUS
can be driven depending on bit VBUS_DRV
SCL
connected to SCL I/O of the I2C-bus slave
SDA
connected to SDA I/O of the I2C-bus slave
[1]
Table 6:
In the USB suspend mode, the ISP1301 can drive the DP and DM lines, if the OE_N/INT_N input
(when the OE_INT_EN bit is not set) is LOW. In such a case, these outputs are driven as in the USB
functional modes, but with the full-speed characteristics, irrespective of the value of the SPEED input
pin or the SPEED_REG bit.
USB functional modes: I/O values[1]
USB mode
VP_VM
DAT_SE0
Bit
Pin
DAT_SE0
BI_DI
OE_N/
INT_N
DAT/VP
SE0/VM
VP
VM
RCV
unidirectional
0
0
X
TxD+[2]
TxD−[2]
RxD+[3]
RxD−[3]
RxD[3]
bidirectional
0
1
LOW
TxD+[2]
TxD−[2]
0
1
HIGH
RxD+[3]
RxD−[3]
1
0
X
TxD[4]
FSE0[5]
FSE0[5]
RSE0[7]
unidirectional
bidirectional
[1]
[2]
[3]
[4]
[5]
[6]
[7]
USB suspend mode: I/O
1
1
LOW
TxD[4]
1
1
HIGH
RxD[6]
Some of the modes and signals are provided to achieve backward compatibility with IP cores.
TxD+ and TxD− are single-ended inputs for driving the DP and DM outputs, respectively, in the single-ended mode.
RxD+ and RxD− are the outputs of the single-ended receivers connected to DP and DM, respectively.
TxD is the input for driving DP and DM in the DAT_SE0 mode.
FSE0 is for forcing an SE0 on the DP and DM lines in the DAT_SE0 mode.
RxD is the output of the differential receiver.
RSE0 is an output indicating that an SE0 has been received on the DP and DM lines.
Table 7:
USB suspend mode: I/O values
USB suspend mode Input pin
DAT_SE0
(bit DAT_SE0 = 1)
VP_VM
(bit DAT_SE0 = 0)
Output pin
DP
DM
DAT/VP
SE0/VM
VP
VM
RCV
LOW
LOW
LOW
HIGH
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
HIGH
LOW
LOW
LOW
HIGH
LOW
HIGH
HIGH
HIGH
LOW
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
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Table 8:
Transparent general-purpose buffer mode
Bit
Direction of the data flow
TRANSP_BDIR[1:0]
00
DAT/VP => DP
SE0/VM => DM
01
DAT/VP => DP
SE0/VM <= DM
10
DAT/VP <= DP
SE0/VM => DM
11
DAT/VP <= DP
SE0/VM <= DM
10. USB transceiver
10.1 Differential driver
The operation of the driver is described in Table 9. The register bits and the pins used
in the column heading are described in Section 11.1 and Section 8.9, respectively.
Table 9:
Transceiver driver operation setting
Suspend[1]
Bit
Pin
TRANSP_ OE_N/
EN
INT_N
Bit
DAT_SE0
Differential driver
0
0
LOW
0
output value from DAT/VP to DP and
SE0/VM to DM
0
0
LOW
1
output value from DAT/VP to DP and DM
if SE0/VM is 0; otherwise, drive both DP
and DM LOW
1
0
LOW
X
output value from DAT/VP to DP and DM
X
X
HIGH
X
high-Z
X
1
X
X
high-Z
[1]
Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit.
Table 10:
USB mode
DAT_SE0
VP_VM
USB functional mode: transmit operation
Input pin
Output pin
DAT/VP
SE0/VM
DP
DM
LOW
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
10.2 Differential receiver
Table 11 describes the operation of the differential receiver. The register bits and the
pins used in the column heading are described in Section 11.1 and Section 8.9,
respectively.
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The detailed behavior of the receive transceiver operation is given in Table 12.
Table 11:
Differential receiver operation settings
Suspend[1]
Bit
TRANSP_EN
Pin
OE_N/INT_N
1
X
X
X
0
X
X
LOW
X
0
X
1
X
X
0
0
0
HIGH
1
output differential value from DP
and DM to DAT/VP and RCV
0
0
HIGH
0
output differential value from DP
and DM to RCV
[1]
Differential receiver
Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit.
Table 12:
USB mode
USB functional mode: receive operation
Suspend[1]
Input pin
Output pin
DP
DM
DAT/VP
SE0/VM
RCV
DAT_SE0
0
LOW
LOW
RCV
HIGH
last value of RCV
DAT_SE0
0
HIGH
LOW
HIGH
LOW
HIGH
DAT_SE0
0
LOW
HIGH
LOW
LOW
LOW
DAT_SE0
0
HIGH
HIGH
RCV
LOW
last value of RCV
DAT_SE0
1
LOW
LOW
LOW
HIGH
LOW
DAT_SE0
1
HIGH
LOW
HIGH
LOW
LOW
DAT_SE0
1
LOW
HIGH
LOW
LOW
LOW
DAT_SE0
1
HIGH
HIGH
HIGH
LOW
LOW
VP_VM
0
LOW
LOW
LOW
LOW
last value of RCV
VP_VM
0
HIGH
LOW
HIGH
LOW
HIGH
VP_VM
0
LOW
HIGH
LOW
HIGH
LOW
VP_VM
0
HIGH
HIGH
HIGH
HIGH
last value of RCV
VP_VM
1
LOW
LOW
LOW
LOW
LOW
VP_VM
1
HIGH
LOW
HIGH
LOW
LOW
VP_VM
1
LOW
HIGH
LOW
HIGH
LOW
VP_VM
1
HIGH
HIGH
HIGH
HIGH
LOW
[1]
Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit.
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DAT_SE0
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USB OTG transceiver
11. Serial controller
11.1 Register map
Table 13 provides an overview of the serial controller registers.
Table 13:
Serial controller registers
Register
Width
(bits)
Access[1] Memory address Functionality
Vendor ID
16
R
00–01H
Product ID
16
R
02–03H
Version ID
16
R
14–15H
Mode Control 1
8
R/S/C
Set — 04H
Reference
device identification registers Section 11.1.1 on page 17
mode control registers
Section 11.1.2 on page 18
OTG registers
Section 11.1.3 on page 19
interrupt related registers
Section 11.1.4 on page 20
Clear — 05H
Mode Control 2
8
R/S/C
Set — 12H
Clear — 13H
OTG Control
8
R/S/C
Set — 06H
OTG Status
8
R
10H
Interrupt Source
8
R
08H
Interrupt Latch
8
R/S/C
Set — 0AH
Interrupt Enable Low
8
R/S/C
Set — 0CH
Clear — 07H
Clear — 0BH
Clear — 0DH
Interrupt Enable High
8
R/S/C
Set — 0EH
Clear — 0FH
[1]
The R/S/C access type represents a field that can be read, set or cleared (set to 0). A register can be read from either of the indicated
addresses—set or clear. Writing logic 1 to the set address causes the associated bit to be set. Writing logic 1 to the clear address
causes the associated bit to be cleared. Writing logic 0 to an address has no effect.
11.1.1
Device identification registers
Vendor ID register (Read: 00H–01H): Table 14 provides the bit allocation of the
Vendor ID register.
Table 14:
Vendor ID register: bit description
Bit
Symbol
Access
Value
Description
15 to 0
VENDORID
[15:0]
R
04CCH
Philips Semiconductors’ Vendor ID
Product ID register (Read: 02H–03H): The bit allocation of this register is given in
Table 15.
Table 15:
Product ID register: bit description
Bit
Symbol
Access
Value
Description
15 to 0
PRODUCTID
[15:0]
R
1301H
Product ID of the ISP1301
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Version ID register (Read: 14H–15H): Table 16 shows the bit allocation of this
register.
Table 16:
11.1.2
Version ID register: bit description
Bit
Symbol
Access
Value
Description
15 to 0
VERSIONID
[15:0]
R
0210H
Version number of the ISP1301
Mode control registers
Mode Control 1 register (Set/Clear: 04H/05H): The bit allocation of the Mode
Control 1 register is given in Table 17.
Table 17:
Mode Control 1 register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
UART_EN
OE_INT_
EN
BDIS_
ACON_EN
TRANSP_
EN
DAT_SE0
SUSPEND
_REG
SPEED_
REG
Reset
-
0
0
0
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Access
Table 18:
Mode Control 1 register: bit description
Bit
Symbol
Description
7
-
reserved
6
UART_EN
When set, the ATX is in the transparent UART mode.
5
OE_INT_EN
When set and when in the suspend mode, pin OE_N/INT_N
becomes an output and is asserted when an interrupt occurs.
4
BDIS_ACON_EN
Enables the A-device to connect if the B-device disconnect is
detected; see Section 11.3
3
TRANSP_EN
When set, the ATX is in the transparent mode.
2
DAT_SE0
0 — VP_VM mode
1
SUSPEND_REG
1 — DAT_SE0 mode; see Table 6 and Table 7
Sets the ISP1301 in the suspend mode, if bit
SPD_SUSP_CTRL = 1.
0 — active-power mode
1 — USB suspend mode
0
SPEED_REG
Sets the rise time and the fall time of the transmit driver in
USB modes, if bit SPD_SUSP_CTRL = 1.
0 — USB low-speed mode
1 — USB full-speed mode
Mode Control 2 register (Set/Clear: 12H/13H): For the bit allocation of this register,
see Table 19.
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Table 19:
Mode Control 2 register: bit allocation
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
EN2V7
PSW_OE
AUDIO_EN
TRANSP_
BDIR1
TRANSP_
BDIR0
BI_DI
SPD_SUSP
_CTRL
GLOBAL_
PWR_DN
0
0
0
0
0
1
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 20:
Mode Control 2 register: bit description
Bit
Symbol
Description
7
EN2V7
0 — VBAT = 3.0 V to 4.5 V
1 — VBAT = 2.7 V to 4.5 V
6
PSW_OE
0 — ADR/PSW pin acts as an input
1 — ADR/PSW pin is driven
5
AUDIO_EN
0 — SE receiver is enabled; cr_int detector is disabled
1 — SE receiver is turned off (pin VP = LOW, pin VM = LOW);
cr_int detector is enabled
4 to 3
TRANSP_BDIR[1:0] controls the direction of data transfer in the transparent
general-purpose buffer mode; see Table 8
2
BI_DI
0 — direction of DAT/VP and SE0/VM are fixed (transmit only)
1 — direction of DAT/VP and SE0/VM are controlled by
pin OE_N/INT_N; see Table 6
1
SPD_SUSP_CTRL
control of speed and suspend in USB modes:
0 — controlled by pins SPEED and SUSPEND
1 — controlled by bit SPEED_REG and bit SUSPEND_REG
of the Mode Control 1 register
0
GLOBAL_PWR_DN 0 — normal operation
1 — sets the ISP1301 to the power down mode
Activities on the I2C-bus or any OTG event can wake up the
chip; see Section 12
11.1.3
OTG registers
OTG Control register (Set/Clear: 06H/07H): Table 21 provides the bit allocation of
the OTG Control register.
Table 21:
OTG Control register: bit allocation
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
VBUS_
CHRG
VBUS_
DISCHRG
VBUS_
DRV
ID_PULL
DOWN
DM_PULL
DOWN
DP_PULL
DOWN
DM_PULL
UP
DP_PULL
UP
0
0
0
0
1
1
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
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Table 22:
OTG Control register: bit description
Bit
Symbol
Description
7
VBUS_CHRG
charge VBUS through a resistor to 3.3 V
6
VBUS_DISCHRG
discharge VBUS through a resistor to ground
5
VBUS_DRV
drive VBUS to 5 V through the charge pump
4
ID_PULLDOWN
connect the ID pin to ground
3
DM_PULLDOWN
connect DM pull-down resistor to ground
2
DP_PULLDOWN
connect DP pull-down resistor to ground
1
DM_PULLUP
connect DM pull-up resistor to 3.3 V
0
DP_PULLUP
connect DP pull-up resistor to 3.3 V
OTG Status register (Read: 10H): Table 23 shows the bit allocation of the OTG
Status register.
Table 23:
OTG Status register: bit allocation
Bit
Symbol
7
6
B_SESS_
VLD
B_SESS_
END
5
4
3
2
1
0
reserved
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 24:
11.1.4
OTG Status register: bit description
Bit
Symbol
Description
7
B_SESS_VLD
set when the VBUS voltage is above the B-device session valid
threshold (2.0 V to 4.0 V)
6
B_SESS_END
set when the VBUS voltage is below the B-device session end
threshold (0.2 V to 0.8 V)
5 to 0
-
reserved
Interrupt related registers
Interrupt Source register (Read: 08H): This register indicates the current state of
the signals that can generate an interrupt. The bit allocation of the Interrupt Source
register is given in Table 25.
Table 25:
Interrupt Source register: bit allocation
Bit
7
6
5
4
3
2
CR_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Symbol
0
SESS_VLD VBUS_VLD
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Table 26:
Interrupt Source register: bit description
Bit
Symbol
Description
7
CR_INT
DP pin is above the car kit interrupt threshold (0.4 V to 0.6 V)
6
BDIS_ACON
set when bit BDIS_ACON_EN is set, and the ISP1301 asserts bit
DP_PULLUP after detecting the B-device disconnect
5
ID_FLOAT
ID pin is floating
4
DM_HI
DM pin is HIGH
3
ID_GND
ID pin is connected to ground
2
DP_HI
DP pin is HIGH
1
SESS_VLD
session valid comparator; threshold = 0.8 V to 2.0 V
0
VBUS_VLD
A-device VBUS valid comparator; threshold > 4.4 V
Interrupt Latch register (Set/Clear: 0AH/0BH): This register indicates the source
that generated the interrupt. The bit allocation of the Interrupt Latch register is given
in Table 27.
Table 27:
Interrupt Latch register: bit allocation
Bit
Symbol
Reset
Access
7
6
5
4
3
2
CR_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
1
0
SESS_VLD VBUS_VLD
0
0
0
0
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 28:
Interrupt Latch register: bit description
Bit
Symbol
Description
7
CR_INT
interrupt for CR_INT status change
6
BDIS_ACON
interrupt for BDIS_ACON status change
5
ID_FLOAT
interrupt for ID_FLOAT status change
4
DM_HI
interrupt for DM_HI status change
3
ID_GND
interrupt for ID_GND status change
2
DP_HI
interrupt for DP_HI status change
1
SESS_VLD
interrupt for SESS_VLD status change
0
VBUS_VLD
interrupt for VBUS_VLD status change
Interrupt Enable Low register (Set/Clear: 0CH/0DH): This register enables
interrupts on transition from true to false. For the bit allocation of this register, see
Table 29.
Table 29:
Interrupt Enable Low register: bit allocation
Bit
Symbol
Reset
Access
7
6
5
4
3
2
CR_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
0
0
0
0
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
0
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Table 30:
Interrupt Enable Low register: bit description
Bit
Symbol
Description
7
CR_INT
interrupt enable for CR_INT status change from 1 to 0
6
BDIS_ACON
interrupt enable for BDIS_ACON status change from 1 to 0
5
ID_FLOAT
interrupt enable for ID_FLOAT status change from 1 to 0
4
DM_HI
interrupt enable for DM_HI status change from 1 to 0
3
ID_GND
interrupt enable for ID_GND status change from 1 to 0
2
DP_HI
interrupt enable for DP_HI status change from 1 to 0
1
SESS_VLD
interrupt enable for SESS_VLD status change from 1 to 0
0
VBUS_VLD
interrupt enable for VBUS_VLD status change from 1 to 0
Interrupt Enable High register (Set/Clear: 0EH/0FH): The Interrupt Enable High
register enables interrupts on transition from FALSE to TRUE. Table 31 provides the
bit allocation of this register.
Table 31:
Interrupt Enable High register: bit allocation
Bit
Symbol
Reset
Access
7
6
5
4
3
2
CR_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
1
0
SESS_VLD VBUS_VLD
0
0
0
0
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 32:
Interrupt Enable High register: bit description
Bit
Symbol
Description
7
CR_INT
interrupt enable for CR_INT status change from 0 to 1
6
BDIS_ACON
interrupt enable for BDIS_ACON status change from 0 to 1
5
ID_FLOAT
interrupt enable for ID_FLOAT status change from 0 to 1
4
DM_HI
interrupt enable for DM_HI status change from 0 to 1
3
ID_GND
interrupt enable for ID_GND status change from 0 to 1
2
DP_HI
interrupt enable for DP_HI status change from 0 to 1
1
SESS_VLD
interrupt enable for SESS_VLD status change from 0 to 1
0
VBUS_VLD
interrupt enable for VBUS_VLD status change from 0 to 1
11.2 Interrupts
Table 26 indicates the signals that can generate interrupts. Any of the signals given in
Table 26 can generate an interrupt when the signal becomes either LOW or HIGH.
After an interrupt has been generated, the OTG controller should be able to read the
status of each signal and the bit that indicates whether or not that signal generated
the interrupt.
A bit in the Interrupt Latch register is set when any of these occurs:
• Writing logic 1 to its set address causes the corresponding bit to be set
• The corresponding bit in the Interrupt Enable High register is set, and the
associated signal changes from LOW to HIGH
• The corresponding bit in the Interrupt Enable Low register is set, and the
associated signal changes from HIGH to LOW.
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The Interrupt Latch register bit is cleared by writing logic 1 to its clear address.
11.3 Autoconnect
The Host Negotiation Protocol (HNP) in the OTG supplement specifies the following
sequence of events to transfer the role of the host from the A-device to the B-device:
1. The A-device puts the bus in the suspend state
2. The B-device simulates a disconnect by deasserting its DP pull-up
3. The A-device detects SE0 on the bus, and asserts its DP pull-up
4. The B-device detects that the DP line is HIGH, and takes the role of the host.
The OTG supplement specifies that the time between the B-device deasserting its DP
pull-up and the A-device asserting its pull-up must be less than 3 ms. For an A-device
with a slow interrupt response time, 3 ms may not be enough time to write an I2C-bus
command to the ISP1301 to assert the DP pull-up. An alternative method is for the
A-device transceiver to automatically assert the DP pull-up after detecting an SE0
from the B-device.
The sequence of events is as follows:
After finishing data transfers between the A-device and the B-device and before
suspending the bus, the A-device sends SOFs. The B-device receives these SOFs,
and does not transmit any packet back to the A-device. During this time, the A-device
sets the BDIS_ACON_EN bit in the ISP1301. This enables the ISP1301 to look for
SE0 whenever the A-device is not transmitting (that is, whenever the OE_N/INT_N
pin of the ISP1301 is not asserted). After the BDIS_ACON_EN bit is set, the A-device
stops transmitting SOFs and allows the bus to go to the idle state. If the B-device
disconnects, the bus goes to SE0, and the ISP1301 logic automatically turns on the
A-device pull-up.
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12. Clock wake up scheme
This section explains the ISP1301 clock stop timing, events triggering the clock to
wake up, and the timing of the clock wake up.
12.1 Power down event
The clock is stopped when the GLOBAL_PWR_DN bit is set. It takes approximately
8 ms for the clock to stop from the time the power down condition is detected. The
clock always stops at its falling edge. The waveform is given in Figure 6.
SCL
GLOBAL_PWR_DN
CLOCK
8 ms
004aaa217
Fig 6. Clock stopped using the GLOBAL_PWR_DN bit.
12.2 Clock wake up events
The clock wakes up when any of the following events occur on the ISP1301 pins:
• SCL goes LOW
• VBUS goes above the session valid threshold (0.8 V to 2.0 V), provided the
SESS_VLD bit in the Interrupt Enable High register is set.
• ID changes when mini-A plug is inserted, provided the ID_FLOAT bit in the
Interrupt Enable Low register is set.
• ID changes when mini-A plug is removed, provided the ID_FLOAT bit in the
Interrupt Enable High register is set.
• DP goes HIGH, provided the DP_HI bit in the Interrupt Enable High register is set.
• DM goes HIGH, provided the DM_HI bit in the Interrupt Enable High register is set.
The event triggers the clock to start and a stable clock is guaranteed after about six
clock periods, which is approximately 8 µs. The startup analog clock time is 10 µs.
Therefore, the total estimated start time after a triggered event is about 20 µs. The
clock will always start at its rising edge.
Waveforms of the clock wake up because of different events are given in Figure 7,
Figure 8, Figure 9, Figure 10 and Figure 11.
SCL
CLOCK
20 µs
004aaa218
Fig 7. Clock wake up using SCL.
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SESS_VLD
CLOCK
20 µs
004aaa219
Fig 8. Clock wake up by VBUS.
ID_FLOAT
CLOCK
20 µs
004aaa220
Fig 9. Clock wake up by ID change (1).
ID_FLOAT
CLOCK
20 µs
004aaa221
Fig 10. Clock wake up by ID change (2).
DP_HI
or DM_HI
CLOCK
20 µs
004aaa434
Fig 11. Clock wake up by data line SRP.
When an event is triggered and the clock is started, it will remain active for 8 ms. If
the GLOBAL_PWR_DN bit is not cleared within this 8 ms period, the clock will stop. If
the clock wakes up because of any event other than SCL going LOW, an interrupt will
be generated once the clock is active.
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13. I2C-bus protocol
For detailed information, refer to The I2C-bus specification; version 2.1.
13.1 I2C-bus byte transfer format
Table 33:
S
I2C-bus byte transfer format[1]
Byte 1
A
Byte 2
8 bits
[1]
A
Byte 3
8 bits
A
…
A
P
…
8 bits
S = Start; A = Acknowledge; P = Stop.
13.2 I2C-bus device address
Table 34:
Device address byte 1
Bit
7
6
5
Name
A6
A5
A4
Value
0
1
0
4
3
2
1
0
A3
A2
A1
A0
R/W
1
1
0
X
X
device address
Table 35:
-
Bit description
Bit
Symbol Description
7 to 1
A[6:0]
Device address: The device address of the ISP1301 is: 0101 10 (A0).
The value of A0 (LSB) is loaded from pin ADR/PSW during reset
(including power-on reset). If pin ADR/PSW = HIGH, bit A0 = 1;
otherwise bit A0 = 0.
0
R/W
Read/write command.
0 — write
1 — read.
13.3 Write format
A write operation can be performed as:
• One-byte write to the specified register address
• Multi-byte write to N consecutive registers, starting from the specified start
address. N defines the number of registers to write. If N = 1, only the start register
is written.
13.3.1
One-byte write
Figure 12 illustrates the byte sequence.
Table 36:
Transfer format description for one-byte write
Byte
Description
S
master starts with a START condition
Device select
master transmits device address and write command bit R/W = 0
ACK
slave generates an acknowledgment
Register address K master transmits address of register K
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Table 36:
13.3.2
Transfer format description for one-byte write…continued
Byte
Description
ACK
slave generates an acknowledgment
Write data K
master writes data to register K
ACK
slave generates an acknowledgment
P
master generates a STOP condition
Multiple-byte write
Figure 12 illustrates the byte sequence.
Table 37:
Transfer format description for multiple-byte write
Byte
Description
S
master starts with a START condition
Device select
master transmits device address and write command bit R/W = 0
ACK
slave generates an acknowledgment
Register address K master transmits address of register K. This is the start address for
writing multiple data bytes to consecutive registers. After a byte is
written, the register address is automatically incremented by 1.
Remark: If the master writes to a non existent register, the slave must
send a 'not ACK' and also must not increment the index address.
ACK
slave generates an acknowledgment
Write data K
master writes data to register K
ACK
slave generates an acknowledgment
Write data K + 1
master writes data to register K + 1
ACK
slave generates an acknowledgment
:
:
Write data
K+N−1
master writes data to register K + N − 1. When the incremented
address K + N − 1 becomes > 255, the register address rolls over to 0.
Therefore, it is possible that some registers may be overwritten, if the
transfer is not stopped before the rollover.
ACK
slave generates an acknowledgment
P
master generates a STOP condition
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ACK
ACK
S
DEVICE
device select
SELECT
P
write data K
register address K
WR
ACK
One-byte write
ACK
ACK
S
DEVICE
deviceSELECT
select
write data K
register address K
WR
ACK
ACK
write data K + 3
DEVICE
write data
SELECT
K+2
ACK
ACK
write data K + 1
ACK
ACK
.... maximum, rollover to 0
write data K + N - 1
P
004aaa213
Multiple-byte write
Fig 12. Writing data to the ISP1301 registers.
13.4 Read format
A read operation can be performed in two ways:
• Current address read: to read the register at the current address.
– Single register read.
• Random address read: to read N registers starting at a specified address.
N defines the number of registers to be read. If N = 1, only the start register is
read.
– Single register read
– Multiple register read.
13.4.1
Current address read
Figure 13 illustrates the byte sequence.
Table 38:
Transfer format description for current address read
Byte
Description
S
master starts with a START condition
Device select
master transmits device address and read command bit R/W = 1
ACK
slave generates an acknowledgment
Read data K
slave transmits and master reads data from register K. If the start
address is not specified, the read operation starts from where the index
register is pointing to because of a previous read or write operation.
No ACK
master terminates the read operation by generating a No Acknowledge
P
master generates a stop condition
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ACK
S
DEVICE
device select
SELECT
RD
No ACK
read data K
Current address read
P
004aaa215
Fig 13. Current address read.
13.4.2
Random address read
Single read: Figure 14 illustrates the byte sequence.
Table 39:
Transfer format description for single-byte read
SDA line
Description
S
master starts with a START condition
Device select
master transmits device address and writes command bit R/W = 0
ACK
slave generates an acknowledgment
Register address K master transmits (start) address of register K to be read from
ACK
slave generates an acknowledgment
Device select
master transmits device address and read command bit R/W = 1
ACK
slave generates an acknowledgment
Read data K
slave transmits and master reads data from register K
No ACK
master terminates the read operation by generating a No Acknowledge
P
master generates a STOP condition
Multiple read: Figure 14 illustrates the byte sequence.
Table 40:
Transfer format description for multiple-byte read
SDA line
Description
S
master starts with a START condition
Device select
master transmits device address and write command bit R/W = 0
ACK
slave generates an acknowledgment
Register address K master transmits (start) address of register K to be read from
ACK
slave generates an acknowledgment
Device select
master transmits device address and read command bit R/W = 1
ACK
slave generates an acknowledgment
Read data K
slave transmits and master reads data from register K. After a byte is
read, the address is automatically incremented by 1.
ACK
slave generates an acknowledgment
Read data K + 1
slave transmits and master reads data from register K + 1
ACK
slave generates an acknowledgment
:
:
Read data
K+N−1
slave transmits and master reads data register K + N − 1. This is the
last register to read. After incrementing, the address rolls over to 0.
Here, N represents the number of addresses available in the slave.
No ACK
master terminates the read operation by generating a No Acknowledge
P
master generates a STOP condition
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ACK
ACK
S
device
select
DEVICE
SELECT
register address K
WR
No ACK
ACK
S
DEVICE
device SELECT
select
P
read data K
RD
Random address single read
ACK
ACK
S
DEVICE
deviceSELECT
select
S
register address K
WR
device SELECT
select
DEVICE
ACK
ACK
DEVICE
read data
SELECT
K+1
ACK
read data K + 2
RD
read data K
ACK
.... maximum, rollover to 0
Random access multiple read
ACK
No ACK
write data K + N - 1
P
004aaa214
Fig 14. Random address read.
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14. Limiting values
Table 41: Absolute maximum ratings
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VBAT
Min
Max
Unit
supply voltage
−0.5
+5.5
V
VDD_LGC
I/O supply voltage
−0.5
+4.6
V
−0.5
VDD_LGC + 0.5
V
-
100
mA
−8
+8
kV
−2
+2
kV
−60
+125
°C
VI
input voltage
Ilu
latch-up current
Vesd
electrostatic discharge voltage
Conditions
VI = −1.8 V to +5.4 V
ILI < 1 µA
pins DP, DM, ID,
VBUS, AGND, CGND
and DGND
[1]
all other pins
storage temperature
Tstg
[1]
Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model). A 4.7 µF capacitor is needed from
VREG(3V3) and VBUS to ground.
15. Recommended operating conditions
Table 42:
Recommended operating conditions
Symbol
Parameter
VBAT
supply voltage
VDD_LGC
I/O supply voltage
VI
Min
Typ
Max
Unit
2.7
-
4.5
V
1.65
-
3.6
V
input voltage
0
-
VDD_LGC V
VI(AI/O)
input voltage on analog I/O pins DP
and DM
0
-
3.6
V
VO(OD)
open-drain output pull-up voltage on
pins SCL, SDA and INT_N
0
-
3.6
V
Tamb
ambient temperature
−40
-
+85
°C
[1]
Conditions
[1]
VDD_LGC should be less than or equal to VBAT.
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16. Static characteristics
Table 43: Static characteristics: supply pins
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
3.0
-
3.6
V
Charge pump disabled
VREG(3V3)
regulated supply voltage output
VBAT = 3.0 V to 4.5 V
2.7
-
3.0
V
IBAT
operating supply current
transmitting and receiving at
12 Mbit/s; CL = 50 pF on
pins DP and DM
[2]
-
4
8
mA
IDD_LGC
operating I/O supply current
transmitting and receiving at
12 Mbit/s
[2]
-
1
2
mA
IBAT(idle)
supply current during full-speed
idle and SE0
idle: VDP > 2.7 V, VDM < 0.3 V;
SE0: VDP < 0.3 V, VDM < 0.3 V
[3]
-
-
300
µA
IDD_LGC(static)
static I/O supply current
idle, SE0 or suspend
-
-
20
µA
IBAT(pd)
power down mode supply current bit GLOBAL_PWR_DN = 1
-
-
20
µA
ILOAD = 8 mA; ATX is idle
-
-
20
mA
ILOAD = 0 mA; ATX is idle
-
-
300
µA
VBAT = 2.7 V to 3.0 V
[3]
Charge pump enabled
IBAT(cp)
[1]
[2]
[3]
operating supply current for the
charge pump
In the suspend mode, the minimum voltage is 2.7 V.
Maximum value characterized only, not tested in production.
Excluding any load current to the 1.5 kΩ and 15 kΩ pull-up and pull-down resistors (200 µA typical).
Table 44: Static characteristics: digital pins
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input levels
VIL
LOW-level input voltage
-
-
0.3VDD_LGC
V
VIH
HIGH-level input voltage
0.6VDD_LGC
-
-
V
-
-
0.4
V
-
-
0.15
V
VDD_LGC − 0.4
-
-
V
VDD_LGC − 0.15
-
-
V
−1
-
+1
µA
−5
-
+5
µA
-
-
10
pF
Output levels
LOW-level output voltage
VOL
IOL = 2 mA
IOL = 100 µA
VOH
HIGH-level output voltage
IOH = 2 mA
IOH = 100 µA
[1]
Leakage current
input leakage current
ILI
Open-drain outputs
OFF-state output current
IOZ
Capacitance
input capacitance
CIN
[1]
pin to GND
Not applicable for open-drain outputs.
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Table 45: Static characteristics: analog I/O pins DP and DM
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDI
differential input sensitivity
|VI(DP) − VI(DM)|
0.2
-
-
V
VCM
differential common mode
voltage
includes VDI range
0.8
-
2.5
V
VIL
LOW-level input voltage
-
-
0.8
V
VIH
HIGH-level input voltage
2.0
-
-
V
-
-
0.3
V
VBAT = 3.0 V to 4.5 V
2.8
-
3.6
V
VBAT = 2.7 V to 3.0 V
2.6
-
3.0
V
−1
-
+1
µA
-
-
10
pF
14.25
-
24.8
kΩ
Input levels
Output levels
VOL
LOW-level output voltage
RL of 1.5 kΩ to +3.6 V
VOH
HIGH-level output voltage
RL of 15 kΩ to GND
Leakage current
OFF-state leakage current
ILZ
Capacitance
transceiver capacitance
CIN
pin to GND
Resistance
RPD
pull-down resistor on pins
DP and DM
RPU_DP
pull-up resistor on pin DP
RPU_DM
pull-up resistor on pin DM
bus idle
900
-
1575
Ω
bus driven
1425
-
3090
Ω
bus idle
900
-
1575
Ω
1425
-
3090
Ω
bus driven
ZDRV
driver output impedance
34
-
44
Ω
ZINP
input impedance
10
-
-
MΩ
termination voltage for the
upstream port pull-up
resistor (RPU)
3.0
-
3.6
V
steady-state drive
[1]
Termination
VTERM
[1]
Includes external series resistors of 33 Ω ± 1 % each on DP and DM.
Table 46: Static characteristics: analog I/O pin ID
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
77
-
130
kΩ
-
-
10
Ω
Resistance
RPU_ID
pull-up resistor on pin ID to
VREG(3V3)
RPD_ID
impedance to GND
bit ID_PULLDOWN = 1
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Table 46: Static characteristics: analog I/O pin ID…continued
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RA_ID
A-device ID impedance to
GND
bit ID_GND = 1
-
-
1
kΩ
RB_ID
B-device ID impedance to
GND
bit ID_FLOAT = 1
800
-
-
kΩ
RACC_ID
Accessory device ID
impedance to GND
bit ID_GND = 0;
bit ID_FLOAT = 0
20
-
200
kΩ
Table 47: Static characteristics: charge pump
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
maximum load current
Cext = 100 nF; VBUS = 4.7 V
-
-
8.0
mA
VBUS
regulated VBUS output
voltage
ILOAD = 8 mA; Cext = 100 nF
4.65
5
5.25
V
VBUS(LEAK)
VBUS leakage voltage
charge pump disabled
-
-
0.2
V
Vth(VBUSVLD)
VBUS valid threshold
4.4
-
4.65
V
Vth(SESSEND)
VBUS session end
comparator threshold
0.2
-
0.8
V
Vhys(SESSEND)
VBUS session end
comparator hysteresis
-
150
-
mV
Vth(SESSVLD)
VBUS session valid
comparator threshold
0.8
-
2.0
V
Vhys(SESSVLD)
VBUS session valid
comparator hysteresis
-
200
-
mV
Vth(BSESSVLD)
VBUS session valid
comparator threshold
for the B-device
2.0
-
4.0
V
Vhys(BSESSVLD) VBUS session valid
comparator hysteresis
for the B-device
-
200
-
mV
E
efficiency when loaded
ILOAD = 8 mA; VBAT = 3 V
-
75
-
%
RVBUS(PU)
VBUS pull-up resistor
connect to VREG(3V3) when
VBUS_CHRG = 1
460
-
1000
Ω
RVBUS(PD)
VBUS pull-down resistor
connect to GND when
VBUS_DISCHRG = 1
660
-
1200
Ω
RVBUS(IDLE_A)
VBUS idle impedance for
A-device
ID pin connected to GND
40
-
100
kΩ
Current
ILOAD
Voltage
Resistance
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17. Dynamic characteristics
Table 48: Dynamic characteristics: reset and clock
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
10
-
-
µs
700
1000
1300
kHz
Reset
tW(RESET_N)
pulse width on input RESET_N
Internal clock
fclk
clock frequency
bit GLOBAL_PWR_DN = 0
Table 49: Dynamic characteristics: digital I/O pins
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40°C to +85 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tTOI
bus turnaround time
(OE_N/INT_N to DAT/VP and
SE0/VM)
output-to-input; see
Figure 19
0
-
5
ns
tTIO
bus turnaround time
(OE_N/INT_N to DAT/VP and
SE0/VM)
input-to-output; see
Figure 19
0
-
5
ns
Table 50: Dynamic characteristics: analog I/O pins DP and DM
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40 °C to +85 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics
tFR
rise time
CL = 50 pF to 125 pF;
10 % to 90 % of
|VOH − VOL|; see Figure 15
4
-
20
ns
tFF
fall time
CL = 50 pF to 125 pF;
90 % to 10 % of
|VOH − VOL|; see Figure 15
4
-
20
ns
FRFM
differential rise/fall time
matching (tFR/tFF)
excluding the first transition
from idle state
90
-
111.1
%
VCRS
output signal crossover voltage
excluding the first transition
from idle state; see
Figure 16
1.3
-
2.0
V
[1]
Driver timing
tPLH(drv)
driver propagation delay
(DAT/VP, SE0/VM to DP, DM)
LOW-to-HIGH; see
Figure 16 and Figure 20
-
-
18
ns
tPHL(drv)
driver propagation delay
(DAT/VP, SE0/VM to DP, DM)
HIGH-to-LOW; see
Figure 16 and Figure 20
-
-
18
ns
tPHZ
driver disable delay
(OE_N/INT_N to DP, DM)
HIGH-to-OFF; see
Figure 17 and Figure 21
-
-
15
ns
tPLZ
driver disable delay
(OE_N/INT_N to DP, DM)
LOW-to-OFF; see
Figure 17 and Figure 21
-
-
15
ns
tPZH
driver enable delay
(OE_N/INT_N to DP, DM)
OFF-to-HIGH; see
Figure 17 and Figure 21
-
-
15
ns
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Table 50: Dynamic characteristics: analog I/O pins DP and DM…continued
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40 °C to +85 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tPZL
driver enable delay
(OE_N/INT_N to DP, DM)
OFF-to-LOW; see
Figure 17 and Figure 21
-
-
15
ns
Receiver timing
Differential receiver
tPLH(rcv)
propagation delay (DP, DM to
RCV)
LOW-to-HIGH; see
Figure 18 and Figure 22
-
-
15
ns
tPHL(rcv)
propagation delay (DP, DM to
RCV)
HIGH-to-LOW; see
Figure 18 and Figure 22
-
-
15
ns
Single-ended receiver
tPLH(se)
propagation delay (DP, DM to
VP and DAT/VP, VM and
SE0/VM)
LOW-to-HIGH; see
Figure 18 and Figure 22
-
-
18
ns
tPHL(se)
propagation delay (DP, DM to
VP and DAT/VP, VM and
SE0/VM)
HIGH-to-LOW; see
Figure 18 and Figure 22
-
-
18
ns
[1]
Characterized only; not tested. Limits guaranteed by design.
1.8 V
logic input
t FR, t LR
VOH
0V
t FF, t LF
90 %
t PLH(drv)
t PHL(drv)
VOH
90 %
differential
data lines
10 %
10 %
VOL
VCRS
VCRS
VOL
MGS964
MGS963
Fig 15. Rise and fall times.
Fig 16. Timing of DAT/VP and SE0/VM to DP and DM.
2.0 V
1.8 V
logic input
0.9 V
0.9 V
differential
data lines
0.9 V
0.9 V
t PZH
t PZL
VOH
VOL
t PLH(rcv)
t PLH(se)
t PHZ
t PLZ
t PHL(rcv)
t PHL(se)
VOH
VOH −0.3 V
logic output
VCRS
VOL +0.3 V
Fig 17. Timing of OE_N/INT_N to DP and DM.
MGS966
VOL
0.9 V
0.9 V
MGS965
Fig 18. Timing of DP and DM to RCV, VP or DAT/VP and
VM or SE0/VM.
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VCRS
0.8 V
0V
differential
data lines
VCRS
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ISP1301
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USB OTG transceiver
OE_N/INT_N
t TOI
t TIO
DAT/VP
SE0/VM
output
input
output
004aaa439
Fig 19. SIE interface bus turnaround timing.
VTERM
VREG(3V3)
D.U.T.
test point
1.5 kΩ
DP or DM
33 Ω
004aaa448
15 kΩ
CL
Load capacitance CL = 50 pF (minimum or maximum timing).
Fig 20. Load on pins DP and DM.
test point
33 Ω
500 Ω
D.U.T.
50 pF
V
MBL142
V = 0 V for tPZH and tPHZ.
V = VREG(3V3) for tPZL and tPLZ.
Fig 21. Load on pins DP and DM for enable and disable times.
test point
D.U.T.
25 pF
MGS968
Fig 22. Load on pins VM, SE0/VM, VP, DAT/VP and RCV.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11355
Product data
Rev. 01 — 14 April 2004
37 of 46
ISP1301
Philips Semiconductors
USB OTG transceiver
Table 51:
Symbol
Characteristics of I/O stages of I2C-bus lines (SDA, SCL)
Parameter
Standard mode
Min
Max
Unit
fSCL
SCL clock frequency
-
100
kHz
tHD;STA
hold time for the START condition
4.0
-
µs
tLOW
LOW period of the SCL clock
4.7
-
µs
tHIGH
HIGH period of the SCL clock
4.0
-
µs
tSU;STA
set-up time for the START condition
4.7
-
µs
tSU;DAT
data set-up time
250
-
ns
tHD:DAT
data hold time
0
-
µs
tr
rise time of SDA and SCL signals
-
1000
ns
tf
fall time of SDA and SCL signals
-
300
ns
tSU;STO
set-up time for the STOP condition
4.0
-
µs
tBUF
bus free time between a STOP and START
condition
4.7
-
µs
SDA
tLOW
tf
tr
tSU;DAT
tf
tHD;STA
tSP
tr
tBUF
SCL
S
tHD;STA
tHD;DAT
tHIGH
tSU;STA
Sr
tSU;STO
P
S
004aaa216
Fig 23. Definition of timing for standard-mode devices on the I2C-bus.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11355
Product data
Rev. 01 — 14 April 2004
38 of 46
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
VBAT
R1
10 kΩ
SW1
VDD_LGC
C1
1 µF
VDD_LGC
SW-PB
C2
0.1 µF
C10
0.1 µF
R9
100 kΩ
Rev. 01 — 14 April 2004
2
SDA
CGND
SDA
3 SCL
SCL
4
INT_N
OTG
CONTROLLER
5
6
7
8
OE_N
9
SE0
10
DAT
11
C5
23
C2
22
C1
21
C4
0.1
µF
INT_N
VBAT
20
SPEED
VBUS
19
5
18
4
ISP1301
ID
VREG(3V3)
AGND
SUSPEND
OE_N/INT_N
DP
VM
DM
VP
RCV
17
R6
16
33 Ω
R7
33 Ω
15
DAT/VP
14
SE0/VM
13
3
C7
22
pF
C8
22
pF
C9
4.7
µF
ID
D+
USB MINI-AB
2
D- RECEPTACLE
1
VBUS
004aaa348
ISP1301
Fig 24. Application diagram for the OTG controller with DAT_SE0 SIE interface.
USB OTG transceiver
39 of 46
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
C6
0.1
µF
GND
6
0.1 µF
12
RESET_N
24
SHIELD
VDD_LGC
ADR/PSW
SHIELD
1
9
R5
10
kΩ
8
R4
10
kΩ
SHIELD
R3
3.3
kΩ
SHIELD
R2
3.3
kΩ
DGND
R8
100
kΩ
7
VDD_LGC
Philips Semiconductors
18. Application information
9397 750 11355
Product data
VDD_LGC
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
Philips Semiconductors
9397 750 11355
Product data
VDD_LGC
VBAT
R1
10 kΩ
SW1
VDD_LGC
C1
1 µF
VDD_LGC
SW-PB
C3
0.1 µF
C10
0.1 µF
R9
100 kΩ
CGND
SDA
3 SCL
SCL
4
INT_N
OTG
CONTROLLER
5
6
7
8
OE_N
9
RCV
10
VM
11
21
VBAT
20
VBUS
19
5
18
4
ISP1301
ID
AGND
SUSPEND
OE_N/INT_N
DP
17
R6
16
33 Ω
DM
VP
DAT/VP
14
SE0/VM
13
3
R7
33 Ω
15
VM
RCV
C4
0.1 µF
C6
0.1
µF
C7
22
pF
C8
22
pF
C9
4.7
µF
GND
ID
D+ USB MINI-AB
2
D- RECEPTACLE
1
VBUS
6
12
C1
004aaa438
ISP1301
Fig 25. Application diagram for the OTG controller with VP_VM SIE interface.
USB OTG transceiver
40 of 46
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
C5
0.1 µF
C2
INT_N
VREG(3V3)
23
22
RESET_N
SPEED
24
SHIELD
2
SDA
VP
VDD_LGC
ADR/PSW
SHIELD
1
9
R5
10
kΩ
SHIELD
R4
10
kΩ
8
R3
3.3
kΩ
SHIELD
R2
3.3
kΩ
DGND
Rev. 01 — 14 April 2004
R8
100
kΩ
7
VDD_LGC
ISP1301
Philips Semiconductors
USB OTG transceiver
19. Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
A
B
D
SOT616-1
terminal 1
index area
A
A1
E
c
detail X
e1
C
1/2 e
e
12
y
y1 C
v M C A B
w M C
b
7
L
13
6
e
e2
Eh
1/2 e
1
18
terminal 1
index area
24
19
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
2.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT616-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-22
Fig 26. HVQFN24 package outline.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11355
Product data
Rev. 01 — 14 April 2004
41 of 46
ISP1301
Philips Semiconductors
USB OTG transceiver
20. Soldering
20.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended. In these situations
reflow soldering is recommended.
20.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
20.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11355
Product data
Rev. 01 — 14 April 2004
42 of 46
ISP1301
Philips Semiconductors
USB OTG transceiver
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
20.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
20.5 Package related soldering information
Table 52:
Suitability of surface mount IC packages for wave and reflow soldering
methods
Package[1]
Soldering method
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, USON, VFBGA
Reflow[2]
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable[4]
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
suitable
PLCC[5], SO, SOJ
suitable
suitable
recommended[5][6]
suitable
LQFP, QFP, TQFP
not
SSOP, TSSOP, VSO, VSSOP
not recommended[7]
suitable
CWQCCN..L[8],
not suitable
not suitable
[1]
[2]
PMFP[9],
WQCCN..L[8]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11355
Product data
Wave
Rev. 01 — 14 April 2004
43 of 46
ISP1301
Philips Semiconductors
USB OTG transceiver
[3]
[4]
[5]
[6]
[7]
[8]
[9]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or
larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than
0.5 mm.
Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex
foil by using a hot bar soldering process. The appropriate soldering profile can be provided on
request.
Hot bar soldering or manual soldering is suitable for PMFP packages.
21. Revision history
Table 53:
Revision history
Rev Date
01
20040414
CPCN
Description
-
Product data (9397 750 11355).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11355
Product data
Rev. 01 — 14 April 2004
44 of 46
ISP1301
Philips Semiconductors
USB OTG transceiver
22. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
23. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
25. Licenses
Purchase of Philips I2C components
Purchase of Philips I2C components conveys a license
under the Philips’ I2C patent to use the components in the
I2C system provided the system conforms to the I2C
specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.
24. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
26. Trademarks
I2C-bus — is a trademark of Koninklijke Philips Electronics N.V.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected].
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11355
Rev. 01 — 14 April 2004
45 of 46
ISP1301
Philips Semiconductors
USB OTG transceiver
Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.4
8.5
8.6
8.7
8.8
8.9
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
8.9.9
8.9.10
8.9.11
8.9.12
8.9.13
9
9.1
9.2
9.3
9.4
9.4.1
9.4.2
9.4.3
10
10.1
10.2
11
11.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 7
Serial controller. . . . . . . . . . . . . . . . . . . . . . . . . 7
VBUS charge pump . . . . . . . . . . . . . . . . . . . . . . 7
VBUS comparators. . . . . . . . . . . . . . . . . . . . . . . 7
VBUS valid comparator . . . . . . . . . . . . . . . . . . . 7
Session valid comparator . . . . . . . . . . . . . . . . . 7
Session end comparator. . . . . . . . . . . . . . . . . . 7
ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pull-up and pull-down resistors. . . . . . . . . . . . . 8
USB transceiver (ATX) . . . . . . . . . . . . . . . . . . . 8
3.3 V DC-DC regulator . . . . . . . . . . . . . . . . . . . 8
Car kit interrupt detector . . . . . . . . . . . . . . . . . . 8
Detailed description of pins . . . . . . . . . . . . . . . 9
ADR/PSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . 9
RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
INT_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
OE_N/INT_N. . . . . . . . . . . . . . . . . . . . . . . . . . 10
SE0/VM, DAT/VP, RCV, VM and VP . . . . . . . . 10
DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
C1 and C2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VDD_LGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AGND, CGND and DGND. . . . . . . . . . . . . . . . 11
Modes of operation . . . . . . . . . . . . . . . . . . . . . 12
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 12
Direct I2C-bus mode . . . . . . . . . . . . . . . . . . . . 12
USB modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transparent modes . . . . . . . . . . . . . . . . . . . . . 13
Transparent general-purpose buffer mode . . . 13
Transparent UART mode . . . . . . . . . . . . . . . . 13
Summary tables . . . . . . . . . . . . . . . . . . . . . . . 13
USB transceiver . . . . . . . . . . . . . . . . . . . . . . . . 15
Differential driver. . . . . . . . . . . . . . . . . . . . . . . 15
Differential receiver . . . . . . . . . . . . . . . . . . . . . 15
Serial controller . . . . . . . . . . . . . . . . . . . . . . . . 17
Register map . . . . . . . . . . . . . . . . . . . . . . . . . 17
© Koninklijke Philips Electronics N.V. 2004.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 14 April 2004
Document order number: 9397 750 11355
11.1.1
11.1.2
11.1.3
11.1.4
11.2
11.3
12
12.1
12.2
13
13.1
13.2
13.3
13.3.1
13.3.2
13.4
13.4.1
13.4.2
14
15
16
17
18
19
20
20.1
20.2
20.3
20.4
20.5
21
22
23
24
25
26
Device identification registers. . . . . . . . . . . . .
Mode control registers . . . . . . . . . . . . . . . . . .
OTG registers. . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt related registers . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Autoconnect . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock wake up scheme . . . . . . . . . . . . . . . . . .
Power down event . . . . . . . . . . . . . . . . . . . . .
Clock wake up events. . . . . . . . . . . . . . . . . . .
2
I C-bus protocol . . . . . . . . . . . . . . . . . . . . . . .
I2C-bus byte transfer format . . . . . . . . . . . . . .
I2C-bus device address . . . . . . . . . . . . . . . . .
Write format . . . . . . . . . . . . . . . . . . . . . . . . . .
One-byte write . . . . . . . . . . . . . . . . . . . . . . . .
Multiple-byte write . . . . . . . . . . . . . . . . . . . . .
Read format . . . . . . . . . . . . . . . . . . . . . . . . . .
Current address read . . . . . . . . . . . . . . . . . . .
Random address read . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Recommended operating conditions . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Manual soldering . . . . . . . . . . . . . . . . . . . . . .
Package related soldering information . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Data sheet status. . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . .
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