Elpida MC-4R256CPE6C-653 Direct rambusâ ¢ dram rimmâ ¢ module 256m-byte (128m-word x 16-bit) Datasheet

PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4R256CPE6C
Direct RambusTM DRAM RIMMTM Module
256M-BYTE (128M-WORD x 16-BIT)
Description
EO
The Direct Rambus RIMM module is a general-purpose high-performance memory module subsystem suitable for
use in a broad range of applications including computer memory, personal computers, workstations, and other
applications where high bandwidth and low latency are required.
MC-4R256CPE6C modules consists of sixteen 128M Direct Rambus DRAM (Direct RDRAM™) devices
(µPD488448). These are extremely high-speed CMOS DRAMs organized as 8M words by 16 bits. The use of
Rambus Signaling Level (RSL) technology permits 600MHz, 711MHz or 800MHz transfer rates while using
conventional system and board design technologies.
Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per sixteen bytes).
L
The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous, randomly
addressed memory transactions. The separate control and data buses with independent row and column control yield
over 95 % bus efficiency. The Direct RDRAM's 32 banks support up to four simultaneous transactions per device.
Features
Pr
• 184 edge connector pads with 1mm pad spacing
• 256 MB Direct RDRAM storage
• Each RDRAM has 32 banks, for 512 banks total on module
• Gold plated contacts
• RDRAMs use Chip Scale Package (CSP)
• Operates from a 2.5 V supply
• Low power and powerdown self refresh modes
od
• Serial Presence Detect support
• Separate Row and Column buses for higher efficiency
• Over Drive Factor (ODF) support
t
uc
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0043N11 (Ver. 1.1)
(Previous No. M14809EJ2V0DS00)
Date Published February 2006 CP (K)
Printed in Japan
This product became EOL in May, 2002.
Elpida Memory, Inc. 2001-2006
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-4R256CPE6C
Order information
Part number
I/O Freq.
RAS access time
MHz
ns
800
45
184 edge connector pads RIMM
16 pieces of
MC-4R256CPE6C - 745
711
45
with heat spreader
µPD488448FF
MC-4R256CPE6C - 653
600
53
Edge connector : Gold plated
FBGA package
MC-4R256CPE6C - 845
Organization
128M x 16
Package
Mounted devices
L
EO
t
uc
od
Pr
2
Preliminary Data Sheet E0043N11
MC-4R256CPE6C
Module Pad Configuration
GND
LDQA7
GND
LDQA5
GND
LDQA3
GND
LDQA1
GND
LCFM
GND
LCFMN
GND
NC
GND
LROW2
GND
LROW0
GND
LCOL3
GND
LCOL1
GND
LDQB0
GND
LDQB2
GND
LDQB4
GND
LDQB6
GND
LDQB8
GND
LCMD
VCMOS
SIN
VCMOS
NC
GND
NC
VDD
VDD
NC
NC
NC
NC
GND
LDQA8
GND
LDQA6
GND
LDQA4
GND
LDQA2
GND
LDQA0
GND
LCTMN
GND
LCTM
GND
NC
GND
LROW1
GND
LCOL4
GND
LCOL2
GND
LCOL0
GND
LDQB1
GND
LDQB3
GND
LDQB5
GND
LDQB7
GND
LSCK
VCMOS
SOUT
VCMOS
NC
GND
NC
VDD
VDD
NC
NC
NC
NC
L
EO
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
LCFM, LCFMN,
Pr
Side B
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
Side A
RCFM, RCFMN : Clock from master
LCTM, LCTMN,
RCTM, RCTMN : Clock to master
NC
NC
NC
NC
LCMD, RCMD
: Serial Command Pad
LROW2 - LROW0,
RROW2 - RROW0 : Row bus
LCOL4 - LCOL0,
RCOL4 - RCOL0
: Column bus
LDQA8 - LDQA0,
RDQA8 - RDQA0
: Data bus A
LDQB8 - LDQB0,
RDQB8 - RDQB0
: Data bus B
LSCK, RSCK : Clock input
SA0 - SA2
: Serial Presence Detect Address
SCL, SDA
: Serial Presence Detect Clock
SIN, SOUT
: Serial I/O
SVDD
: SPD Voltage
SWP
VCMOS
: Serial Presence Detect Write Protect
: Supply voltage for serial pads
t
VREF
GND
SCL
VDD
SDA
SVDD
SWP
VDD
RSCK
GND
RDQB7
GND
RDQB5
GND
RDQB3
GND
RDQB1
GND
RCOL0
GND
RCOL2
GND
RCOL4
GND
RROW1
GND
NC
GND
RCTM
GND
RCTMN
GND
RDQA0
GND
RDQA2
GND
RDQA4
GND
RDQA6
GND
RDQA8
GND
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
uc
NC
NC
NC
NC
VREF
GND
SA0
VDD
SA1
SVDD
SA2
VDD
RCMD
GND
RDQB8
GND
RDQB6
GND
RDQB4
GND
RDQB2
GND
RDQB0
GND
RCOL1
GND
RCOL3
GND
RROW0
GND
RROW2
GND
NC
GND
RCFMN
GND
RCFM
GND
RDQA1
GND
RDQA3
GND
RDQA5
GND
RDQA7
GND
od
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
VDD
: Supply voltage
VREF
: Logic threshold
GND
: Ground reference
NC
: These pads are not connected
Preliminary Data Sheet E0043N11
3
MC-4R256CPE6C
Module Pad Names
Signal Name
Pad
Signal Name
Pad
Signal Name
Pad
Signal Name
A1
GND
B1
GND
A47
NC
B47
NC
A2
LDQA8
B2
LDQA7
A48
NC
B48
NC
A3
GND
B3
GND
A49
NC
B49
NC
A4
LDQA6
B4
LDQA5
A50
NC
B50
NC
A5
GND
B5
GND
A51
VREF
B51
VREF
A6
LDQA4
B6
LDQA3
A52
GND
B52
GND
A7
GND
B7
GND
A53
SCL
B53
SA0
A8
LDQA2
B8
LDQA1
A54
VDD
B54
VDD
A9
GND
B9
GND
A55
SDA
B55
SA1
A10
LDQA0
B10
LCFM
A56
SVDD
B56
SVDD
A11
GND
B11
GND
A57
SWP
B57
SA2
A12
LCTMN
B12
LCFMN
A58
VDD
B58
VDD
EO
Pad
A13
GND
B13
GND
A59
RSCK
B59
RCMD
A14
LCTM
B14
NC
A60
GND
B60
GND
A15
GND
B15
GND
A61
RDQB7
B61
RDQB8
A16
NC
B16
LROW2
A62
GND
B62
GND
GND
B17
GND
A63
RDQB5
B63
RDQB6
A18
LROW1
B18
LROW0
A64
GND
B64
GND
RDQB4
A19
B19
GND
A65
RDQB3
B65
B20
LCOL3
A66
GND
B66
GND
GND
B21
GND
A67
RDQB1
B67
RDQB2
A22
LCOL2
B22
LCOL1
A68
GND
B68
GND
A23
GND
B23
GND
A69
RCOL0
B69
RDQB0
A24
LCOL0
B24
LDQB0
A70
GND
B70
GND
A25
GND
B25
GND
A71
RCOL2
B71
RCOL1
A26
LDQB1
B26
LDQB2
A72
GND
B72
GND
A27
GND
B27
GND
A73
RCOL4
B73
RCOL3
A28
LDQB3
B28
LDQB4
A74
GND
B74
GND
A29
GND
B29
GND
A75
RROW1
B75
RROW0
A30
LDQB5
B30
LDQB6
A76
GND
B76
GND
A31
GND
B31
GND
A77
NC
B77
RROW2
A32
LDQB7
B32
LDQB8
A78
GND
B78
GND
A21
od
Pr
GND
LCOL4
A20
A33
GND
B33
GND
A34
LSCK
B34
LCMD
A79
RCTM
B79
NC
A80
GND
B80
GND
A35
VCMOS
B35
VCMOS
A36
SOUT
B36
SIN
A81
RCTMN
B81
RCFMN
A82
GND
B82
GND
A37
VCMOS
B37
VCMOS
A83
A38
NC
B38
NC
A84
RDQA0
B83
RCFM
GND
B84
GND
A39
GND
B39
GND
A85
A40
NC
B40
NC
A86
RDQA2
B85
RDQA1
GND
B86
A41
VDD
B41
VDD
A87
GND
RDQA4
B87
RDQA3
A42
VDD
B42
VDD
A88
A43
NC
B43
NC
A89
A44
NC
B44
NC
A45
NC
B45
NC
A46
NC
B46
NC
uc
GND
B88
RDQA6
B89
A90
GND
B90
A91
RDQA8
B91
RDQA7
A92
GND
B92
GND
Preliminary Data Sheet E0043N11
GND
t
4
L
A17
RDQA5
GND
MC-4R256CPE6C
Module Connector Pad Description
Signal
I/O
Type
GND
—
—
LCFM
I
RSL
(1/2)
Description
Ground reference for RDRAM core and interface. 72 PCB connector pads.
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
LCFMN
I
RSL
LCMD
I
VCMOS
LCOL4..LCOL0
I
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
Serial Command used to read from and write to the control registers. Also used
for power management.
EO
LCTM
LCTMN
I
I
accesses.
RSL
RSL
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
I/O
RSL
LDQB8..LDQB0
I/O
RSL
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQA8 is non-functional on modules with x16 RDRAM devices.
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQB8 is non-functional on modules with x16 RDRAM devices.
L
LSCK
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Positive polarity.
LDQA8..LDQA0
LROW2..LROW0
Column bus. 5-bit bus containing control and address information for column
I
RSL
I
VCMOS
Row bus. 3-bit bus containing control and address information for row accesses.
Serial clock input. Clock source used to read from and write to the RDRAM
control registers.
NC
—
—
These pads are not connected. These 24 connector pads are reserved for future
Pr
use.
RCFM
I
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
RCFMN
I
RSL
RCMD
I
VCMOS
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
Serial Command Input used to read from and write to the control registers. Also
od
used for power management.
RCOL4..RCOL0
I
RSL
Column bus. 5-bit bus containing control and address information for column
accesses.
RCTM
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Positive polarity.
RCTMN
I
RSL
I/O
RSL
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
uc
RDQA8..RDQA0
and the RDRAM. RDQA8 is non-functional on modules with x16 RDRAM devices.
RDQB8..RDQB0
I/O
RSL
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQB8 is non-functional on modules with x16 RDRAM devices.
RROW2..RROW0
I
RSL
Row bus. 3-bit bus containing control and address information for row accesses.
t
Preliminary Data Sheet E0043N11
5
MC-4R256CPE6C
(2/2)
Signal
RSCK
I/O
Type
Description
I
VCMOS
Serial clock input. Clock source used to read from and write to the RDRAM
control registers.
SA0
I
SVDD
Serial Presence Detect Address 0.
SA1
I
SVDD
Serial Presence Detect Address 1.
SA2
I
SVDD
Serial Presence Detect Address 2.
SCL
I
SVDD
Serial Presence Detect Clock.
SDA
I/O
SVDD
Serial Presence Detect Data (Open Collector I/O).
SIN
I/O
VCMOS
Serial I/O for reading from and writing to the control registers. Attaches to SIO0
EO
SOUT
I/O
of the first RDRAM on the module.
VCMOS
Serial I/O for reading from and writing to the control registers. Attaches to SIO1
of the last RDRAM on the module.
SVDD
—
—
SPD Voltage. Used for signals SCL, SDA, SWP, SA0, SA1 and SA2.
SWP
I
SVDD
Serial Presence Detect Write Protect (active high). When low, the SPD can be
written as well as read.
VCMOS
—
—
CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT.
VDD
—
—
Supply voltage for the RDRAM core and interface logic.
L
VREF
—
—
Logic threshold reference voltage for RSL signals.
t
uc
od
Pr
6
Preliminary Data Sheet E0043N11
MC-4R256CPE6C
Block Diagram
DQA 8
DQA 7
DQA 6
DQA 5
DQA 4
DQA 3
DQA 2
DQA 1
DQA 0
CFM
CFMN
CTM
CTMN
ROW 2
ROW 1
ROW 0
COL 4
COL 3
COL 2
COL 1
COL 0
DQB 0
DQB 1
DQB 2
DQB 3
DQB 4
DQB 5
DQB 6
DQB 7
DQB 8
DQA 8
DQA 7
DQA 6
DQA 5
DQA 4
DQA 3
DQA 2
DQA 1
DQA 0
CFM
CFMN
CTM
CTMN
ROW 2
ROW 1
ROW 0
COL 4
COL 3
COL 2
COL 1
COL 0
DQB 0
DQB 1
DQB 2
DQB 3
DQB 4
DQB 5
DQB 6
DQB 7
DQB 8
SCK
CMD
VREF
VDD
VCC
0.1 µF
SERIAL PD
7
Preliminary Data Sheet E0043N11
t
SA0 SA1 SA2
1 per
2 RDRAMs
Plus one
Near Connector
0.1 µF
47 kΩ
uc
RDQA 8
RDQA 7
RDQA 6
RDQA 5
RDQA 4
RDQA 3
RDQA 2
RDQA 1
RDQA 0
RCFM
RCFMN
RCTM
RCTMN
RROW 2
RROW 1
RROW 0
RCOL 4
RCOL 3
RCOL 2
RCOL 1
RCOL 0
RDQB 0
RDQB 1
RDQB 2
RDQB 3
RDQB 4
RDQB 5
RDQB 6
RDQB 7
RDQB 8
SOUT
RSCK
RCMD
od
U16
SIO 1
VREF
A2
Pr
DQA 8
DQA 7
DQA 6
DQA 5
DQA 4
DQA 3
DQA 2
DQA 1
DQA 0
CFM
CFMN
CTM
CTMN
ROW 2
ROW 1
ROW 0
COL 4
COL 3
COL 2
COL 1
COL 0
DQB 0
DQB 1
DQB 2
DQB 3
DQB 4
DQB 5
DQB 6
DQB 7
DQB 8
SIO 0
2 per
RDRAM
0.1 µF
SVDD
SVDD
U2
SCK
VDD
VCMOS
DQA 8
DQA 7
DQA 6
DQA 5
DQA 4
DQA 3
DQA 2
DQA 1
DQA 0
CFM
CFMN
CTM
CTMN
ROW 2
ROW 1
ROW 0
COL 4
COL 3
COL 2
COL 1
COL 0
DQB 0
DQB 1
DQB 2
DQB 3
DQB 4
DQB 5
DQB 6
DQB 7
DQB 8
L
VREF
U1
SIO 1
1 per
2 RDRAMs
0.1 µF
VCMOS
A1
A0
SIO 0
SIO 1
CMD
VREF
EO
CMD
SDA
WP
SDA
SCL
SWP
U0
SCL
LDQA 8
LDQA 7
LDQA 6
LDQA 5
LDQA 4
LDQA 3
LDQA 2
LDQA 1
LDQA 0
LCFM
LCFMN
LCTM
LCTMN
LROW 2
LROW 1
LROW 0
LCOL 4
LCOL 3
LCOL 2
LCOL 1
LCOL 0
LDQB 0
LDQB 1
LDQB 2
LDQB 3
LDQB 4
LDQB 5
LDQB 6
LDQB 7
LDQB 8
SIN
LSCK
LCMD
VREF
SIO 0
SCK
CMD
VREF
SIO 0
SIO 1
SCK
U3
Remarks 1. Rambus Channel signals form a loop through the RIMM module, with the exception of the SIO chain.
2. See Serial Presence Detection Specification for information on the SPD device and its contents.
MC-4R256CPE6C
Electrical Specification
Absolute Maximum Ratings
Symbol
Parameter
MIN.
MAX.
Unit
VI,ABS
Voltage applied to any RSL or CMOS signal pad with respect to GND
−0.3
VDD + 0.3
V
VDD,ABS
Voltage on VDD with respect to GND
−0.5
VDD + 1.0
V
TSTORE
Storage temperature
−50
+100
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
EO
DC Recommended Electrical Conditions
Symbol
Parameter and conditions
VDD
Supply voltage
VCMOS
CMOS I/O power supply at pad
MIN.
MAX.
Unit
2.50 − 0.13
2.50 + 0.13
V
2.5V controllers
2.5 − 0.13
2.5 + 0.25
V
1.8V controllers
1.8 − 0.1
1.8 + 0.2
1.4 − 0.2
1.4 + 0.2
V
Reference voltage
VIL
RSL input low voltage
VREF − 0.5
VREF − 0.2
V
VIH
RSL input high voltage
VREF + 0.2
VREF + 0.5
V
VIL,CMOS
CMOS input low voltage
−0.3
0.5VCMOS − 0.25
V
VIH,CMOS
CMOS input high voltage
0.5VCMOS+0.25
VCMOS + 0.3
V
VOL,CMOS
CMOS output low voltage, IOL,CMOS = 1 mA
—
0.3
V
VOH,CMOS
CMOS output high voltage, IOH,CMOS = −0.25 mA
VCMOS − 0.3
—
V
IREF
VREF current, VREF,MAX
−160.0
+160.0
µA
ISCK,CMD
CMOS input leakage current, (0 ≤ VCMOS ≤ VDD)
−160.0
+160.0
µA
ISIN,SOUT
CMOS input leakage current, (0 ≤ VCMOS ≤ VDD)
−10.0
+10.0
µA
L
VREF
t
uc
od
Pr
8
Preliminary Data Sheet E0043N11
MC-4R256CPE6C
AC Electrical Specifications
Symbol
Parameter and Conditions
MIN.
TYP.
MAX.
Unit
25.2
28
30.8
Ω
ns
Z
Module Impedance
TPD
Average clock delay from finger to finger of all RSL clock nets
-845
2.06
(CTM, CTMN,CFM, and CFMN)
-745
2.06
-653
2.10
∆TPD
Propagation delay variation of RSL signals with respect to TPD
−24
+24
ps
∆TPD-CMOS
Propagation delay variation of SCK and CMD signals with respect to
−100
+100
ps
-845
25
%
-745
25
-653
21
Forward crosstalk coefficient
-845
8
(300ps input rise time 20% - 80%)
-745
8
-653
8
Backward crosstalk coefficient
-845
2.5
(300ps input rise time 20% - 80%)
-745
2.5
-653
2.5
-845
1.2
-745
1.2
-653
1.2
an average clock delay
Vα/VIN
Note1,2
Note1
Attenuation Limit
EO
VXF/VIN
VXB/VIN
L
RDC
DC Resistance Limit
%
%
Ω
Pr
Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2. If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted ∆TPD Specification” table.
Symbol
∆TPD
Parameter and conditions
od
Adjusted ∆TPD Specification
Propagation delay variation of RSL signals with respect to TPD
Adjusted MIN./MAX.
+/− [24+(18*N*∆Z0)]
Note
Absolute
MIN.
MAX.
−50
+50
Unit
ps
Note N = Number of RDRAM devices installed on the RIMM module.
uc
∆Z0 = delta Z0% = (MAX. Z0 − MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on
the module.)
t
Preliminary Data Sheet E0043N11
9
MC-4R256CPE6C
RIMM Module Current Profile
IDD
IDD1
IDD2
IDD3
RIMM module power conditions
One RDRAM in Read
One RDRAM in Read
One RDRAM in Read
Note1
Note2
, balance in NAP mode
Note2
, balance in Standby mode
Note2
, balance in Active mode
EO
IDD4
IDD5
One RDRAM in Write, balance in Standby mode
L
IDD6
One RDRAM in Write, balance in NAP mode
One RDRAM in Write, balance in Active mode
MAX.
Unit
-845
753
mA
-745
688
-653
603
-845
2,340
-745
2,200
-653
1,965
-845
3,390
-745
3,100
-653
2,715
-845
713
-745
658
-653
578
-845
2,300
-745
2,170
-653
1,940
-845
3,350
-745
3,070
-653
2,690
mA
mA
mA
mA
mA
Pr
Notes 1. Actual power will depend on individual RDRAM component specifications, memory controller and usage
patterns. Power does not include Refresh Current.
2. I/O current is a function of the % of 1’s, to add I/O power for 50 % 1’s for a x16 need to add 257 mA for the
following : VDD = 2.5 V, VTERM = 1.8 V, VREF = 1.4 V and VDIL = VREF − 0.5 V.
t
uc
od
10
Preliminary Data Sheet E0043N11
MC-4R256CPE6C
Timing Parameters
The following timing parameters are from the RDRAMs pins, not the RIMM. Please refer to the RDRAM data sheet
(µPD488448) for detailed timing diagrams.
Para-
Description
MIN.
meter
tRC
Row Cycle time of RDRAM banks - the interval between ROWA packets with
MAX.
Units
tCYCLE
-845
-745
-653
28
28
28
—
20
20
20
64µs
tCYCLE
8
8
8
—
tCYCLE
8
8
8
—
tCYCLE
8
8
8
—
tCYCLE
9
7
7
—
tCYCLE
8
8
8
12
tCYCLE
ACT commands to the same bank.
tRAS
RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT
command and next ROWR packet with PRER
tRP
Note 1
command to the same bank.
Row Precharge time of RDRAM banks - the interval between ROWR packet with
Note 1
command and next ROWA packet with ACT command to the same
EO
PRER
Note 2
bank.
tPP
Precharge-to-precharge time of RDRAM device - the interval between
successive ROWR packets with PRER
Note 1
commands to any banks of the
same device.
tRR
RAS-to-RAS time of RDRAM device - the interval between successive ROWA
packets with ACT commands to any banks of the same device.
tRCD
RAS-to-CAS Delay - the interval from ROWA packet with ACT command to
COLC packet with RD or WR command. Note - the RAS-to-CAS delay seen
L
by the RDRAM core (tRCD-C) is equal to tRCD-C = 1 + tRCD because of differences in
the row and column paths through the RDRAM interface.
tCAC
CAS Access delay - the interval from RD command to Q read data. The
equation for tCAC is given in the TPARM register.
CAS Write Delay - interval from WR command to D write data.
6
6
6
6
tCYCLE
tCC
CAS-to-CAS time of RDRAM bank - the interval between successive COLC
4
4
4
—
tCYCLE
commands.
Pr
tCWD
tPACKET
Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
4
4
4
tCYCLE
tRTR
Interval from COLC packet with WR command to COLC packet which causes
8
8
8
—
tCYCLE
4
4
4
4
tCYCLE
retire, and to COLM packet with bytemask.
tOFFP
The interval (offset) from COLC packet with RDA command, or from COLC
od
packet with retire command (after WRA automatic precharge), or from COLC
packet with PREC command, or from COLX packet with PREX command to
the equivalent ROWR packet with PRER. The equation for tOFFP is given in the
TPARM register.
tRDP
Interval from last COLC packet with RD command to ROWR packet with
PRER.
tRTP
Interval from last COLC packet with automatic retire command to ROWR
Notes 1. Or equivalent PREC or PREX command.
4
4
—
tCYCLE
4
4
4
—
tCYCLE
uc
packet with PRER.
4
2. This is a constraint imposed by the core, and is therefore in units of ms rather than tCYCLE.
t
Preliminary Data Sheet E0043N11
11
MC-4R256CPE6C
Standard RIMM Module Marking
The RIMM modules are marked per Figure 1 below. This marking assists users to specify and verify if the correct
RIMM modules are installed in their systems. In the diagram, a label is shown attached to the RIMM module's heat
spreader. Information contained on the label is specific to the RIMM module and provides RDRAM information without
requiring removal of the RIMM module's heat spreader.
Figure 1. RIMM Module marking example
A
B
C
EO
128MB/8d nonECC
JAPAN
MC-4R128CEE6C-845 800-45
0020B9001
G
G100 S100
E
H
Label Field
I
1996 HCS, Inc.
B Manufacturing Country
800-748-0241
F
No. 6043B-ISO
J
Description
Marked Text
Units
Vendor logo area
NEC
−
Country of origin
JAPAN, USA, FRANCE
−
L
A Vendor logo
D
C Module Memory Capacity Number of 8-bit or 9-bit MBytes of RDRAM storage in 64MB, 96MB, 128MB, 192MB,
256MB
Number of RDRAM devices contained in the RIMM
/4d, /6d, /8d, /12d, /16d
Pr
Number of RDRAMs
RIMM module
RDRAM
module
D ECC Support
Indicates whether the RIMM module supports 8-bit
MBytes
devices
non ECC, ECC
−
(non ECC) or 9-bit (ECC) Bytes
E Part No.
NEC RIMM Part No.
See table Order information
−
F Memory Speed
Data transfer speed for RIMM module
800, 711, 600
MHz
Row Access Time
od
tRAC
-45, -53
ns
G Manufacturing Lot No.
Manufactured Year code, Week code, In-house code YYWW∗∗∗∗∗
−
H Gerber Version
PCB Gerber file revision used on RIMM Module
G100 as Rev 1.00
−
I SPD Version
SPD code version
S100 as Rev 1.00
−
J Caution Logo
−
−
−
t
uc
12
Preliminary Data Sheet E0043N11
MC-4R256CPE6C
Package Drawings
184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (1/2)
A (AREA B)
R
128 M Direct RDRAM
V
M1 (AREA B)
P
S
O N
A
M
Q
EO
L
M2 (AREA A)
K
H
G
B
I
D
B
T
J
E
F
C
A1 (AREA A)
EEPROM
L
Pr
detail of B part
detail of A part
W
X
R1.00
R1.00
od
Y
C1
B1
Z
ITEM
A
MILLIMETERS
133.35 TYP.
A1
133.35±0.13
B
55.175
B1
1.00±0.10
C
11.50
C1
3.00±0.10
D
45.00
E
F
32.00
G
5.675
H
47.625
I
25.40
J
47.625
K
6.35
L
1.00 TYP.
M
31.75±0.13
M1
11.97
M2
19.78
N
29.21
O
17.78
45.00
uc
4.00±0.10
Q
R 2.00
R
3.00±0.10
φ 2.44
1.27±0.10
3.49 MAX.
0.80±0.10
2.99
0.15
2.00±0.10
S
T
V
W
X
Y
Z
Preliminary Data Sheet E0043N11
t
P
13
MC-4R256CPE6C
;
;
;;;;;;;;;
;;;;;
;;;;;;;;;
;;;;;;;;;
184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (2/2)
A
B
E
EO
Pad A1
B
C
E
F
H
G
MIN.
133.22
TYP.
133.35
MAX.
133.48
UNIT
mm
PCB height for 1.25" RIMM Module
31.62
31.75
31.88
mm
Center-center pad width from pad A1 to A46,
A47 to A92, B1 to B46 or B47 to B92
Spacing from PCB left edge to connector key notch
44.95
45.00
45.05
mm
-
55.175
-
mm
-
17.78
-
mm
1.17
1.27
1.37
mm
-
-
3.09
mm
-
-
7.55
mm
Spacing from contact pad PCB edge
to side edge retainer notch
PCB thickness
Heat spreader thickness from PCB surface (one side) to
heat spreader top surface
RIMM thickness
F
H
DESCRIPTION
PCB length
t
uc
od
G
Pad A92
D
Pr
D
C
L
ITEM
A
C
14
Preliminary Data Sheet E0043N11
MC-4R256CPE6C
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
EO
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
L
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
Pr
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
od
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
t
uc
Preliminary Data Sheet E0043N11
15
MC-4R256CPE6C
Rambus, RDRAM and the Rambus Logo are registered trademarks of Rambus Inc.
DirectRambus, DirectRDRAM, RIMM, RModule and RSocket are trademarks of Rambus Inc.
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
EO
L
• The information in this document is current as of August, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or
data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all
products and/or types are available in every country. Please check with an Elpida Memory, Inc. for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document.
• Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of Elpida semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of Elpida or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• Elpida semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in
Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in
applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine
Elpida's willingness to support a given application.
(Note)
(1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned
subsidiaries.
(2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or
for Elpida (as defined above).
t
uc
od
Pr
M8E 00. 4
Similar pages