Intersil ISL6571EVAL1 Complementary mosfet driver and synchronous half-bridge switch Datasheet

ISL6571
®
Data Sheet
April 18, 2005
Complementary MOSFET Driver and
Synchronous Half-Bridge Switch
FN9082.4
Features
The Intersil ISL6571 provides a new approach for
implementing a synchronous rectified buck switching
regulator. The ISL6571 replaces two power MOSFETs, a
Schottky diode, two gate drivers and synchronous control
circuitry. Its main applications address high-density power
conversion circuits including multiphase-topology computer
microprocessor core power regulators, ASIC and memory
array regulators, etc. Another useful feature of the ISL6571
is the compatibility with three-state input control: left open,
the PWM input turns off both output drives. The ISL6571
operates in continuous conduction mode reducing EMI
constraints and enabling high bandwidth operation.
• Improved Performance over Conventional Synchronous
Buck Converter using Discrete Components
• Optimal Deadtime Provided by Adaptive Shoot-Through
• Switching Frequency up to 1MHz
- High-Bandwidth, Fast Transient Response
- Small, Low Profile Converters
• Reduced Connection Parasitics between Discrete
Components
- Low Electromagnetic Emissions
• Low Profile, Low Thermal Impedance Packaging
- High Power Density Applications
ISL6571CR*
0 to 70
68 Ld 10x10 QFN L68.10x10A
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Available (RoHS Compliant)
ISL6571CRZ*
(See Note)
0 to 70
68 Ld 10x10 QFN L68.10x10A
(Pb-free)
Applications
Ordering Information
PART NUMBER
ISL6571EVAL1
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
• Multiphase Power Regulators
• Low-Voltage Switchmode Power Conversion
Evaluation Board
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
• High-Density Power Converters
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6571
Pinout
VCC
LGATE
NC
53
52
NC
55
54
GND
PVCC
56
LGATE1
58
57
PGND
PHASE
59
PGND
61
60
64
PGND
PGND
65
PGND
PGND
66
62
PGND
67
63
PGND
PGND
68
ISL6571 (QFN) TOP VIEW
51
NC
2
50
GND
3
49
NC
48
PWM
47
BOOT
6
46
GND
7
45
PHASE
PHASE
8
44
VIN
PHASE
9
43
VIN
VIN
PHASE
1
PHASE
PHASE
PHASE
4
PHASE
5
PHASE
PHASE
71
GND
69
PHASE
PHASE
10
42
PHASE
11
41
VIN
PHASE
12
40
VIN
PHASE
13
39
VIN
VIN
70
VIN
2
28
29
30
31
32
33
34
NC
VIN
VIN
VIN
VIN
VIN
27
PHASE
VIN
25
26
NC
24
NC
NC
23
NC
VIN
NC
35
22
17
21
VIN
PHASE
20
36
NC
16
NC
VIN
PHASE
19
37
NC
15
18
14
PHASE
NC
PHASE
38
FN9082.4
VIN
PVCC
VCC
3
POWER-ON
RESET (POR)
BOOT
DRIVE1
+
10K
PHASE
GATE
CONTROL
PVCC
PWM
LGATE
10K
DRIVE2
LFET
GND
LGATE1
FN9082.4
FIGURE 1. BLOCK DIAGRAM
PGND
ISL6571
CONTROL
LOGIC
5V
UFET
ISL6571
+12VIN
+5VIN
CBOOT
LOUT
CONTROL
AND
DRIVERS
PWM
VOUT
COUT
ISL6571
FIGURE 2. SIMPLIFIED POWER SYSTEM DIAGRAM
LIN
+12VIN
+5VIN
VCC
BOOT
PVCC
+
CIN1
CBOOT1
PWM
VIN
U2
ISL6571
PHASE
LGATE1
LGATE
LOUT1
GND
PGND
PVCC
BOOT
RSNS1
20
VCC
18
17
PWM4
PWM1
ISEN4
ISEN1
15
16
VCC
PWM
POWER
GOOD
PWM2
19
PGOOD
ISEN2
FS/DIS
ISEN3
5
4
3
2
1
COMP
VID0
VID1
VID2
VID3
VID4
13
GND
PGND
PVCC
BOOT
+
VOUT
RSNS2
12
6
7
R2
10
ROFFSET
COUT
11
C1
FB
VSEN
LOUT2
PHASE
LGATE1
C2
GND
9
CBOOT2
VIN
LGATE
PWM3
RFS
CIN2
U3
ISL6571
14
U1
HIP6301
8
+
VCC
PWM
+
CIN3
CBOOT3
VIN
U4
ISL6571
PHASE
LGATE1
LGATE
LOUT3
GND
PGND
RSNS3
R1
FIGURE 3. TYPICAL APPLICATION
4
FN9082.4
ISL6571
Absolute Maximum Ratings
Thermal Information
Bias Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
Driver Supply, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10.5V
Conversion Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . VCC+0.3V
DRIVE1 Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . .+15V
Input Voltage, PWM . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 7V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical, Note 1)
θJC (°C/W)
Pad 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Pad 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.0
Pad 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.0
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
Maximum Storage Temperature Range . . . . . . . . . . . -40°C to 125°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Control and Conversion Voltage, VCC, VIN. . . . . . . . . . +12V ±10%
MOSFET Bias Supply, PVCC . . . . . . . . . . . . . . . . . . . +5V to +10V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJC is measured with the component mounted on a typical application PCB. A separate θJC value is provided for each of the three exposed die
pads (#69, 70, 71). Each value should be used in combination with the power dissipated by only the individual die mounted on that pad.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
2.5
3.6
mA
9.70
9.95
10.40
V
-
2.40
-
V
-
5
-
kΩ
PWM Rising Threshold
-
-
3.80
V
PWM Falling Threshold
1.30
-
-
V
SUPPLY CURRENT
Nominal Bias Supply Current
IVCC
PWM Open
POWER-ON RESET
Rising VCC Threshold
VCC Threshold Hysteresis
MOSFET DRIVER
Input Impedance
ZIN
PWM-to-PHASE Low-to-High Propagation
Delay
tPLH
-
80
-
ns
PWM-to-PHASE High-to-Low Propagation
Delay
tPHL
-
56
-
ns
1.60
-
3.40
V
-
230
-
ns
VBOOT - VPHASE = 5V
12.8
13.5
18.2
mΩ
VBOOT - VPHASE = 10V
7.70
9.20
12.7
mΩ
VBOOT - VPHASE = 5V
25
-
-
A
VPVCC = 5V
4.10
4.80
5.55
mΩ
VPVCC = 10V
3.40
4.05
4.70
mΩ
VPVCC = 5V
25
-
-
A
Shutdown Window
Shutdown Holdoff Time
tSH
UPPER MOSFET (UFET)
Drain-to-Source ON-State Resistance
rDS(ON)
ON-State Drain Current
LOWER MOSFET (LFET)
Drain-to-Source ON-State Resistance
ON-State Drain Current
5
rDS(ON)
FN9082.4
ISL6571
Typical Performance Curves/Setup
∆ILOUT(p-p)
+12V
+5V
VOUT
1.8
ROUT
VIN
PVCC BOOT
CBOOT
LOUT
CONTROL
AND
DRIVERS
PWM
NORMALIZED r(DS)ON
+12V
CVCC
VCC
VOUT
PHASE
1.26
75
50
Tj (°C)
100
125
150
VGS = 10V
1.08
VPVCC = 10V
ID = 20A
0.90
72
0.72
54
0.54
36
0.36
18
0.18
NORMALIZED r(DS)ON
1.4
IPHASE = 0A
300 400 500 600 700 800
SWITCHING FREQUENCY (kHz)
25
1.6
PPVCC (W)
IPVCC (mA)
0
FIGURE 5. UPPER MOSFET ON RESISTANCE vs
TEMPERATURE
VPVCC = 5V
1.2
1.0
0.8
0
900 1000
FIGURE 6. BIAS SUPPLY CURRENT/POWER vs FREQUENCY
0.6
-25
4.00
VPVCC = 5V
ILOUT = 12A
DISSIPATED POWER (W)
3.00
2.50
2.00
25
VPVCC = 5V
LOUT = 1µH
12Vin/1.5Vout
3.50
LOUT = 1µH
0
75
50
Tj (°C)
100
125
150
FIGURE 7. LOWER MOSFET ON RESISTANCE vs
TEMPERATURE
4.00
DISSIPATED POWER (W)
1.0
-25
126
3.50
1.2
0.6
FIGURE 4. TYPICAL TEST CIRCUIT
0
100 200
1.4
PGND
GND
90
ID = 12A
0.8
ROUT
COUT
ISL6571
108
VGS = 10V
1.6
CVIN
CPVCC
3.00
750kHz
500kHz
300kHz
2.50
200kHz
2.00
1.50
1.00
0.50
1.50
200
300
600
400
500
700
800
SWITCHING FREQUENCY (kHz)
900
1000
FIGURE 8. ISL6571 POWER DISSIPATION vs FREQUENCY
AT 12A
6
0
0
1.5
3.0
4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5
OUTPUT CURRENT (A)
FIGURE 9. ISL6571 POWER DISSIPATION vs CURRENT AT
200kHz, 300kHz, 500kHz, 750kHz
FN9082.4
ISL6571
Typical Performance Curves/Setup (Continued)
93
200kHz
EFFICIENCY (%)
91
89
300kHz
87
500kHz
85
750kHz
83
81
79
77
75
73
0
1.5
3.0
4.5
6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5
OUTPUT CURRENT (A)
FIGURE 10. ISL6571 EFFICIENCY AT 200kHz, 300kHz, 500kHz, 750kHz
Functional Pin Descriptions
VCC (Pin 54)
Provide a 12V bias supply for the driver IC to this pin. The
voltage at this pin is monitored for Power-On Reset (POR)
purposes.
provides the bias for the upper MOSFET drive and the gate
charge for the upper MOSFET.
LGATE (Pin 53)
This pin is the output of the lower MOSFET drive. Connect
this pin to LGATE1 pin using the shortest available path.
PVCC (Pin 56)
LGATE1 (Pin 58)
Provide a well decoupled 5V to 10V bias supply at this pin.
The voltage at this pin is used to bias the gates of the
MOSFET switches.
This pin is connected to the gate of the lower MOSFET
switch. Connect this pin to LGATE pin using the shortest
available path.
GND (Pins 46, 50, 57, 71)
PWM (Pin 48)
Ground pins for the driver IC. Connect these pins to the
circuit ground (plane) and to the PGND pins using the
shortest available paths.
Connect this pin to the regulating controller’s PWM output.
Left open, this input will float to approximately 2.5V and
cause both MOSFET switches to be turned off. Applying 5V
to this input causes the upper MOSFET switch to be turned
on. A 0V applied to this input causes the lower MOSFET
switch to be turned on. The approximate input impedance of
this pin is 5kΩ.
PGND (Pins 60-68)
This is the source ground connection for the lower MOSFET
switches. Connect these pins to the circuit ground (plane)
and to the GND pins using the shortest available paths.
VIN (Pins 29-44, 70)
NC (Pins 18-26, 28, 49, 51, 52, 55)
These pins are not internally connected.
Connect these pins to the input voltage to be converted
down. Provide bulk and high-frequency decoupling
capacitors as close to these pins as feasible.
PHASE (Pins 1-17, 27, 45, 59, 69)
As a minimum, connect pin 69 to the output inductor. The
remainder of the PHASE pins may be tied to pin 69, left
open, or used for other connections. It is recommended pin
45 is connected to the bootstrap capacitor, CBOOT.
BOOT (Pin 47)
This pin is connected to the PVCC pin through an internal
quasi-diode. Connect a bootstrap capacitor from this pin to
PHASE pin 45 (0.1µF recommended). This capacitor
7
Description
Bias Requirements
The on-board driver includes a Power-On Reset (POR)
function, which continually monitors the input bias supply.
The POR monitors the bias voltage (+12VIN) at the VCC pin,
and enables the ISL6571 for operation immediately after it
exceeds the rising threshold. Upon the bias voltage’s drop
below the falling threshold, the IC is disabled and both
internal MOSFETs are turned off.
The output drivers are powered from the PVCC pin. For
proper functionality and driving capability, connect PVCC to
FN9082.4
ISL6571
a suitable supply, 5V to 10V, no higher than the voltage
applied at the VCC pin. The higher the voltage applied at the
PVCC pin, the better the channel enhancement of the onboard power MOSFETs, but also the higher the power
dissipated inside the driver.
The down-conversion voltage applied at VIN cannot exceed
the bias voltage applied at VCC, but can be as low as
practically possible.
Operation
The ISL6571 combines two MOSFET transistors in a
synchronous buck power train configuration, along with a halfbridge MOSFET driver designed to control these two
MOSFETs. When reviewing the operational details, refer to
Figure 5 test setup.
PWM
With all requirements for operation met, a logic high signal
on the PWM pin causes the UFET to turn on, while a logic
low signal applied to the PWM pin causes LFET to turn on. If
the PWM input is driven within the shutdown window and
remains there for the minimum holdoff time specified (See
‘Electrical Specifications’), both MOSFETs are turned off.
PHASE
GND
tSH
tPHL
tPLH
GND
FIGURE 11. PHASE RESPONSE TO PWM INPUT
At the transition between the on intervals of the two
MOSFETs, the internal driver acts in a ‘break-before-make’
fashion. Thus, the driver monitors the on device and turns on
the (previously) off device, following a short time delay after
the on MOSFET has turned off. This behavior is necessary
to insure the absence of cross-conduction (shoot-through)
amongst the two MOSFETs.
Application and Component Selection
Guidelines
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
8
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turn-off
transition of the upper MOSFET. Prior to turn-off, the upper
MOSFET was carrying the full load current. During the turnoff, current stops flowing in the upper MOSFET and is picked
up by the lower MOSFET or Schottky diode. Any inductance
in the switched current path generates a large voltage spike
during the switching interval. Careful component selection,
tight layout of the critical components, and short, wide circuit
traces minimize the magnitude of voltage spikes.
The ISL6571 is the first step in such an efficient design. By
bringing the driver and switching transistors in close
proximity, most of the interconnect/layout parasitic
inductances are greatly reduced. However, these benefits
are nulled if the associated decoupling elements and other
circuit components are not carefully positioned and laid out
to help the ISL6571 realize its full potential. Figure 12 shows
one possible layout pattern, detailing preferred positioning of
components, land size/pattern, and via count. Figure 12 is
one of many possible layouts yielding good results; use it for
general illustration and guidance.
Locate the decoupling capacitors, especially the highfrequency ceramic capacitors, close to the ISL6571. To fully
exploit ceramic capacitors’ low equivalent series inductance
(ESL), insure their ground connection is made as close to
their grounded terminal as physically feasible. Figure 12
details via-in-pad (VIP) practices, where the via is placed on
the component’s landing pad, thus yielding the shortestpath, lowest ESL connection to the desired plane/island.
Via-in-pad design is very important to the layout of the
ISL6571, since it is an integral part of the thermal design
consideration. VIP not only provides the lowest ESL circuit
connections, but it is essential to the propagation of heat
from the internal dies to the ambient. The vias placed directly
underneath the bottom pads of the package provide a low
thermal impedance path for the heat generated inside the IC
to diffuse through the internal planes, as well as through
islands on the back side of the board. Layout with landing
pads for the bottom pads of the package devoid of vias is
possible (rather, with vias placed outside of the package
outline), but the thermal performance of such a layout would
be significantly reduced. Use the smallest diameter vias
available and avoid the use of thermal relief on the contacts
with internal planes; if thermal relief is mandatory on all vias,
design the thermal relief so that it voids the smallest possible
copper area around the vias (thus preserving thermal
conductivity and reducing electrical contact resistance).
A multi-layer printed circuit board is recommended. Dedicate
one solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes.
FN9082.4
ISL6571
TO VIN
TO PWM
CBULK
TO +12V
CBOOT
TO +5V
CVCC
GND
VIN
CPVCC
CHF (x2)
PHASE
Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the surrounding application to
the ISL6571 should be sized according to their task. Thus,
small-signal traces, like the PWM signal or the ISEN
feedback (if used in conjunction with another Intersil
controller), only need be as wide as 5-10mils. Traces
carrying bias current should be larger, proportionately with
the current flowing through them; for example, traces
carrying PVCC current around 50-100mA would require
30-50mils. Generally, the best connections are the shortest,
enclosing the least amount of area possible. Similarly, from a
conduction requirement perspective, where vias are required
to carry current, use a via for each 2-3A of RMS current.
Bootstrap Requirements
The ISL6571 features an integrated boot element connected
between the PVCC and BOOT pins. A 0.1µF external
bootstrap capacitor is recommended.
TO LOUT
KEY
ISLAND ON POWER PLANE LAYER
CONNECTING TRACES ON TOP/BOTTOM LAYERS
VIA CONNECTION TO OTHER PLANEs
FIGURE 12. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
Use copper-filled polygons on the top and bottom circuit
layers for the PHASE node, but do not unnecessarily
oversize these particular islands. Since the PHASE node is
subject to very high dV/dt voltages, the stray capacitors
formed between these islands and the surrounding circuitry
or internal planes will tend to couple switching noise. On the
other hand, these islands have to be sufficiently large to offer
a good path to surrounding environment for the heat
produced inside the ISL6571.
Capacitor (Decoupling) Selection
To fully extract the benefits of a highly performant power
integrated circuit, the circuit elements surrounding it must
conform to the same high standards as the active power
element. As such, the capacitors used for high-frequency
decoupling of the ISL6571 should be good quality ceramic,
with a low ESR and ESL (X7R, X5R dielectric, and 0805 or
smaller footprints recommended); a minimum of two 1µF
capacitors are recommended. Bulk decoupling capacitor
technology is not restricted to ceramic, as electrolytic
capacitors are also suitable. For best results, select
capacitors based on the input RMS current draw of the
circuit, with a low ESL; distribute evenly amongst and place
them as close to the ISL6571 as possible.
ISL6571 DC-DC Converter Application
Circuit
Figure 13 shows an application circuit of a power supply for
a microprocessor computer system. For detailed information
on the circuit, including a Bill-of-Materials and circuit board
description, contact Intersil to order the evaluation kit
ISL6571EVAL1. Also see Intersil web page
(http://www.intersil.com).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN9082.4
ISL6571
LIN
+12VIN >
+5VIN >
VCC
BOOT
PVCC
PWM
+
CIN1
U2
ISL6571
LGATE1
LGATE
LOUT1
PHASE
LGATE2
CVCC1
CBOOT1
VIN
GND
PGND
PVCC
BOOT
RSNS1
20
VCC
15
PWM1
ISEN1
PWM2
RPG
ISEN2
POWER
GOOD
>
PWM3
19
PGOOD
ISEN3
16
VCC
14
PWM
13
FS/DIS
RFS
ISEN4
CBOOT2
VIN
U3
ISL6571
LOUT2
PHASE
LGATE2
12
LGATE
PWM4
CIN2
LGATE1
11
U1
HIP6301
8
+
COUT
GND
PGND
+
RSNS2
18
17
VOUT
5
4
3
2
1
COMP
VID0
VID1
VID2
VID3
VID4
FB
VSEN
GND
9
6
7
C2
PWM
R2
LGATE1
10
CPVCC2-5
CVIN2-5
COUT_HF
+
CIN3
CBOOT3
VIN
U4
ISL6571
LGATE
LOUT3
PHASE
LGATE2
ADDITIONAL
HIGH-FREQUENCY
DECOUPLING
BOOT
PVCC
C1
ROFFSET
CVCC2-5
VCC
GND
PGND
PVCC
BOOT
RSNS3
R1
VCC
1 to each of VCC2-5
C3
1 to each of PVCC2-5
2 to each of VIN2-5
varied HF mix to VOUT
varied bulk mix to VOUT
COUT_BULK
R3
PWM
+
CIN4
CBOOT4
VIN
U5
ISL6571
LGATE1
PHASE
LGATE2
LGATE
LOUT4
GND
PGND
RSNS3
FIGURE 13. TYPICAL ISL6571 APPLICATION CIRCUIT
10
FN9082.4
ISL6571
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
2X
A
68 LEAD MICRO LEAD FRAME PLASTIC PACKAGE
(CUSTOMIZED WITH THREE EXPOSED PADS)
0.15 C A
D
MILLIMETERS
D/2
SYMBOL
D1
6
INDEX
AREA 1
2
3
L68.10x10A
2X
D1/2
N
0.15 C B
E/2
E1/2
MIN
-
-
0.90
-
-
-
0.05
-
A2
-
-
0.70
-
b
0.20 REF
0.18
2X
B
TOP VIEW
0.15 C A
2X
θ
A2
C
A
NX
0.05 C
SEATING
PLANE
A3
SIDE VIEW
A1
5
0.10 M C A B
D2
4X P
7
D2/2
8
NX k
D3
D4
4X P
E4
69
(Ne–1)Xe
REF.
E2
6
INDEX
AREA 3
2
1
NX L
9.75 BSC
7.85
7, 8
D3
2.44
2.59
2.74
7, 8
D4
4.48
4.63
4.78
7, 8
E
10.00 BSC
-
E1
9.75 BSC
-
E2
7.55
7.70
7.85
7, 8
E3
2.44
2.59
2.74
7, 8
E4
4.48
4.63
4.78
7, 8
0.50 BSC
k
0.25
-
L
0.50
0.60
-
-
0.75
8
N
68
2
Nd
17
3
17
3
P
-
-
0.60
θ
-
-
12
-
1. Dimensioning and tolerancing per ASME Y14.5-1994.
2. N is the number of peripheral terminals. Exposed pads are
terminals 69, 70 and 71, as shown.
E3
3. Nd is the number of terminals in the X direction, and Ne is the
number of terminals in the Y direction.
8
e
4. Controlling dimension: Millimeters. Angles are in degrees.
(Nd–1)Xe
REF.
5. Dimension b applies to the plated terminal and is measured
between 0.20mm and 0.25mm from the terminal tip.
BOTTOM VIEW
C C
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a molded or marked feature.
A1
C
L
-
7.70
NOTES:
7
8
-
Rev. 0 2/02
E2/2
71
N
5, 8
7.55
Ne
70
0.30
D2
e
NX b
0.23
-
10.00 BSC
D1
0.15 C B
NOTES
A
D
E1
MAX
A1
A3
E
NOMINAL
NX b
C
L
5
7. Dimensions D2/3/4 and E2/3/4 are for the three exposed pads
which provide improved electrical and thermal performance.
SECTION "C-C"
e
e
8. Nominal dimensions provided to assist with PCB Land Pattern
Design efforts, see Technical Brief TB389.
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
11
FN9082.4
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