TI1 DS96F172MJ/883 Eia-485/eia-422 quad differential driver Datasheet

DS96F172MQML, DS96F174MQML
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SNOSAS8A – APRIL 2011 – REVISED APRIL 2013
DS96F172MQML/DS96F174MQML EIA-485/EIA-422 Quad Differential Drivers
Check for Samples: DS96F172MQML, DS96F174MQML
FEATURES
DESCRIPTION
•
•
•
•
•
The DS96F172 and the DS96F174 are high speed
quad differential line drivers designed to meet EIA485 Standards. The DS96F172 and the DS96F174
offer improved performance due to the use of L-FAST
bipolar technology. The use of LFAST technology
allows the DS96F172 and DS96F174 to operate at
higher speeds while minimizing power consumption.
1
2
•
•
•
•
Meets EIA-485 and EIA-422 Standards
Monotonic Differential Output Switching
TRI-STATE Outputs
Designed for Multipoint bus Transmission
Common Mode Output Voltage Range: −7.0V
to +12V
Operates from Single +5.0V Supply
Reduced Power Consumption
Thermal Shutdown Protection
DS96F172 and DS96F174 are Lead and
Function Compatible with the SN75172/174 or
the AM26LS31/MC3487
The DS96F172 and the DS96F174 have TRI-STATE
outputs and are optimized for balanced multipoint
data bus transmission at rates up to 15 Mbps. The
drivers have wide positive and negative common
mode range for multipoint applications in noisy
environments. Positive and negative current-limiting
is provided which protects the drivers from line fault
conditions over a +12V to −7.0V common mode
range. A thermal shutdown feature is also provided.
The DS96F172 features an active high and active low
Enable, common to all four drivers. The DS96F174
features separate active high Enables for each driver
pair.
Connection Diagrams
Figure 1. 16-Lead CDIP Package-Top View
DS96F172
(See Package Number NFE0016A)
Figure 2. 16-Lead CDIP Package-Top View
DS96F174
(See Package Number NFE0016A)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
DS96F172MQML, DS96F174MQML
SNOSAS8A – APRIL 2011 – REVISED APRIL 2013
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NC = No connection
Figure 3. 20-Lead LCCC Package-Top View
DS96F172
(see Package Number NAJ0020A)
Figure 4. 20-Lead LCCC Package-Top View
DS96F174
(see Package Number NAJ0020A)
Logic Diagrams
Figure 5. DS96F172
2
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Figure 6. DS96F174
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SNOSAS8A – APRIL 2011 – REVISED APRIL 2013
Function Tables (Each Driver)
Table 1. DS96F172 (1)
Input
(1)
Enable
Outputs
A
E
E
Y
Z
H
H
X
H
L
H
L
H
X
L
H
X
L
H
L
L
X
L
L
H
X
L
H
Z
Z
H = High Level
L = Low Level
X = Don't Care
Z = High Impedance (Off)
Table 2. DS96F174 (1)
(1)
Input
Enable
A
E
Y
Outputs
Z
H
H
H
L
L
H
L
H
X
L
Z
Z
H = High Level
L = Low Level
X = Don't Care
Z = High Impedance (Off)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
−65°C ≤ TA ≤ +175°C
Storage Temperature Range (TStg)
Lead Temperature (Soldering, 60 sec.)
300°C
Maximum Package Power Dissipation at 25°C (2)
LCCC package
2,000 mW
CDIP package
1,800 mW
Ceramic Flatpack package
1,000 mW
Supply Voltage
7.0V
Enable Input Voltage
5.5V
(1)
(2)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not verify specific performance limits. For verified specifications and test conditions, see the
Electrical Characteristics. The verified specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Above TA = 25°C, derate LCCC package 13.3, CDIP package 12.5, Ceramic flatpack package 7.1 mW/°C
Recommended Operating Conditions
Min
Max
Units
Supply Voltage (VCC)
4.50
5.50
V
Common Mode Output Voltage (VOC)
−7.0
+12.0
V
−60
mA
60
mA
+125
°C
Output Current High (IOH)
Output Current Low (IOL)
−55
Operating Temperature (TA)
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Quality Conformance Inspection
Table 3. Mil-Std-883, Method 5005 - Group A
Subgroup
Description
1
Static tests at
Temp (°C)
+25
2
Static tests at
+125
3
Static tests at
-55
4
Dynamic tests at
+25
5
Dynamic tests at
+125
6
Dynamic tests at
-55
7
Functional tests at
+25
8A
Functional tests at
+125
8B
Functional tests at
-55
9
Switching tests at
+25
10
Switching tests at
+125
11
Switching tests at
-55
12
Settling time at
+25
13
Settling time at
+125
14
Settling time at
-55
DS96F172/DS96F174 Electrical Characteristics AC/DC Parameters (1)
The following conditions apply, unless otherwise specified.
DC: VCC = 5.5V
AC: VCC = 5.0V
Parameter
Test Conditions
VIL
Logical 0 Input Voltage
VIH
Logical 1 Input Voltage
VIC
Input Clamp Voltage
I = -18mA
VOD1
Differential Output Voltage
IO = 0mA
Notes
Min
Units
0.8
V
1
0.7
V
2, 3
V
1, 2, 3
V
1, 2, 3
V
1, 2, 3
1.5
V
1, 2
1.2
V
3
2.0
V
1, 2, 3
1, 2
2.0
VCC = 4.5V, RL = 54Ω
Figure 7
VOD2
Differential Output Voltage
VOD2
Differential Output Voltage
VCC = 4.5V, RL = 100Ω
Figure 7
ΔVOD1
Change In Magnitude of VOD2
VCC = 4.5V, RL = 54Ω
-1.5
6.0
See
(2)
See (3)
See
(2) (3)
Subgroups
Max
-200
200
mV
-400
400
mV
3
See (3)
-200
200
mV
1, 2
See (2) (3)
-400
400
mV
3
ΔVOD2
Change In Magnitude of VOD2
VCC = 4.5V, RL = 100Ω
VOC
Common Mode Output Voltage
RL = 54Ω
Figure 7
3.0
V
1, 2, 3
VOC
Common Mode Output Voltage
RL = 100Ω
Figure 7
3.0
V
1, 2, 3
ΔVOC
Change in Magnitude of VOC
VCC = 4.5V, RL = 54Ω
Figure 7
See (3)
-200
200
mV
1, 2, 3
ΔVOC
Change in Magnitude of VOC
VCC = 4.5V, RL = 100Ω
Figure 7
See (4)
-200
200
mV
1, 2, 3
IO
Output Current With Power Off
VCC = 0V, VO = -7V to 12V
-50
50
µA
1, 2, 3
(1)
(2)
(3)
(4)
4
All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are reference to ground unless
otherwise specified.
−55°C limit exceeds EIA standard RS−485 specification
Δ|VOD| is the change in magnitude of VOD, that occurs when the input is changed between high and low levels.
Δ|VOC| is the change in magnitude of the VOC that occurs when the input is changed between high and low levels.
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SNOSAS8A – APRIL 2011 – REVISED APRIL 2013
DS96F172/DS96F174 Electrical Characteristics AC/DC Parameters(1) (continued)
The following conditions apply, unless otherwise specified.
DC: VCC = 5.5V
AC: VCC = 5.0V
Parameter
Test Conditions
Notes
Min
Max
Units
Subgroups
-50
50
µA
1, 2, 3
20
µA
1, 2, 3
µA
1, 2, 3
IOZ
High Impedance State Output Current
VO = -7V to 12V
IIH
Logical 1 Input Current
VI = 2.4V
IIL
Logical 0 Input Current
VI = 0.4V
ICC
Supply Current
Outputs Enabled
50
mA
1, 2, 3
ICCX
Supply Current
Outputs Disabled
30
mA
1, 2, 3
-50
(5)
-250
mA
1, 2, 3
-150
mA
1, 2, 3
IOS1
Short Circuit Output Current
VO = -7V
See
IOS2
Short Circuit Output Current
VO = 0V
See (5)
IOS3
Short Circuit Output Current
VO = VCC
See (5)
150
mA
1, 2, 3
Short Circuit Output Current
VO = 12V
(5)
250
mA
1, 2, 3
tPLH
Propagation Delay Lo to Hi level
RL = 27Ω, CL = 15pF
Figure 10
25
ns
10, 11
16
ns
9
tPHL
Propagation Delay Hi to Low Level
RL = 27Ω, CL = 15pF
Figure 10
25
ns
10, 11
16
ns
9
RL = 60Ω
10
ns
10, 11
4
ns
9
RL = 110Ω, CL = 50pF
Figure 12
40
ns
10, 11
25
ns
9
Output Disable Time From High Level
RL = 110Ω, CL = 50pF
Figure 11
80
ns
10, 11
30
ns
9
Output Enable Time to Low Level
RL = 110Ω, CL = 50pF
Figure 12
100
ns
10, 11
40
ns
9
RL = 110Ω, CL = 50pF
Figure 10
40
ns
10, 11
32
ns
9
RL = 60Ω, CL = 15pF
Figure 9
30
ns
10, 11
22
ns
9
RL = 60Ω, CL = 15pF
Figure 9
40
ns
10, 11
22
ns
9
IOS4
SKEW
tLZ
tHZ
tZL
tZH
tDD
tTD
(5)
Output to Output Delay Time
Output Disable Time From Low Level
Output Enable Time to High Level
Differential Output Delay Time
Differential Output Transition Time
See
0.2µF cap is connected between the output and Gnd to reduce oscillation.
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PARAMETER MEASUREMENT INFORMATION
Note 10: DS96F172 with active high and active low Enables is
shown. DS96F174 has active high Enable only.
Figure 7. Differential and Common Mode Output
Voltage
Note 10: DS96F172 with active high and active low Enables is
shown. DS96F174 has active high Enable only.
Figure 8. Differential Output Voltage with Varying
Common Mode Voltage
Note 8:The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, duty cycle = 50%,
tr ≤ 5.0 ns, tf ≤ 5.0 ns, ZO = 50Ω.
Note 9:CL includes probe and jig capacitance.
Note 10: DS96F172 with active high and active low Enables is shown. DS96F174 has active high Enable only.
Figure 9. Differential Output Delay and Transition Times
Note 8:The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, duty cycle = 50%,
tr ≤ 5.0 ns, tf ≤ 5.0 ns, ZO = 50Ω.
Note 9:CL includes probe and jig capacitance.
Note 10: DS96F172 with active high and active low Enables is shown. DS96F174 has active high Enable only.
Figure 10. Propagation Delay Times
6
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SNOSAS8A – APRIL 2011 – REVISED APRIL 2013
PARAMETER MEASUREMENT INFORMATION (continued)
Note 8:The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, duty cycle = 50%,
tr ≤ 5.0 ns, tf ≤ 5.0 ns, ZO = 50Ω.
Note 9:CL includes probe and jig capacitance.
Note 11:To test the active low Enable E of DS96F172 ground E and apply an inverted waveform to E . DS96F174
has active high Enable only.
Figure 11. tZH and tHZ
Note 8:The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, duty cycle = 50%,
tr ≤ 5.0 ns, tf ≤ 5.0 ns, ZO = 50Ω.
Note 9:CL includes probe and jig capacitance.
Note 11:To test the active low Enable E of DS96F172 ground E and apply an inverted waveform to E . DS96F174
has active high Enable only.
Figure 12. tZL, tLZ, tLZL
NOTE
For more information see Application Bulletin, Contact Product Marketing.
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TYPICAL APPLICATION
The line length should be terminated at both ends in its characteristic impedance.
Stub lengths off the main line should be kept as short as possible.
8
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SNOSAS8A – APRIL 2011 – REVISED APRIL 2013
REVISION HISTORY
Released
Revision
8–Apr-11
A
Section
New Release, Corporate format
Changes
2 MDS data sheets converted into one Corp. data
sheet format. MNDS96F172M-X Rev 1A0 &
MNDS96F174M-X Rev 1B0 will be archived.
Changes from Original (April 2013) to Revision A
•
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 8
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
(3)
Top-Side Markings
(4)
5962-9076501M2A
ACTIVE
LCCC
NAJ
20
50
TBD
Call TI
Call TI
-55 to 125
DS96F172ME
/883 Q
5962-90765
01M2A ACO
01M2A >T
5962-9076501MEA
ACTIVE
CDIP
NFE
16
25
TBD
Call TI
Call TI
-55 to 125
DS96F172MJ/883
5962-9076501MEA Q
5962-9076502M2A
ACTIVE
LCCC
NAJ
20
50
TBD
Call TI
Call TI
-55 to 125
DS96F174ME
/883 Q
5962-90765
02M2A ACO
02M2A >T
5962-9076502MEA
ACTIVE
CDIP
NFE
16
25
TBD
Call TI
Call TI
-55 to 125
DS96F174MJ/883
5962-9076502MEA Q
5962-9076502VEA
ACTIVE
CDIP
NFE
16
25
TBD
Call TI
Call TI
-55 to 125
DS96F174MJ-QMLV
5962-9076502VEA Q
DS96F172ME/883
ACTIVE
LCCC
NAJ
20
50
TBD
Call TI
Call TI
-55 to 125
DS96F172ME
/883 Q
5962-90765
01M2A ACO
01M2A >T
DS96F172MJ/883
ACTIVE
CDIP
NFE
16
25
TBD
Call TI
Call TI
-55 to 125
DS96F172MJ/883
5962-9076501MEA Q
DS96F174ME/883
ACTIVE
LCCC
NAJ
20
50
TBD
Call TI
Call TI
-55 to 125
DS96F174ME
/883 Q
5962-90765
02M2A ACO
02M2A >T
DS96F174MJ-QMLV
ACTIVE
CDIP
NFE
16
25
TBD
Call TI
Call TI
-55 to 125
DS96F174MJ-QMLV
5962-9076502VEA Q
DS96F174MJ/883
ACTIVE
CDIP
NFE
16
25
TBD
Call TI
Call TI
-55 to 125
DS96F174MJ/883
5962-9076502MEA Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2013
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DS96F174MQML, DS96F174MQML-SP :
• Military: DS96F174MQML
• Space: DS96F174MQML-SP
NOTE: Qualified Version Definitions:
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 2
MECHANICAL DATA
NFE0016A
J0016A
J16A (REV L)
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MECHANICAL DATA
NAJ0020A
E20A (Rev F)
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