INTEGRATED CIRCUITS DATA SHEET PNX3000 Analog front end for digital video processors Preliminary specification Supersedes data of 2004 Jun 24 2004 Oct 04 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 Vision IF DTV IF Sound IF CVBS/YC source selector RGB/YPbPr source selector Video ADCs and anti-alias filters Audio source selectors and A to D converters Microphone inputs Clock generation, timing circuitry and black level clamping Data link transmitters I2C-bus transceiver Power supply circuit East-west interface 8 I2C-BUS SPECIFICATION 8.1 8.2 Input control registers Output status registers 2004 Oct 04 9 LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 QUALITY SPECIFICATION 11.1 Latch-up performance 12 CHARACTERISTICS 13 TEST AND APPLICATION INFORMATION 13.1 13.2 Power supply decoupling Application diagram 14 PACKAGE OUTLINE 15 SOLDERING 15.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 15.2 15.3 15.4 15.5 2 16 DATA SHEET STATUS 17 DEFINITIONS 18 DISCLAIMERS 19 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Preliminary specification Analog front end for digital video processors 1 PNX3000 FEATURES • Multi-standard vision IF circuit with alignment-free PLL demodulator without external components • Internal (switchable) time-constant for the IF AGC circuit • DTV IF circuit for gain control of digital broadcast TV signals • Two microphone amplifiers with adjustable gain • Sound IF amplifier with separate AGC circuit for quasi-split sound • Three analog audio outputs for SCART and line out with independent source selection for each output • IF circuit can also be used for intercarrier sound • Four 1-bit audio sigma delta ADCs for the conversion of audio and microphone signals • Analog demodulator for AM sound • Three serial data link transmitters for interfacing with the digital video processor at a bit rate of 594 Mbit/s per data link • Integrated sound trap and group delay correction • Video ident function detects the presence of a video signal • Voltage to current converter for driving external east-west power amplifier • Video source selector with four external CVBS or YC inputs and two analog CVBS outputs with independent source selection for each output • I2C-bus transceiver with selectable slave address and maskable interrupt output. • Two linear inputs for 1fH or 2fH RGB signals with source selector; the RGB signals are converted to YUV before A to D conversion; both inputs can also be used as YPbPr input for DVD or set top box 2 The PNX3000 is an analog front end for digital video processors. It contains an IF circuit for both analog and digital broadcast signals, input selectors and ADCs for analog video and audio signals. The digital output signals are made available via three serial data links. • Integrated anti-alias filters for video Analog to Digital Converters (ADCs) • Four 10-bit video ADCs for the conversion of CVBS, YC, YUV and down-mixed sound IF signals • Up to three different A to D converted video channels are available simultaneously (e.g. CVBS, YC and YUV) The IC has a supply voltage of 5 V. The supply voltage of the analog audio part can be 5 V or 8 V, depending on the maximum signal amplitudes that are required. • Audio source selector with five stereo inputs for analog audio and two microphone inputs 3 GENERAL DESCRIPTION ORDERING INFORMATION PACKAGE TYPE NUMBER PNX3000HL/N3 2004 Oct 04 NAME DESCRIPTION VERSION LQFP128 plastic low profile quad flat package; 128 leads; body 14 × 20 × 1.4 mm SOT425-1 3 Philips Semiconductors Preliminary specification Analog front end for digital video processors 4 PNX3000 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VP main supply voltage IP main supply current 4.75 5.0 5.25 V − 285 320 mA VCC(1ASW), VCC(2ASW) audio supply voltage note 1 4.75 8.0 8.4 V ICC(ASW) note 1 − 3.5 5.0 mA audio supply current Input signals Vi(VIF)(dif)(rms) video IF amplifier sensitivity (differential; RMS value) − 75 150 µV Vi(DTVIF)(dif)(rms) video DTV IF amplifier sensitivity (differential; RMS value) − 75 150 µV − 45 tbf dBµV − 1.0 1.76 V note 2 − 0.7 1.0 V −3 dB Vi(SIF)(rms) sound IF amplifier sensitivity (RMS value) Vi(CVBS/Y)(p-p) CVBS or Y input voltage (peak-to-peak value) Vi(RGB)(b-w) RGB inputs (black-to-white value) Vi(Y)(p-p) luminance input signal (peak-to-peak value) note 2 − 1.0 1.43 V Vi(Pb)(p-p) Pb input signal (peak-to-peak value) note 2 − 0.7 1.0 V Vi(Pr)(p-p) Pr input signal (peak-to-peak value) note 2 − 0.7 1.0 V Bv(−3dB) −3 dB signal bandwidth 1fH mode − 9 − MHz fsample sample frequency 1fH mode − 27 − MHz RES resolution − 10 − bit Video ADCs Analog output signals Vo(CVBS)(p-p) analog CVBS output voltage (peak-to-peak value) − 2.0 − V Io(TUNERAGC) tuner AGC output current range 0 − 1 mA Notes 1. The supply voltage for the analog audio part of the IC can be 5 V or 8 V. For a supply voltage of 5 V the maximum signal amplitudes at in- and outputs are 1 V (RMS). For a supply voltage of 8 V the maximum amplitudes are 2 V (RMS). 2. The RGB inputs can also be used as YPbPr input. The selection is made via the I2C-bus. The YPbPr input sensitivity is in accordance with the DVD player specification. 2004 Oct 04 4 Philips Semiconductors Preliminary specification Analog front end for digital video processors 5 PNX3000 BLOCK DIAGRAM handbook, full pagewidth CVBSOUTA 1× CVBSOUTB 2NDSIFEXT (FMRAD) CVBSOUTIF SIFAGC SIF AMP 2 SIFIN QSS MIXER & AM SND DEMOD 2nd SIF internal DTV 1st IF 2 SWITCH Fpc DTVOUT 2 VIFIN 2 DTVIFIN IF SWITCH VIF AMP 2 DTVIFAGC TUNERAGC DTVIFPLL VIFPLL CVBS0 VIF PLL & DTVIF MIXER DTV 2nd IF SNDTRAP & GROUP DELAY PNX3000 CVBS_IF CVBS1 CVBS2 CVBS/Y3 C3 CVBS/Y4 C4 YCOMB CCOMB CVBS_DTV CVBS/Y_PRIM A CVBS PRIM. SWITCH 10 DATA LINK 1 C D VIDEO IDENT CLK 4 DLINK1 297 MHz ICLP CLP_PRIM 2ndSIF AGC DET AM sound CVBS OUT SWITCH & CVBS SEC. SWITCH 2NDSIFAGC VCA A 10 DATA LINK 3 D CVBS_SEC 4 DLINK3 CLK 297 MHz ICLP CLP_SEC CLP_YUV ICLP A ICLP Yyuv R1/PR1/V1 G1/Y1/Y1 B1/PB1/U1 RGB/YUV MATRIX & SWITCH R2/PR2/V2 G2/Y2/Y2 B2/PB2/U2 U L1/AMint A L R1/AMext A R L2/MIC1/PipMono 2 R2/MIC2/AM 2 R MIC1 MIC2 AUDIO SWITCH (DIGITAL OUT) VD2V5 27 MHz 13.5 MHz 54 MHz 6.75 MHz ADC CLOCK PLL AUDIO SWITCH (ANALOG OUT) DIVIDER HV_PRIM HV_SEC CLP_SEC AUDIO AMPS VOLTAGE TO CURRENT XREF 13.5 or 27 MHz TIMING CIRCUIT CLP_YUV I2C-BUS INTERFACE IRQ MCE430 REW DSNDL1 LINEL SCART2R LINER SCART2L DSNDR1 DSNDL2 SCART1L DSNDR2 EWVIN SCART1R Fig.1 Block diagram. 2004 Oct 04 VAUD RREF CLP_PRIM R1 R2 R3 R4 R5 L1 L2 L3 L4 L5 AM EXT VDEFL VAUDO VAUDS DATALINK PLL D AM int VDEFLS BAND GAP REF 297 MHz 2 BGDEC VDEFLO CLK secondary digital audio L A 297 MHz DLINK2 10 D MIC AMPS MIC2 A 4 D primary digital audio 2 D MIC1 CLK A V D DATA LINK 2 10 D 5 ADR SCL SDA EWIOUT Philips Semiconductors Preliminary specification Analog front end for digital video processors 6 PNX3000 PINNING SYMBOL PIN DESCRIPTION CVBS2 1 CVBS2 input VAUDO 2 DC output voltage for supply of audio DACs in digital decoder VAUDS 3 sense voltage input for audio DACs supply CVBS/Y3 4 external CVBS/Y3 input C3 5 external CHROMA3 input GND(VSW) 6 ground video switch BGDEC 7 bandgap decoupling CVBS/Y4 8 external CVBS/Y4 input C4 9 external CHROMA4 input FUSE 10 fused lead GND(FILT) 11 ground filters CVBS_DTV 12 input for CVBS encoded signal from DTV decoder RREF 13 reference current input VCC(FILT) 14 supply voltage filters (5 V) YCOMB 15 Y signal input from 3D Comb filter CCOMB 16 C signal input from 3D Comb filter AMEXT 17 external AM mono input TESTPIN3 18 test pin 3; must be left open CVBSOUTA 19 CVBS or Y+CHROMA output A VDEFLO 20 DC output voltage for supply of deflection DACs in digital decoder VDEFLS 21 sense input voltage for deflection DACs supply CVBSOUTB 22 CVBS or Y+CHROMA output B FUSE 23 fused lead TESTPIN2 24 test pin 2; connect to ground R1/PR1/V1 25 R input 1 of RGB signal Pr input 1 of YPbPr signal or V input 1 of YUV signal G1/Y1/Y1 26 G input 1 of RGB signal or Y input 1 of YPbPr signal or Y input 1 of YUV signal B1/PB1/U1 27 B input 1 of RGB signal Pb input 1 of YPbPr signal or U input 1 of YUV signal VCC(RGB) 28 supply voltage RGB matrix (5 V) GND(RGB) 29 ground RGB matrix R2/PR2/V2 30 R input 2 of RGB signal Pr input 2 of YPbPr signal or V input 2 of YUV signal G2/Y2/Y2 31 G input 2 of RGB signal or Y input 2 of YPbPr signal or Y input 2 of YUV signal B2/PB2/U2 32 B input 2 of RGB signal Pb input 2 of YPbPr signal or U input 2 of YUV signal FUSE 33 fused lead GND(VADC) 34 ground video ADCs VCC(VADC) 35 supply voltage video ADCs (5 V) EWVIN 36 east-west input voltage EWIOUT 37 east-west output current REW 38 east-west voltage to current conversion resistor ADR 39 I2C-bus address selection input XREF 40 XTAL reference frequency input 2004 Oct 04 6 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PNX3000 PIN DESCRIPTION FUSE 41 fused lead IRQ 42 interrupt request output SDA 43 I2C-bus serial data input and output SCL 44 I2C-bus serial clock input HV_SEC 45 horizontal and vertical sync input for secondary video channel HV_PRIM 46 horizontal and vertical sync input for primary video channel VD2V5 47 decoupling of internal digital supply voltage GND(DIG) 48 digital ground VCC(DIG) 49 digital supply voltage (5 V) STROBE3N 50 strobe negative data link 3 STROBE3P 51 strobe positive data link 3 DATA3N 52 data negative data link 3 DATA3P 53 data positive data link 3 FUSE 54 fused lead STROBE2N 55 strobe negative data link 2 STROBE2P 56 strobe positive data link 2 DATA2N 57 data negative data link 2 DATA2P 58 data positive data link 2 GND(I2D) 59 ground data links STROBE1N 60 strobe negative data link 1 STROBE1P 61 strobe positive data link 1 DATA1N 62 data negative data link 1 DATA1P 63 data positive data link 1 VCC(I2D) 64 supply voltage data links (5 V) SCART2R 65 audio output for SCART2 right SCART2L 66 audio output for SCART2 left LINER 67 audio line output right LINEL 68 audio line output left SCART1R 69 audio output for SCART1 right SCART1L 70 audio output for SCART1 left FUSE 71 fused lead DSNDR2 72 audio signal input from digital decoder right 2 DSNDL2 73 audio signal input from digital decoder left 2 DSNDR1 74 audio signal input from digital decoder right 1 DSNDL1 75 audio signal input from digital decoder left 1 GND(AADC) 76 ground audio ADCs VCC(AADC) 77 supply voltage audio ADCs (5 V) FUSE 78 fused lead R4 79 right input audio 4 L4 80 left input audio 4 R3 81 right input audio 3 2004 Oct 04 7 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PNX3000 PIN DESCRIPTION L3 82 left input audio 3 R2 83 right input audio 2 L2 84 left input audio 2 R1 85 right input audio 1 L1 86 left input audio 1 GND(2ASW) 87 ground 2 audio switch VCC(2ASW) 88 supply voltage 2 audio switch (audio output buffers; 5 or 8 V) VAADCREF 89 decoupling of reference voltage for audio ADCs VAADCN 90 0 V reference voltage for audio ADCs (GND) VAADCP 91 full scale reference voltage for audio ADCs (5 V) MIC2N 92 microphone input 2, negative MIC2P 93 microphone input 2, positive MIC1N 94 microphone input 1, negative MIC1P 95 microphone input 1, positive FUSE 96 fused lead GND(1ASW) 97 ground 1 audio switch VCC(1ASW) 98 supply voltage 1 audio switch (audio input buffers; 5 or 8 V) SIFINP 99 sound IF input, positive SIFINN 100 sound IF input, negative SIFAGC 101 control voltage for sound IF AGC DTVIFAGC 102 control voltage for DTV IF AGC DTVIFINP 103 DTV IF input, positive DTVIFINN 104 DTV IF input, negative TUNERAGC 105 tuner AGC output FUSE 106 fused lead VIFINP 107 vision IF input, positive VIFINN 108 vision IF input, negative DTVIFPLL 109 output loop filter DTV IF PLL demodulator VCC(IF) 110 supply voltage IF circuit (5 V) VIFPLL 111 output loop filter VIF PLL demodulator GND(1IF) 112 ground 1 IF circuit 2NDSIFEXT 113 second sound IF input 2NDSIFAGC 114 second sound IF AGC capacitor GND(2IF) 115 ground 2 IF circuit DTVOUTP 116 DTV output, positive DTVOUTN 117 DTV output, negative VCC(SUP) 118 supply voltage of supply circuit (5 V) FUSE 119 fused lead CVBSOUTIF 120 CVBS output of IF circuit GND(SUP) 121 ground of supply circuit VCC(1VSW) 122 supply voltage 1 of video switch (5 V) 2004 Oct 04 8 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL CVBS0 PNX3000 PIN 123 DESCRIPTION CVBS0 input for CVBS from IF part TESTPIN1 124 test pin 1; connect to ground VCC(2VSW) 125 supply voltage 2 of video switch (5 V) CVBS1 126 CVBS1 input R5 127 right input audio 5 L5 128 left input audio 5 2004 Oct 04 9 Philips Semiconductors Preliminary specification 103 DTVIFINP 104 DTVIFINN 105 TUNERAGC 106 FUSE 107 VIFINP 108 VIFINN 109 DTVIFPLL 110 VCC(IF) 111 VIFPLL 112 GND(1IF) 113 2NDSIFEXT 114 2NDSIFAGC 115 GND(2IF) 116 DTVOUTP 117 DTVOUTN PNX3000 118 VCC(SUP) 119 FUSE 120 CVBSOUTIF 121 GND(SUP) 122 VCC(1VSW) 123 CVBS0 126 CVBS1 127 R5 128 L5 handbook, full pagewidth 125 VCC(2VSW) 124 TESTPIN1 Analog front end for digital video processors CVBS2 1 VAUDO 2 101 SIFAGC VAUDS 3 100 SIFINN CVBS/Y3 4 C3 5 99 SIFINP 98 VCC(1ASW) GND(VSW) 6 97 GND(1ASW) BGDEC 7 96 FUSE CVBS/Y4 8 95 MIC1P C4 9 94 MIC1N FUSE 10 93 MIC2P GND(FILT) 11 92 MIC2N 102 DTVIFAGC CVBS_DTV 12 91 VAADCP RREF 13 90 VAADCN VCC(FILT) 14 89 VAADCREF YCOMB 15 88 VCC(2ASW) CCOMB 16 87 GND(2ASW) AMEXT 17 86 L1 TESTPIN3 18 85 R1 CVBSOUTA 19 84 L2 PNX3000HL VDEFLO 20 83 R2 VDEFLS 21 82 L3 CVBSOUTB 22 81 R3 FUSE 23 80 L4 TESTPIN2 24 79 R4 R1/PR1/V1 25 78 FUSE G1/Y1/Y1 26 77 VCC(AADC) B1/PB1/U1 27 76 GND(AADC) VCC(RGB) 28 75 DSNDL1 GND(RGB) 29 74 DSNDR1 R2/PR2/V2 30 73 DSNDL2 G2/Y2/Y2 31 72 DSNDR2 B2/PB2/U2 32 71 FUSE FUSE 33 70 SCART1L GND(VADC) 34 69 SCART1R VCC(VADC) 35 68 LINEL EWVIN 36 67 LINER Fig.2 Pinning configuration. 2004 Oct 04 10 VCC(I2D) 64 DATA1P 63 DATA1N 62 STROBE1P 61 STROBE1N 60 DATA2P 58 GND(I2D) 59 DATA2N 57 STROBE2P 56 STROBE2N 55 FUSE 54 DATA3P 53 DATA3N 52 STROBE3P 51 STROBE3N 50 VCC(DIG) 49 GND(DIG) 48 VD2V5 47 HV_PRIM 46 SCL 44 HV_SEC 45 SDA 43 IRQ 42 FUSE 41 65 SCART2R ADR 39 66 SCART2L REW 38 XREF 40 EWIOUT 37 MCE429 Philips Semiconductors Preliminary specification Analog front end for digital video processors 7 7.1 PNX3000 FUNCTIONAL DESCRIPTION that is approximately 4 MHz higher than the incoming 1st IF centre frequency. Vision IF In DTV 2nd IF mode the 2nd IF signal is obtained by down-mixing the incoming DTV IF signal with the IF VCO signal. The low-pass filtered DTV 2nd IF signal is available as a differential signal at the DTV output. This signal may have a maximum bandwidth of 10 MHz. The VCO frequency is programmed via the I2C-bus in steps of 250 kHz. The IF amplifier contains 3 AC-coupled control stages which have a total gain control range of more than 66 dB. The video signal is demodulated by means of an alignment-free PLL carrier regenerator with an internal VCO. This VCO is calibrated by means of a digital control circuit which uses the external crystal frequency as a reference. The frequency setting for the various standards (33.4 MHz, 33.9 MHz, 38 MHz, 38.9 MHz, 45.75 MHz and 58.75 MHz) is realised via the I2C-bus. To improve performance for phase modulated carrier signals the control speed of the PLL can be increased by setting bit FFI. In DTV mode the AGC time constant is determined by a capacitor on pin DTVIFAGC. There are two AGC modes: internal and external. In the internal AGC mode the gain is controlled by an internal AGC detector. The external AGC mode is activated by bit AGCM. In this mode the appropriate AGC pin is used as input, so that the IF gain can be controlled by the DTV channel decoder. The AFC output is generated by the digital control circuit of the IF PLL demodulator and can be read via the I2C-bus. For fast search tuning systems the window of the AFC can be increased with a factor of three with bus bit AFW. The IF PLL has two pins for connection of the PLL loop filters, one for analog TV and one for DTV. This allows each loop filter to be optimized for its application. The AGC-detector operates on top sync or top white level. The demodulation polarity is switched via the I2C-bus. The AGC detector capacitor is integrated. The time-constant can be chosen via I2C-bus bits AGC1 and AGC0. The AGC has also an external mode which is activated by bit AGCM. In this mode the IF gain is determined by an external voltage on pin DTVIFAGC. 7.3 The PNX3000 has a separate sound IF input to enable quasi-split sound applications. The sound IF amplifier is similar to the vision IF amplifier and has a gain control range of about 55 dB. The AGC detector measures the average level of the AM or FM SIF carrier and ensures a constant signal amplitude for the AM demodulator and Quasi-Split Sound (QSS) mixer. The IC has an integrated sound trap filter. The filter is constructed as a cascade of three separate traps, to realize sufficient suppression of the first and second sound carriers. The trap frequencies are selected via the I2C-bus. The single reference QSS mixer is realised by a multiplier. In this multiplier the SIF signal is converted to the intercarrier frequency by mixing it with the regenerated picture carrier from the video IF VCO. With this system a high performance stereo sound processing can be achieved. The IC has an integrated group delay correction filter. The filter can be switched between the PAL BG curve and a flat group delay response characteristic. This has the advantage that in multi-standard receivers the video SAW filter does not need to be switchable. 7.2 For applications without a SIF SAW filter the IC can also be used in intercarrier mode. In this mode the composite video signal from the VIF amplifier is fed to the QSS mixer and converted to the intercarrier frequency. DTV IF Apart from processing analog TV signals, the IF circuit can also be used to preprocess digital TV signals before they are sent to a DTV channel decoder. For this application the two modes of operation are DTV 1st IF and DTV 2nd IF. For both operating modes the IF PLL must be set to synthesizer mode. AM sound demodulation is realised in the analog domain by the QSS mixer. The modulated SIF signal is multiplied in phase with the limited SIF signal. The demodulator output signal is low-pass filtered for suppression of the carrier harmonics. The demodulated AM signal can be digitized by one of the audio ADCs. In DTV 1st IF mode only the AGC function of the IF circuit is used, so the DTV channel decoder must be able to handle the 1st IF frequency. Because the AGC detector operates on the down-mixed 2nd IF signal, it is still important to program a valid frequency for the IF VCO. It is recommended to set the frequency of the VCO to a value 2004 Oct 04 Sound IF The QSS mixer can also be used for down-mixing an FM radio IF signal to an intercarrier frequency, so that it can be demodulated by the digital decoder. The IF PLL must be set to synthesizer mode in this case. The preferred solution is to supply the FM radio signal via a 11 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 7.5 separate SAW or ceramic filter to the DTV input of the PNX3000. The reason is that the selectivity of a SAW filter for TV sound is not sufficient for FM radio and, if the SIF input is used, no tuner AGC information is available. The IC has two RGB inputs. Both inputs can also be used as YPbPr input for connecting video sources with an YPbPr output like a DVD player. The RGB inputs can also be used for fast insertion of RGB signals (for instance on screen display menus) in the primary CVBS signal. The fast insertion switch is located in the digital video processor. For high performance FM radio it is recommended that a 10.7 MHz FM radio IF signal is supplied to the external 2nd SIF input. In this case the IF signal must be filtered by an external bandpass filter, that also functions as an anti-alias filter. The low-pass filter before the 2nd SIF ADC must be bypassed by setting bus bit SLPM. The RGB signals are converted to YUV before further processing. The YUV output signal is digitized by two ADCs. The U and V components have half the bandwidth of the Y signal, therefore the U and V signals are multiplexed and digitized by one ADC. The IC includes a separate AGC circuit for the 2nd SIF signal. This AGC is needed for intercarrier sound applications and when an external sound IF signal is supplied to the 2nd SIF input. The AGC amplifier is preceded by a second order high-pass filter for suppression of video signal components. The AGC time constant is determined by an external capacitor. 7.4 7.6 Video ADCs and anti-alias filters The PNX3000 contains four video ADCs for analog and digital video broadcast signals. The clock frequency for the ADCs is either 27 MHz or 54 MHz. Two analog signals can be multiplexed at the input of one ADC. Then the clock frequency of the ADC is 54 MHz and the sample frequency of each channel is 27 MHz. CVBS/YC source selector The video input selector consists of four independent source selectors, that can select between the CVBS signal coming from the IF part and four external CVBS signals. Two of the external CVBS inputs can also be used as YC input. One selector is used to select the signal for of the primary video channel. A second selector selects the CVBS or YC signal for the secondary channel. The third and fourth selectors are used to select analog outputs CVBS A and B, which can be used for SCART or line output. The video ADCs are 10-bit folding ADCs. The sample frequency for standard 1fH video signals is 27 MHz. For the YUV channel the sample frequency of the U and V components is half the sample frequency of the Y signal. For 2fH YPbPr or RGB input signals (for instance 480p or 1080i ATSC signals), the frequency that is used to sample the YUV signals is twice as high as for 1fH signals. The sample frequency is 54 MHz for Y and 27 MHz for U and V. The high sample frequency requires two data links to transport the video data to the digital video processor. The primary channel can be a CVBS or YC signal. If a YC signal is selected for the secondary channel or for the external CVBS outputs A or B, the luminance and chrominance signals are added to obtain a CVBS signal. The anti-alias filters before the ADCs limit the signal bandwidth to prevent aliasing effects. The filters for YUV can be bypassed by means of two separate bits: bit BPY for the Y filter and bit BPUV for the U and V filters. This enables the use of external anti-alias filters with increased bandwidth for 2fH, RGB or YPbPr input signals. The IC has an extra YC input for connection of a 3D comb filter. The comb signal can only be selected for the primary video channel. The input pin CVBS_DTV allows an analog CVBS signal derived from a digital broadcast (MPEG) signal to be recorded with an analog VCR. This signal cannot be selected for the primary video channel. Table 1 shows the signal bandwidths and sample rates for the various types of video signals. Table 2 shows which video signals are sent to the digital video processor for both data link modes. The video identification circuit detects the presence of a video signal on the CVBS_IF input (pin CVBS0). The identification output is normally used to detect transmitters during search tuning and can be read via the I2C-bus. The circuit can also be used to monitor the selected primary CVBS or YC signal. Either mode is selected by bit VIM. 2004 Oct 04 RGB/YPbPr source selector 12 Philips Semiconductors Preliminary specification Analog front end for digital video processors Table 1 PNX3000 Overview of anti-alias filter bandwidths and video signal sample rates. SIGNAL TYPE SIGNAL COMPONENT SIGNAL BAND −1.0 dB (MHz) SIGNAL BAND −3.0 dB (MHz) SAMPLE FREQUENCY (MHz) 8 9 27 8 9 27 CVBS YC Y YUV 1fH YUV 2fH C 8 9 27 Y 8 9 27 U 4 4.5 13.5 V 4 4.5 13.5 Y 16 18 54 U 8 9 27 V 8 9 27 DTV − 10 12 − 2nd SIF − 8 9 27 7.7 Audio source selectors and A to D converters 7.8 The PNX3000 contains two different audio source selectors. The first selector selects which audio signals are routed to the audio ADCs for further processing in the digital domain. The two microphone inputs are also connected to this selector. The selector has two outputs, a primary channel and a secondary channel. The primary audio channel is used for one stereo signal. The secondary audio channel can carry a second stereo signal, or two microphone signals, or one mono signal and one microphone signal or one mono signal and one AM sound signal. The IC has two microphone inputs. One microphone input can be used for voice control of the TV set with the help of an intelligent voice command decoder. The second input can be used for connection of a microphone for Karaoke. To allow the use of microphones with different sensitivities the gain of each microphone amplifier is switchable between two values via the I2C-bus. 7.9 Clock generation, timing circuitry and black level clamping The IC contains two PLL circuits that derive the sample clock for the ADCs and the bit and word clocks for the data links from an external reference frequency. The reference frequency must be a stable frequency of either 13.5 MHz or 27 MHz from a crystal oscillator. The internal reference frequency is always 13.5 MHz. If the external frequency is 27 MHz a prescaler must be activated by bus bit FXT. The second selector selects which audio signals are fed to the analog audio outputs for SCART and line out. This selector also has two stereo inputs for demodulated sound signals coming from the digital video processor. The gain from an external audio input to an analog output is 1. A supply voltage of 5 V allows input and output amplitudes of 1 V (RMS) full scale. The PNX3000 has separate supply voltage pins for the audio selector circuit. To allow for input and output amplitudes of 2 V (RMS) full scale, as required for compliance with the SCART specification, an audio supply voltage of 8 V must be used. One PLL is used to multiply the 13.5 MHz reference frequency to the 27 MHz and 54 MHz clock frequencies that are needed for the video ADCs. A second PLL is used to obtain the 297 MHz bit clock for the data link transmitters. The audio ADCs are 1-bit sigma-delta converters that operate at a clock frequency of 6.75 MHz. The audio A to D clock is synchronous with the video A to D clock, so that audio and video data can be sent over the same data links. The effective audio sample rate is f clk ---------- = 52.7 ksample/s. 128 2004 Oct 04 Microphone inputs A special timing circuit is used to generate the horizontal and vertical timing pulses that are needed in the IF part, and also for clamping the black level of the selected video signals to a defined value at the output of the video ADCs. The horizontal and vertical timing information of the primary and secondary video channels must be supplied by the digital video processor on pins HV_PRIM and HV_SEC. The signal on these pins must consist of a 13 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 horizontal timing pulse that starts just before and ends just after the horizontal sync pulse of the selected video signal. To enable detection of the vertical blanking period, the horizontal pulses must be wider during a number of lines in the vertical blanking interval. Table 2 shows which video signals are sent to the digital video processor for both data link modes. In the standard mode up to three video channels plus one sound IF signal are digitized and transferred simultaneously over the data links. The clamp signal inside the IC is generated with the help of the external horizontal timing pulse and the 13.5 MHz clock. The vertical timing information is used to disable the black level clamp, so that the black level is not disturbed by the vertical sync pulse on the video signal. The clamp pulse for the YUV channel can be derived from the primary or the secondary HV pulse, and is selected by bus bit CLPS. The distance between both ICs that are connected via the data link must not be larger than about 10 centimetres. The two wires for each differential signal should be paired in the layout of the printed-circuit board. 7.11 The slave address of the I2C-bus transceiver in the PNX3000 has two possible values, selected via the ADR pin. The maximum bus clock frequency is 400 kHz, and the voltage swing of SCL and SDA can be 3.3 V or 5 V. The I2C-bus transceiver also has a hardwired IRQ output (open drain and LOW-active) for interruption of the microprocessor when the value of an important status bit in status byte 0 changes. The IRQ signal is maskable with register 0FH. To avoid signal disturbance, it is possible to disable the black clamps when the horizontal PLL in the digital video processor is not locked to the selected video signal. This is done by bus bit CMP for the primary CVBS channel and bus bit CMS for the secondary CVBS channel. Special attention is required when the same CVBS input is selected for primary and secondary CVBS channels. In this case the black level clamp loop is only closed for the primary CVBS input. Due to internal offsets this will normally result in a deviation on the black level of the digitized secondary CVBS output. 7.10 7.12 Power supply circuit An internal bandgap circuit generates a stable voltage of 1.25 V. This voltage is multiplied to a reference voltage of 2.3 V, and a digital supply voltage of 2.5 V. These two voltages must be decoupled by external capacitors. A 1/2VP reference voltage for the audio ADCs also requires an external decoupling capacitor. The PNX3000 contains two voltage regulators to supply the SDACs that are used in the digital video processor. Each regulator requires a few external components (one transistor, two resistors and a decoupling capacitor). The output voltage is adjustable between 1.25 V and 3.3 V by selection of external resistors values. Data link transmitters Three serial data links are used for transportation of the digital video and audio data coming from the ADCs in the PNX3000 to the digital video processor. The use of serial data connections results in a considerable reduction in pin count and the number of connection wires that are needed between both ICs. The communication between data link transmitter and data link receiver consists of two signals, a data signal and a strobe signal. The two signals together contain the data, bit-sync and word-sync information. For optimal EMC performance both data and strobe are low voltage differential signals. The voltage swing on each wire is 300 mV. 7.13 East-west interface The PNX3000 contains a voltage to current converter that serves as the interface between the voltage output of the digital video processor and the current input of the east-west stage of the vertical deflection amplifier (TDA8358). The transconductance is determined by the value of an external resistor. Each data word sent over a data link consists of 44 bits: 4 video samples of 10 bits each, 2 audio bits and 2 word-sync bits. The word clock is 13.5 MHz. The data rate on each of the three data links is 594 Mbit/s. 2004 Oct 04 I2C-bus transceiver 14 Philips Semiconductors Preliminary specification Analog front end for digital video processors Table 2 PNX3000 Overview of data link modes DATA LINK 1 DATA LINK 2 DATA LINK 3 MODE APPLICATION VIDEO1 8 AUDIO1 VIDEO2 AUDIO2 VIDEO3 TEST 0 standard CVBS/Yprim C L1 R1 Yyuv U,V L2 R2 CVBSsec 2nd SIF HV_P HV_S 1 YUV 2fH input Yyuv L1 R1 U V L2 R2 CVBSsec 2nd SIF HV_P HV_S I2C-BUS SPECIFICATION The slave addresses of the IC are given in Table 3. The circuit operates at clock frequencies of up to 400 kHz. Table 3 Slave addresses (9A or 9E) A6 A5 A4 A3 A2 A1 A0 R/W 1 0 0 1 1 A1 1 1/0 Bit A1 is controlled via the ADR pin, when the pin is connected to ground A1 = 0 and when connected to the positive supply line A1 = 1. When this pin is left open it is connected to ground via an internal resistor. 8.1 Input control registers Table 4 Input control registers; valid subaddresses: 00 to 0F; auto-increment mode available for subaddresses SUB ADDR D7 D6 D5 D4 D3 D2 D1 D0 POR VALUE (HEX) 00 AFN AFW IFS AGCM FFI PMOD AGC1 AGC0 00 Vision IF 1 01 IFON DSIF DFIF DTV IFLH SYNT SSIF QSS 00 IF PLL offset 02 IFGT VAI IFO5 IFO4 IFO3 IFO2 IFO1 IFO0 20 IF tuner take over 03 VA1 VA0 TTO5 TTO4 TTO3 TTO2 TTO1 TTO0 20 IF PLL frequency 04 FXT IFA IFB IFC 0 0 0 0 80 IF synthesizer frequency 05 SF7 SF6 SF5 SF4 SF3 SF2 SF1 SF0 00 Filters 06 BPUV BPY BPP GD SLPM BPS ST1 ST0 00 Data link mode 07 DRND 0 0 HDTV 0 0 0 DM 00 Video switches 0 08 SEC3 SEC2 SEC1 SEC0 PRI3 PRI2 PRI1 PRI0 00 Video switches 1 09 VIM VSW CMS CMP CVA3 CVA2 CVA1 CVA0 36 Video switches 2 and audio mute 0A 0 MA2 MA1 MA0 CVB3 CVB2 CVB1 CVB0 76 RGB switches 0B 0 RSEL MAT DVD 0 0 CMR CLPS 00 Audio switches ADC 0C MONO SEA2 SEA1 SEA0 MNM1 PRA2 PRA1 PRA0 00 Audio switches 0 0D DSG A1S2 A1S1 A1S0 MNM0 A0S2 A0S1 A0S0 00 Audio switches 1 0E 0 M2G AMX M1G MICON A2S2 A2S1 A2S0 00 0F 1(1) IM6 IM5 IM4 IM3 IM2 IM1 IM0 80 FUNCTION Vision IF 0 IRQ mask status byte 0 DATA BYTE Note 1. The value of this bit cannot be changed. 2004 Oct 04 15 Philips Semiconductors Preliminary specification Analog front end for digital video processors Table 5 PNX3000 AFC switch Table 12 IF amplifier on/off AFN MODE IFON MODE 0 normal operation 0 IF amplifier not active 1 AFC not active 1 normal operation Table 6 AFC window AFW AFC WINDOW 0 normal 1 enlarged Table 7 Table 13 Selection of signal on analog DTV output IF sensitivity IFS IF SENSITIVITY 0 normal 1 reduced MODE DFIF 0 0 DTV second IF Y 0 1 DTV first IF N 1 0 2nd SIF internal N 1 1 spare N/A Table 14 Vision IF input select DTV Table 8 Internal or external AGC mode AGCM MODE 0 internal 1 external MODE 0 VIF input 1 DTVIF input Table 15 Calibration of IF PLL demodulator IFLH Table 9 Fast filter IF PLL FFI CONDITION 0 normal time constant 1 increased time constant MODE 0 calibration system active 1 calibration system not active Table 16 IF PLL mode SYNT Table 10 Video modulation standard PMOD CONDITION 0 negative modulation (FM sound) 1 positive modulation (AM sound) MODE 0 normal mode 1 synthesizer mode Table 17 Second sound IF input SSIF Table 11 IF AGC speed MODE 0 internal input 1 external input AGC1 AGC0 0 0 0.7 × norm 0 1 norm 1 0 3 × norm QSS 1 1 6 × norm 0 intercarrier sound 1 quasi split sound 2004 Oct 04 AGC SPEED Table 18 Sound operation 16 LPF ACTIVE DSIF MODE Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 Table 19 IF AGC operation mode IFGT Table 24 External reference frequency MODE FXT CONDITION 0 non gated operation 0 13.5 MHz 1 gated operation; note 1 1 27 MHz Note Table 25 PLL demodulator frequency setting 1. Gated operation improves weak signal performance. Gated operation is automatically disabled if CVBS_IF is not selected as primary or secondary video signal. In this situation bit IFLH should be set to 1 to avoid recalibration of the IF VCO for white video patterns. Table 20 CVBS IF output signal amplitude correction for system I MODE IFA IFB IFC IF FREQUENCY 0 0 0 58.75 MHz 0 0 1 45.75 MHz 0 1 0 38.90 MHz 0 1 1 38.00 MHz 1 0 0 33.40 MHz 1 1 0 33.90 MHz VAI PMOD = 0 PMOD = 1 0 no correction no correction 1 amplitude +8 % amplitude −8 % Table 26 IF VCO synthesizer frequency (SF7 to SF0); note 1 SF7 TO SF0 (DECIMAL NUMBER) Table 21 IF PLL offset adjustment IFO5 TO IFO0 (HEX) CONTROL 00 tbf 20 no correction 3F tbf FREQUENCY 95 f = 24 MHz 255 f = 64 MHz Note 1. fsynth = (N + 1) × 250 kHz; where 95 ≤ N ≤ 255. Table 27 Bypass UV anti-alias filters Table 22 CVBS IF output signal amplitude BPUV OUTPUT SIGNAL AMPLITUDE VA1 VA0 PMOD = 0 PMOD = 1 MODE 0 normal operation 1 UV anti-alias filters bypass 0 0 no correction no correction 0 1 spare spare 1 0 amplitude −5 % amplitude +5 % BPY 1 1 amplitude +5 % amplitude −5 % 0 normal operation 1 Yyuv anti-alias filter bypass Table 28 Bypass Yyuv anti-alias filter Table 23 IF AGC tuner take over TTO5 TO TTO0 (HEX) Table 29 Bypass anti-alias filters of primary CVBS CONTROL BPP 3F tuner take over at IF input signal of 0.4 mV 00 tuner take over at IF input signal of 80 mV 2004 Oct 04 MODE 17 MODE 0 normal operation 1 primary CVBS anti-alias filters bypass Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 Table 36 Data link modes; note 1 Table 30 Group delay correction GD MODE DM APPLICATION MODE 0 group delay correction bypass 0 Normal 0 1 group delay correction active 1 YUV 2fH 1 Note Table 31 2nd SIF LPF mode SLPM 1. See Table 2 in Chapter “Functional description”. MODE Table 37 Selection of secondary video signal 0 2nd SIF LPF active 1 2nd SIF LPF bypass (for FM radio 10.7 MHz) Table 32 Bypass anti-alias filters of secondary CVBS BPS MODE SELECTED SIGNAL SEC3 SEC2 SEC1 SEC0 0 0 0 0 CVBS_IF 0 0 0 1 CVBS1 CVBS2 0 normal operation 0 0 1 0 1 secondary CVBS anti-alias filters bypass 0 0 1 1 CVBS3 1 0 1 1 Y + C3 0 1 0 0 CVBS4 1 1 0 0 Y + C4 0 1 0 1 CVBS_DTV Table 33 Sound trap frequency ST1 ST0 FREQUENCY 0 0 5.5 MHz 0 1 4.5 MHz 1 0 6.0 MHz 1 1 6.5 MHz other Table 38 Selection of primary video channel PRI2 PRI1 PRI0 0 0 0 0 CVBS_IF normal operation 0 0 0 1 CVBS1 pseudo random test mode; note 1 0 0 1 0 CVBS2 0 0 1 1 CVBS3 1 0 1 1 Y + C3 0 1 0 0 CVBS4 1 1 0 0 Y + C4 1 1 1 0 YC_COMB DRND 1 SELECTED SIGNAL PRI3 Table 34 Data link transmitter test mode 0 CVBS_IF MODE Note 1. The pseudo random mode can be used for in-circuit testing of the data link connections between data link transmitter in the analog front end IC and data link receiver in the digital video processor IC. other Table 35 YUV 2fH clamp pulse timing HDTV CVBS_IF Table 39 Video ident mode MODE 0 normal timing (480p signal) VIM MODE 1 HDTV timing (1080i signal) 0 ident coupled to CVBS_IF 1 ident coupled to selected primary CVBS signal Table 40 IF video mute VSW 2004 Oct 04 18 MODE 0 normal operation 1 CVBSOUTIF muted Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 Table 41 Clamp mode secondary CVBS channel CMS Table 47 Selection of CVBS output B MODE 0 top sync clamping mode 1 black level clamping mode Table 42 Clamp mode primary CVBS channel CMP MODE SELECTED SIGNAL CVB3 CVB2 CVB1 CVB0 0 0 0 0 CVBS_IF 0 0 0 1 CVBS1 0 0 1 0 CVBS2 0 0 1 1 CVBS3 Y + C3 0 top sync clamping mode 1 0 1 1 1 black level clamping mode 0 1 0 0 CVBS4 1 1 0 0 Y + C4 0 1 0 1 CVBS_DTV Table 43 Selection of CVBS output A other SELECTED SIGNAL CVA3 CVA2 CVA1 CVA0 0 0 0 0 CVBS_IF 0 0 0 1 CVBS1 RSEL 0 0 1 0 CVBS2 0 RGB1 input 1 RGB2 input 0 0 1 1 CVBS3 1 0 1 1 Y + C3 0 1 0 0 CVBS4 1 1 0 0 Y + C4 0 1 0 1 other Table 48 Selection of RGB/YUV input MAT DVD CVBS_DTV 0 0 YUV input; note 1 output muted 0 1 YPbPr input; note 2 1 0 RGB input; note 3 1 1 spare MODE 0 normal operation 1 SCART2 audio output muted 1. YUV input is an Y, −(B−Y) and −(R−Y) input with the specification: a) Y = 1.43 V (p-p); U = 1.33 V (p-p); V = 1.05 V (p-p). MODE 0 normal operation 1 SCART1 audio output muted MODE Notes Table 45 Mute SCART1 audio output MA1 SELECTED SIGNAL Table 49 RGB/YUV input mode Table 44 Mute SCART2 audio output MA2 output muted b) These signal amplitudes are based on a colour bar signal with 75 % saturation. 2. YPbPr input with the specification: a) Y = 1.0 V (p-p); Pb = 0.7 V (p-p); Pr = 0.7 V (p-p). Table 46 Mute LINE audio output MA0 b) These signal amplitudes are based on a colour bar signal with 100 % saturation. MODE 0 normal operation 1 LINE audio output muted 3. RGB input with the specification: a) R = 0.7 × VB-W; G = 0.7 × VB-W; B = 0.7 × VB-W. b) These signal amplitudes are based on a colour bar signal with 100 % saturation. 2004 Oct 04 19 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 Table 50 Clamp mode for RGB and YUV signals CMR Table 54 Selection of primary audio channel MODE 0 top sync clamp mode 1 black level clamp mode Table 51 Clamp pulse selection for RGB and YUV signals CLPS MODE PRA2 PRA1 PRA0 SELECTED SIGNAL 0 0 0 AMint (L) and AMext (R); note 1 0 0 1 L1 and R1 0 1 0 L2 and R2 0 1 1 L3 and R3 0 clamp pulse of primary channel 1 0 0 L4 and R4 1 clamp pulse of secondary channel 1 0 1 L5 and R5 1 1 1 AMext (L) and AMint (R); note 1 Table 52 Selection of secondary audio channel Note SEA2 SEA1 SEA0 SELECTED SIGNAL 0 0 0 AMint (L) and AMext (R); note 1 0 0 1 L1 and R1 0 1 0 L2 and R2 0 1 1 L3 and R3 DSG 1 0 0 L4 and R4 0 0 dB; to be used with 5 V audio supply 1 6 dB; to be used with 8 V audio supply 1. Selection between AMint and AMext must be done by digital video processor. Table 55 Gain from DSND inputs to SCART outputs 1 0 1 L5 and R5 1 1 0 MIC1 (L) and MIC2 (R) 1 1 1 AMext (L) and AMint (R); note 1 GAIN Table 56 Selection of SCART1 audio output Note 1. Selection between AMint and AMext must be done by digital video processor. Table 53 Secondary audio channel mode MODE SELECTED SIGNAL AMX A1S2 A1S1 A1S0 0 0 0 0 AMint 0 0 0 1 LR1 0 0 1 0 LR2 0 0 1 1 LR3 0 1 0 0 LR4 MONO MNM1 MNM0 0 − − stereo; see Table 52 0 1 0 1 LR5 1 0 0 mono (L) and AMint (R); note 1 0 1 1 0 DSND1 0 1 1 1 DSND2 1 0 0 0 AMext 1 0 1 mono (L) and AMext (R); note 1 1 1 0 mono (L) and MIC1 (R); note 1 1 1 1 mono (L) and MIC2 (R); note 1 Note 1. Mono is (L + R)/2; when AM is selected in Table 52, mono is AMint for SEA[2:0] = 000 and AMext for SEA[2:0] = 111. A more comprehensive table can be found in the application note. 2004 Oct 04 20 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 Table 57 Selection of LINE audio output Table 61 Selection of SCART2 audio output SELECTED SIGNAL SELECTED SIGNAL AMX A2S2 A2S1 A2S0 AMint 0 0 0 0 AMint 1 LR1 0 0 0 1 LR1 1 0 LR2 0 0 1 0 LR2 1 1 LR3 0 0 1 1 LR3 1 0 0 LR4 0 1 0 0 LR4 0 1 0 1 LR5 0 1 0 1 LR5 0 1 1 0 DSND1 0 1 1 0 DSND1 0 1 1 1 DSND2 0 1 1 1 DSND2 1 0 0 0 AMext 1 0 0 0 AMext. AMX A0S2 A0S1 A0S0 0 0 0 0 0 0 0 0 0 0 0 0 Table 58 Microphone input 2 gain M2G Table 62 IRQ mask bits for status byte 0 IRQ OUTPUT(1) IM6 TO IM0 GAIN 0 low 0 IRQ output not activated 1 high 1 IRQ output is activated when the corresponding status bit changes value Table 59 Microphone input 1 gain M1G GAIN 0 low 1 high Note 1. The IRQ output is always activated if status bit POR = 1. Table 60 Microphone amplifiers on/off MICON 8.2 MODE 0 microphone amplifiers not active 1 normal operation Output status registers Table 63 Output status registers; subaddresses must not be sent, they are automatically incremented DATA BYTE SUB ADDR D7 Status byte 0 00 POR Status byte 1 01 0 0 0 Reserved 02 0 0 Status byte 3 03 ID7 ID6 FUNCTION 2004 Oct 04 D6 D5 D4 D3 ROK 0 0 ID5 MSUP ASUP 21 D2 D1 D0 LOCK VID AFA AFB 0 DCF 0 AGC 0 0 0 0 0 ID4 ID3 ID2 ID1 ID0 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 Table 64 Power-on-reset POR Table 70 AFC output CONDITION AFA AFB CONDITION 0 normal 0 0 outside window; too low 1 Power-down 0 1 outside window; too high 1 0 in window; below reference 1 1 in window; above reference Table 65 Main supply MSUP CONDITION 0 main supply not OK 1 main supply OK Table 71 Data link current test DCF Table 66 Audio supply ASUP audio supply not OK 1 audio supply OK data link current test OK 1 data link current test FAIL Table 72 Tuner AGC output AGC Table 67 Reference frequency ROK INDICATION 0 tuner gain reduction active 1 no gain reduction of tuner CONDITION 0 reference frequency not present 1 reference frequency present Table 73 Mask version indication ID7 ID6 ID5 ID4 ID3 0 0 0 0 0 N1A or N1B version 0 0 0 0 1 − 0 0 0 1 0 N1C version IF PLL not locked 0 0 0 1 1 N1D version IF PLL locked 0 0 1 0 0 N1E or N1F version 0 0 1 0 1 N2B version 0 0 1 1 0 N3B version Table 68 IF PLL lock indication LOCK 1 0 CONDITION 0 0 INDICATION INDICATION Table 69 Video identification VID INDICATION 0 no video signal detected 1 video signal detected 2004 Oct 04 22 MASK VERSION Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP main supply voltage − 6.0 V VCC(1ASW), VCC(2ASW) audio supply voltage − 9.0 V Tstg storage temperature −25 +150 °C Tamb ambient temperature 0 70 °C Tsol soldering temperature − 260 °C Tj operating junction temperature − 150 °C Vesd electrostatic discharge voltage pin SDA − ±1500 V all other pins − ±2000 V for 5 s Human Body Model; C = 100 pF; R = 1.5 kΩ Machine Model; C = 200 pF; R = 0 kΩ − pin SDA − ±150 V all other pins − ±200 V 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient in free air; note 1 VALUE UNIT 30 K/W Note 1. The value given for the thermal resistance from junction to ambient should only be considered as an indication. Most of the dissipated heat is conveyed to the ambient air through the Printed-Circuit Board (PCB) on which the IC is mounted. The actual value of the thermal resistance depends on the number of metal layers, size and layout of the PCB, and also on the dissipation of other components on the PCB. 11 QUALITY SPECIFICATION In accordance with document “SNW-FQ-611”. 11.1 Latch-up performance At Tamb = 70 °C all pins meet the following specification: • Positive stress test: Itrigger ≥ 100 mA or Vtrigger ≥ 1.5 VP(max) • Negative stress test: Itrigger ≤ −100 mA or Vtrigger ≤ −0.5 VP(max). 2004 Oct 04 23 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 12 CHARACTERISTICS VCC = 5 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies POWER SUPPLIES VP main supply voltage 4.75 5.0 5.25 V IP main supply current − 285 320 mA VCC(1ASW), VCC(2ASW) audio supply voltage note 1 4.75 8.0 8.4 V note 1 ICC(ASW) audio supply current − 3.5 5.0 mA VCC(SUP) minimum required voltage to set status bit MSUP − 4.0 − V VCC(ASW1) minimum required voltage to set status bit ASUP − 4.0 − V Ptot total power dissipation − 1.45 1.70 W REFERENCE VOLTAGES VBGDEC bandgap decoupling voltage on pin BGDEC 2.20 2.30 2.40 V VRREF voltage on pin RREF 2.19 2.30 2.41 V VVD2V5 digital supply decoupling voltage at pin VD2V5 2.35 2.50 2.65 V VPOR Power-On Reset (POR) level on pin VD2V5 1.8 2.0 2.2 V 1.25 − 3.30 V 1.24 1.27 1.31 V fi = 38.9 MHZ − 75 150 µV fi = 45.75 MHz − 75 150 µV fi = 58.75 MHz − 75 150 µV VOLTAGE REGULATORS VAUDO, VDEFLO output voltage range VAUDS, VDEFLS voltage at feedback pin note 2 Video IF circuit VIDEO IF AMPLIFIER INPUTS Vi(dif)(rms) input sensitivity (differential; RMS value) AGC set Ri(dif) input resistance (differential) note 3 − 2 − kΩ Ci(dif) input capacitance (differential) note 3 − 3 − pF ∆Gv gain control range 64 − − dB 150 − − mV Vi(max)(dif)(rms) maximum input signal (differential; RMS value) 2004 Oct 04 24 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER PNX3000 CONDITIONS MIN. TYP. MAX. UNIT PLL DEMODULATOR; NOTES 4 AND 5 ∆fVCO free-running frequency offset of VCO PLL not locked; deviation from nominal setting −500 − 0 kHz fcr(PLL) catching range PLL without SAW filter; referred to selected IF system frequency ±1 − − MHz td(ident) delay time of identification bit LOCK = 1 − − 20 ms VIDEO AMPLIFIER OUTPUT: PIN CVBSOUTIF; NOTE 6 Vo(z) zero signal output level negative modulation; note 7 − 3.5 − V positive modulation; note 7 − 1.1 − V Vo(ts) top sync level negative modulation 1.3 1.4 1.5 V Vo(w) white level positive modulation − 3.4 − V Vo(dem)(p-p) demodulated CVBS output recommended settings for bits signal (peak-to-peak value) VA1 and VA0; note 8 1.8 2.0 2.2 V ∆Vo difference in amplitude between negative and positive modulation − 0 15 % Zo(v) video output impedance − 150 250 Ω Ibias(int) internal bias current of NPN emitter follower output transistor − 0.9 − mA Isource(max) maximum source current − − 1 mA Bv(−3dB) bandwidth of demodulated video output signal at −3 dB; before sound trap 6 9 − MHz Gdif differential gain recommended settings for bits VA1 and VA0; note 8 negative modulation; note 9 − 2 5 % positive modulation; note 9 − 3 5 % deg ϕdif differential phase notes 9 and 10 − − 5 NLvid video non-linearity note 11 − − 5 % Vclamp white spot clamp level − 3.8 − V Nclamp noise inverter clamping level note 12 − 0.9 − V Nins noise inverter insertion level note 12 − 2.3 − V dblue intermodulation at ‘blue’ notes 10 and 13 Vo at 0.92 MHz or 1.1 MHz 60 66 − dB Vo at 2.66 MHz or 3.3 MHz 60 66 − dB 56 62 − dB dB dyellow intermodulation at ‘yellow’ notes 10 and 13 Vo at 0.92 MHz or 1.1 MHz 60 66 − − − − weighted 56 60 − dB unweighted 49 53 − dB − 5.5 − mV Vo at 2.66 MHz or 3.3 MHz S/N ∆Vrc 2004 Oct 04 signal-to-noise ratio residual carrier signal notes 10 and 14 note 10 25 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL ∆Vrc(2H) PARAMETER residual 2nd harmonic of carrier signal PNX3000 CONDITIONS MIN. TYP. MAX. UNIT note 10 − 2.5 − mV IF AND TUNER AGC; NOTE 15 Timing of IF AGC MVI modulated video interference 30 % AM for 1 V to 100 mV; 0 Hz to 200 Hz (B/G standard) − − 10 % tres response time IF input signal amplitude increase of 52 dB; positive and negative modulation; IF AGC time constant set to normal − 2 − ms negative modulation − 50 − ms positive modulation − 100 − ms − 0.4 0.8 mV 100 150 − mV IF input signal amplitude decrease of 52 dB Tuner take over adjustment (via I2C-bus) Vstart(min)(rms) minimum starting level for tuner take over (RMS value) Vstart(max)(rms) maximum starting level for tuner take over (RMS value) Tuner control output Vo(max) maximum tuner AGC output voltage maximum tuner gain; note 3 − − 5 V minimum tuner gain; Io = 1 mA Vo(sat) output saturation voltage − − 300 mV Io(TUNERAGC) tuner AGC output current range 0 − 1 mA IL leakage current RF AGC − − 1 µA ∆Vi input signal variation for complete tuner control 0.5 2 4 dB AFC OUTPUT (VIA I2C-BUS); NOTE 16 fAFC AFC resolution − 2 − bits ∆fw window sensitivity − 125 − kHz ∆flw window sensitivity in large window mode − 275 − kHz 75 150 µV 2 − kΩ DTV IF circuit DTV IF AMPLIFIER INPUT Vi(dif)(rms) input sensitivity (differential; RMS value) fi between 30 MHz and 60 MHz − Ri(dif) input resistance (differential) note 3 2004 Oct 04 − 26 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER Ci(dif) input capacitance (differential) ∆Gv gain control range PNX3000 CONDITIONS note 3 Vi(max)(dif)(rms) maximum input signal (differential; RMS value) MIN. TYP. MAX. UNIT − 3 − pF 64 − − dB 150 − − mV DTV IF MIXER fosc oscillator frequency step size 250 kHz 24 − 64 MHz Nϕ(osc) oscillator phase noise carrier to noise ratio in dBc/Hz − −92 − dB PBll lower limit pass-band − − 1.0 MHz PBul upper limit pass-band 10.0 − − MHz PBR pass-band ripple − − 0.5 dB Bsb stop band − 44 − MHz αsb stop band attenuation 40 − − dB EXTERNAL AGC CONTROL ∆Vi voltage range for full control of the amplifier 1 − 3 V Zi input impedance 1 − − MΩ DTV 1st IF mode; f = 40 MHz − 0.68 − V DTV 2nd IF mode; f = 4 MHz − 1.20 − V DTV 1st IF mode; f = 40 MHz − 0.95 − V DTV 2nd IF mode; f = 4 MHz − 1.68 − V − 150 − Ω DTV 1st IF mode − 1.15 − V DTV 2nd IF mode − 3.0 − V DTV OUTPUT (DOWN-MIXED OUTPUT SIGNAL) Vo(dif)(p-p) differential output signal (peak-to-peak value) Vo(dif)(p-p)(max) maximum allowed differential output signal (peak-to-peak value) Zo(dif) output impedance (differential) VO DC output level internal AGC mode; no modulation external AGC mode; note 17 Ibias(int) internal bias current of emitter followers − 2 − mA Isource(max) maximum allowed source current − − 2 mA − 45 tbf dBµV tbf 100 − dBµV − 2 − kΩ Sound IF circuit SOUND IF AMPLIFIER Vi(rms) input sensitivity (RMS value) Vi(max)(rms) maximum input signal (RMS value) Ri(dif) input resistance (differential) 2004 Oct 04 −3 dB note 3 27 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER PNX3000 CONDITIONS MIN. TYP. MAX. UNIT − 3 − pF gain control range − 55 − dB crosstalk attenuation between SIF and VIF input 50 − − dB 75 100 125 mV Ci(dif) input capacitance (differential) ∆Gv αct(SIF-VIF) note 3 SOUND IF INTERCARRIER OUTPUT ON DTV OUTPUT, FM MODULATION; NOTE 18 Vo(dif)(rms) differential output signal amplitude (RMS value) SC1; sound carrier 2 off B−3dB bandwidth (−3 dB) 7.5 8.5 − MHz ∆Vr(SC)(rms) residual IF sound carrier (RMS value) − 2 − mV Zo(dif) output impedance (differential) − 150 − Ω VO DC output voltage − 1.3 − V Ibias(int) internal bias current of emitter followers − 2 − mA Isource(max) maximum allowed source current − 2 − mA S/NW weighted S/N ratio (SC1/SC2) black picture 53/48 58/55 − dB white picture 52/47 55/53 − dB 6 kHz sinewave (black-to-white modulation) 44/42 48/46 − dB 250 kHz sine wave (black-to-white modulation) 44/25 48/30 − dB sound carrier subharmonics (f = 2.75 MHz ± 3 kHz) 45/44 51/50 − dB sound carrier subharmonics (f = 2.87 MHz ± 3 kHz) 46/45 52/51 − dB 600 mV ratio of PC/SC1 at vision IF input of 40 dB or higher; note 19 AM SOUND OUTPUT; NOTE 20 Vo(rms) AF output signal amplitude 54 % modulation (RMS value) 400 500 THD total harmonic distortion 54 % modulation − 0.5 1.0 % 80 % modulation − tbf 5.0 % 100 125 − kHz B−3dB −3 dB AF bandwidth S/NW weighted signal-to-noise ratio 54 % modulation 47 53 − dB PSRR power supply ripple rejection ratio 5 V main supply − 17 − dB 2004 Oct 04 28 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER PNX3000 CONDITIONS MIN. TYP. MAX. UNIT 2nd sound IF AGC circuit 2ND SOUND IF EXTERNAL INPUT ∆Vi(rms) input voltage range (RMS value) ∆fi input frequency range Ri input resistance Ci input capacitance 18 − 320 note 21 4 − 10.7 MHz note 3 − 25 − kΩ note 3 − 3 − pF − 25 − dB − − 12.5 µA mV 2ND SOUND IF AGC ∆G gain control range Ich(AGC) charge current AGC pin AM mode − − 2.5 µA Idch(AGC) discharge current AGC pin FM mode − − 50 µA AM mode − − 2.5 µA overload − 1 − mA FM mode − 716 − AM mode; no modulation − 358 − fSC1 = 4.5 MHz 3.90 4.00 − MHz fSC1 = 5.5 MHz 4.80 4.90 − MHz fSC1 = 6.0 MHz 5.25 5.35 − MHz fSC1 = 6.5 MHz 5.70 5.80 − MHz − 1.0 2.0 dB FM mode DIGITAL OUTPUT nd(p-p) decimal digital output level (peak-to-peak value) Sound trap and group delay correction filter SOUND TRAP Bv(−3dB) −3 dB video bandwidth (sound trap + group delay) ∆Vchrom(p) peaking at chroma subcarrier frequency αSC1 attenuation at first sound carrier fSC1 all trap frequencies 28 33 − dB αSC2 attenuation at second sound carrier fSC2 f = 4.726 MHz; fSC1 = 4.5 MHz 21 27 − dB f = 5.742 MHz; fSC1 = 5.5 MHz 21 27 − dB f = 6.55 MHz; fSC1 = 6.0 MHz 12 18 − dB f = 6.742 MHz; fSC1 = 6.5 MHz 18 24 − dB f = 4.43 MHz; sound trap frequency 5.5 MHz; sound trap only − 180 − ns f = 4.43 MHz; sound trap frequency 5.5 MHz; sound trap plus group delay correction filter − 170 − ns GROUP DELAY CORRECTION; FIGURES 6 AND 7; NOTE 22 td(g) 2004 Oct 04 group delay 29 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER PNX3000 CONDITIONS MIN. TYP. MAX. UNIT Video switches CVBS AND YC SWITCHES Vi(CVBS/Y)(p-p) CVBS or Y input voltage (peak-to-peak value) Vi(CVBS/Y)(clip) CVBS or Y clipping level Ii(CVBS/Y) CVBS or Y input current − 1.0 1.76 V black-to-peak video − 1.33 − V outside clamp pulse − 0 − µA during clamp pulse −10 − +10 µA αsup(CVBSn) suppression of non-selected CVBS input signal note 10 50 − − dB Vi(C)(p-p) chrominance input voltage (peak-to-peak value) 100 % colour bar; note 3 − 885 1264 mV Zi(C) chrominance input impedance − 50 − kΩ 70 100 140 mV − 10 ms VIDEO IDENT FUNCTION Vsync(min) minimum sync pulse amplitude td(ident) delay time of identification I2C-bus status bit VID = 1; after − the Video IF AGC has stabilized on a new transmitter ANALOG CVBS OUTPUTS: PINS CVBSOUTA AND CVBSOUTB Zo output impedance − − 250 Ω Vo(p-p) output signal amplitude (peak-to-peak value) at input signal of 1.0 V (p-p) − 2.0 − V VO DC output level top sync − 0.4 − V output muted − 0.5 − V DIGITAL OUTPUTS CVBS/Y signal nd(black) decimal digital output level for black black clamp mode − 240 − nd(white) decimal digital output level for white nominal input signal − 652 − 480 512 544 − 520 − C signal nd(black) decimal digital output level for black nd(p-p) decimal digital output amplitude (peak-to-peak value) 2004 Oct 04 nominal input level; 100 % colour bar 30 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER PNX3000 CONDITIONS MIN. TYP. MAX. UNIT RGB, YPbPr and YUV inputs ANALOG INPUTS General Ii input current outside clamp pulse − 0 − µA during clamp pulse −10 − +10 µA − 0.7 1.0 V RGB mode Vi(b-w) input signal amplitude (black-to-white value) YPbPr mode Vi(Y)(p-p) Y input signal amplitude (peak-to-peak value) top sync-to-white − 1.0 1.43 V Vi(Pb)(p-p) Pb input signal amplitude (peak-to-peak value) 100 % colour bar − 0.7 1.0 V Vi(Pr)(p-p) Pr input signal amplitude (peak-to-peak value) 100 % colour bar − 0.7 1.0 V Vi(Y) Y input signal amplitude top sync-to-white − 1.43 2.04 V Vi(U)(p-p) U input signal amplitude (peak-to-peak value) 100 % colour bar − 1.77 2.53 V Vi(V)(p-p) V input signal amplitude (peak-to-peak value) 100 % colour bar − 1.40 2.00 V delay difference for the three channels note 10 − 0 20 ns nd(black) decimal digital output level for black black clamp mode − 240 − nd(white) decimal digital output level for white nominal input level − 788 − YUV mode DIGITAL OUTPUTS General ∆td Y signal U and V signals; note 23 nd(black) decimal digital output level for black black clamp mode − 512 − nd(p-p) decimal digital output amplitude (peak-to-peak value) nominal input level; 100 % colour bar − 716 − − 8.0 − Video anti-alias filters CVBS, YYC, C AND 2ND SIF FILTERS fpb(−1dB) 2004 Oct 04 −1.0 dB pass-band frequency 31 MHz Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER PNX3000 CONDITIONS MIN. TYP. MAX. UNIT fpb(−3dB) −3.0 dB pass-band frequency − 9.0 − MHz fsb(−35dB) −35 dB stop band frequency − 20 − MHz td(g) group delay at 1.0 MHz − 36 − ns at 5.0 MHz − 42 − ns E∆G differential gain error note 9 − 2 5 % E∆ϕ differential phase error notes 9 and 10 − − 5 deg S/N signal-to-noise ratio B = 5 MHz; note 24 60 − − dB −1.0 dB pass-band frequency 1fH mode − 8.0 − MHz 2fH mode − 16 − MHz −3.0 dB pass-band frequency 1fH mode − 9.0 − MHz 2fH mode − 18 − MHz fsb(−35dB) −35 dB stop band frequency 1fH mode − 20 − MHz 2fH mode − 40 − MHz td(g) group delay at 1 MHz; 1fH mode − 36 − ns at 1 MHz; 2fH mode − 18 − ns at 5 MHz; 1fH mode − 42 − ns at 10 MHz; 2fH mode − 21 − ns − − dB YYUV FILTERS fpb(−1dB) fpb(−3dB) S/N signal-to-noise ratio 1fH mode: B = 5 MHz 60 2fH mode: B = 10 MHz; note 24 U AND V FILTERS −1.0 dB pass-band frequency 1fH mode − 4.0 − MHz 2fH mode − 8.0 − MHz −3.0 dB pass-band frequency 1fH mode − 4.5 − MHz 2fH mode − 9.0 − MHz fsb(−35dB) −35 dB stop band frequency 1fH mode − 10 − MHz 2fH mode − 20 − MHz td(g) group delay at 1 MHz; 1fH mode − 72 − ns at 1 MHz; 2fH mode − 36 − ns at 2.5 MHz; 1fH mode − 84 − ns at 5 MHz; 2fH mode − 42 − ns − − dB fpb(−1dB) fpb(−3dB) S/N signal-to-noise ratio 1fH mode: B = 5 MHz 60 2fH mode: B = 10 MHz; note 24 FILTER FOR DTV 2ND IF SIGNAL fpb(−1dB) −1.0 dB pass-band frequency − 10 − MHz fpb(−3dB) −3.0 dB pass-band frequency − 12 − MHz 2004 Oct 04 32 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER PNX3000 CONDITIONS MIN. TYP. MAX. UNIT fsb(−35dB) −35 dB stop band frequency − 44 − MHz td(g) group delay − 22 − ns − 32 − ns B = 10 MHz; note 25 60 − − dB S/N signal-to-noise ratio Video analog-to-digital converters GENERAL; NOTE 26 Bv(−3dB) −3 dB signal bandwidth 1fH mode − 9 − MHz fsample sample frequency 1fH mode − 27 − MHz RES resolution − 10 − bit STATIC MEASUREMENTS DNL differential non-linearity fclk = 54 MHz; fsignal = 10 MHz − 0.7 − LSB INL integral non-linearity fclk = 54 MHz; fsignal = 10 MHz − 1 − LSB fclk = 27 MHz; fsignal = 5 MHz − −63 − dB fclk = 54 MHz; fsignal = 10 MHz − −63 − dB DYNAMIC MEASUREMENTS THD S/N ENOB total harmonic distortion signal-to-noise ratio effective number of bits fclk = 27 MHz; B = 5 MHz − 58 − dB fclk = 54 MHz; B = 10 MHz − 58 − dB fclk = 54 MHz; fsignal = 10 MHz − 9.0 − bits 5 V audio supply 1.0 − − V 8 V audio supply 2.0 − − V 24 32 − kΩ Audio selectors LR INPUTS Vi(max)(rms) maximum input voltage (RMS value) Ri input resistance G gain from LR inputs to analog outputs outputs unloaded −0.4 0 +0.3 dB α(LRn) crosstalk attenuation from non-selected inputs f = 10 kHz 70 80 − dB DSND INPUTS FOR AUDIO SIGNALS COMING FROM DIGITAL VIDEO PROCESSOR Vi(max)(rms) maximum input signal amplitude (RMS value) 1.0 − − V Ri input resistance 24 32 − kΩ G gain from DSND inputs to analog outputs 5 V audio supply; DSG = 0; outputs unloaded −0.4 0 +0.3 dB 8 V audio supply; DSG = 1; outputs unloaded 5.6 6.0 6.3 dB 70 80 − dB − 20 − kΩ α(DSNDn) crosstalk attenuation from non-selected inputs MICROPHONE AMPLIFIERS; NOTE 27 Ri 2004 Oct 04 input resistance 33 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER PNX3000 CONDITIONS MIN. Glow low gain bits M1G = M2G = 0 − Ghigh high gain bits M1G = M2G = 1 − ∆f frequency range 50 THD + N total harmonic distortion plus noise 1 kHz input signal at 0.9 V (RMS) output level −74 S/N signal-to-noise ratio referred to 16 mV (RMS) input level; low gain TYP. MAX. UNIT − dB 35 − dB − 20000 Hz −80 − dB 70 76 − dB referred to 16 mV (RMS) input level; high gain 74 80 − dB 5 V audio supply 1.0 − − V 8 V audio supply 2.0 − − V − 500 650 Ω +6 dBV output level −80 −88 − dB −54 dBV output level; A-weighted −36 −40 − dB 90 96 − dB 20 − 20000 Hz ripple on 5 V main supply − 43 − dB ripple on 8 V audio supply − 45 − dB 17 ANALOG OUTPUTS Vo(max)(rms) maximum output signal amplitude (RMS value) Zo output impedance THD + N total harmonic distortion plus noise S/N signal-to-noise ratio ∆f frequency range PSRR power supply ripple rejection ratio 1 kHz input signal referred to 0 dBV output level; A-weighted 1 kHz ripple frequency Audio analog-to-digital converters DIGITAL AUDIO OUTPUTS; NOTE 28 Vi(max)(rms) maximum input voltage (RMS value) 5 V audio supply 1.0 − − V 8 V audio supply 2.0 − − V THD + N total harmonic distortion plus noise 1 kHz input signal +0 dBV output level − −78 − dB −54 dBV output level; A-weighted − −30 − dB S/N signal-to-noise ratio referred to 0 dBV input level; A-weighted − 86 − dB αcs channel separation 0 kHz to 20 kHz − 80 − dB − −4.3 − dBFS ripple on 5 V main supply − 54 − dB ripple on 8 V audio supply − 55 − dB 5 V audio supply voltage; 1 kHz − ripple frequency 18 − dB Vo digital output level at 2 V (RMS) input level PSRR power supply ripple rejection ratio 8 V audio supply voltage; 1 kHz ripple frequency 2004 Oct 04 34 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER PNX3000 CONDITIONS MIN. TYP. MAX. UNIT Timing circuit HV INPUT SIGNALS: PINS HV_PRIM AND HV_SEC; NOTES 29 AND 30 Timing specification for HV pulses coming from digital video processor; see Fig.8 t(HV-sync) tW(HV) time between start HV pulse and start of horizontal sync pulse on CVBS/Y signal 1fH TV mode − 0.6 − µs 2fH mode; HDTV = 0 − 0.3 − µs 2fH mode; HDTV = 1 − 0.3 − µs width of HV pulses 1fH TV mode normal lines − 72 − ck clamp disable lines − 128 − ck vsync lines − 288 − ck normal lines − 36 − ck clamp disable lines − 64 − ck vsync lines − 144 − ck normal lines − 20 − ck clamp disable lines − 44 − ck vsync lines − 144 − ck 1fH TV mode − 80 − ck 2fH mode; HDTV = 0 − 40 − ck 2fH mode; HDTV = 1 − 24 − ck 1fH TV mode − 255 − ck 2fH mode; HDTV = 0 − 136 − ck 2fH mode; HDTV = 1 − 136 − ck delay between start of HV pulse and start of clamp pulse 1fH TV mode − 80 − ck 2fH mode; HDTV = 0 − 40 − ck 2fH mode; HDTV = 1 − 24 − ck width of clamp pulse 1fH TV mode − 44 − ck 2fH mode; HDTV = 0 − 22 − ck 2fH mode; HDTV = 1 − 17 − ck 2fH mode HDTV = 0 2fH mode; HDTV = 1 Detection of clamp disable lines tdet(clamp)(dis) clamp disable detection Detection of vsync lines tdet(vsync) vsync detection Internal clamp pulses td(HV-clamp) tW(clamp) CRYSTAL REFERENCE FREQUENCY INPUT: PIN XREF Ri input resistance 25 35 45 kΩ Ci input capacitance − 3 − pF Vi(p-p) input signal amplitude (peak-to-peak value) 1 − 3.5 V 2004 Oct 04 35 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER PNX3000 CONDITIONS MIN. TYP. MAX. UNIT Data link transmitters GENERAL fword(CLK) word clock frequency − 13.5 − MHz WL word length − 44 − bits fD data rate − 594 − Mbit/s fbit(CLK) bit clock frequency − 297 − MHz individual data and strobe signals OUTPUT DRIVERS FOR DATA AND STROBE SIGNALS ∆Vo voltage swing (peak-to-peak value) individual pins; output loaded with 100 Ω − 0.3 − V Vo(dif)(p-p) differential output voltage (peak-to-peak value) output loaded with 100 Ω − 0.6 − V Ro output resistance − − 50 Ω RL load resistance − 100 − Ω connected between positive terminal and negative terminal East-west drive circuit: pins EWVIN, EWIOUT and REW Ri input resistance − 40 − kΩ ∆Vi input voltage range 0 − 3.5 V Rew external conversion resistor note 31 − 750 − Ω ∆Vo output voltage range note 31 1.0 − Vcc V ∆Io output current range 0 − 1.2 mA V I2C-bus control inputs and outputs SDA/SCL INPUTS AND OUTPUT; NOTE 32 Vi input voltage level 0 − 5.5 VIL LOW-level input voltage − − 0.2 × VCC V VIH HIGH-level input voltage 0.5 × VCC − − V IIL LOW-level input current Vi = 0 V − 0 − µA IIH HIGH-level input current Vi = 5.5 V − 0 − µA VOL LOW-level output voltage SDA pin; IL = 3 mA − − 0.4 V Ci input capacitance − 5 10 pF IRQ OUTPUT; NOTE 33 VOL LOW-level output voltage IRQ pin; IL = 1.5 mA − − 0.4 V VOH HIGH-level output voltage open drain − − 5.5 V Notes 1. The supply voltage for the analog audio part may have a value between 5 V and 8 V. For a supply voltage of 5 V the maximum amplitude of in- and output signals is 1 V (RMS). For a supply voltage of 8 V the maximum amplitude of in- and output signals is 2 V (RMS). 2. The value of the regulated voltage is determined by the external resistive voltage divider. The voltage range mentioned relates to the voltage at the emitter of the external transistor. The stability of the voltage regulator loop 2004 Oct 04 36 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 depends on the value of the decoupling capacitor Cdec on the emitter of the external transistor. Recommended value Io is C dec = 1.5 × ------ µF, with Io in mA. Vo 3. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 4. Loop bandwidth BL = 60 kHz (natural fN = 15 kHz; damping factor d = 2; calculated with top sync level as IF PLL input signal level). 5. The IF PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a digital control circuit which uses the clock frequency of the microcontroller/teletext decoder as a reference. The required IF frequency for the various standards is set via the I2C-bus. When the system is locked the resulting IF frequency is very accurate with a deviation from the nominal value of less than 25 kHz. 6. Measured at pin CVBSOUTIF with 10 mV (RMS) top sync input signal at VIF input. 7. So called projected zero point, i.e. with switched demodulator. 8. The signal amplitude at the CVBSOUTIF output depends on the setting of bits VA1 and VA0. The recommended settings for negative modulation (bit PMOD = 0) is VA1 = VA0 = 1. For positive modulation (bit PMOD = 1) the settings VA1 = 1 and VA0 = 0 is recommended. The Vo(dem)(p-p) and ∆Vo values specified are valid if the recommended settings are used. 9. Measured in accordance with the test line given in Fig.3. For the differential phase test the peak white setting is reduced to 87 %: a) The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. b) The phase difference is defined as the difference in degrees between the largest and smallest phase angle. 10. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 11. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.4. 12. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal). 13. The test set-up and input conditions are given in Fig.5. Measurement is done with an input signal of 10 mV (RMS). 14. Measured at an input signal of 10 mV (RMS). The S/N is the ratio of black-to-white amplitude to the black level noise voltage (RMS value); B = 5 MHz. Weighted in accordance with CCIR 567. 15. The time-constant of the IF AGC is internal and the speed of the AGC can be set via bus bits AGC1 and AGC0. The AGC response time is also dependent on the acquisition time of the PLL demodulator. The values given are valid for the ‘norm’ setting (AGC1 = 0 and AGC0 = 1) and when the PLL is in lock. 16. The AFC control voltage is generated by the digital tuning system of the PLL demodulator. This system uses the external crystal frequency as a reference and is therefore very accurate. For this reason no maximum and minimum values are given for the window sensitivity figures. The tuning information is supplied to the tuning system via the I2C-bus. Two bits are reserved for this function. The AFC value is valid only when bit LOCK = 1. 17. Exceeding this amplitude leads to intermodulation distortion. 18. The intercarrier sound (2nd SIF) signal is not normally an analog output signal of the IC. It can be made available on the DTV output pins by setting bus bits DSIF = 1 and DFIF = 0. 19. The weighted S/N ratio is measured under the following conditions: a) The vision IF modulator incidental phase modulation for black-to-white jumps must be less than 0.5 degrees b) QSS AF performance of the vision IF modulator, measured with the television demodulator AMF2 (audio output and weighted S/N ratio) better than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation c) Picture-to-sound carrier ratio of the vision IF modulator: PC/SC1 = 13 dB (transmitter) 2004 Oct 04 37 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 d) The measurements must be carried out with the Siemens SAW filters G3962 for vision IF and G9350 for sound IF. Input level for sound IF 10 mV (RMS) with 27 kHz deviation e) The PC/SC ratio at the vision IF input is calculated as the addition of the TV transmitter ratio and the SAW filter PC/SC ratio. This PC/SC ratio is necessary to achieve the S/NW values as indicated. 20. The demodulated AM sound signal can be made available in the analog domain on LINE or SCART audio outputs by selecting AM internal (bus bit AMX = 0). 21. The frequency range of the 2nd SIF channel is limited by the 2nd SIF anti-alias filter. If a 10.7 MHz FM radio IF signal is supplied to the external 2nd SIF input; an external 10.7 MHz bandpass filter must be used; and the internal anti-alias filter must be bypassed by setting bus bit SLPM = 1. 22. The cascade of sound trap and group delay correction filter compensates for the group delay pre-distortion of the BG standard, curve A (see “Rec. ITU-R BT.470-4”). The indicated values are the difference between the group delay at 4.43 MHz and the group delay at 10 kHz. 23. The digitized U and V signals have the following polarity: U = +(B−Y) and V = +(R−Y). 24. The S/N ratio is defined as the ratio of the full scale black-to-white amplitude to the black level noise voltage (RMS value). 25. The S/N ratio is defined as the ratio of the full scale peak-to-peak signal amplitude to the zero signal noise voltage (RMS value). 26. The video ADC is specified as a stand-alone circuit. Distortion and noise of the video switch and anti-alias filters is not included. 27. The gain of the microphone amplifiers can be switched between low (17 dB) and high (35 dB). The low gain can be used for microphones with a sensitivity between 5 mV (RMS) and 40 mV (RMS) at 94 dB SPL. The high gain can be used for microphones with a sensitivity of less than 5 mV (RMS) at 94 dB SPL. 28. If the audio supply voltage is 8 V; the 5 V full scale reference voltage for the audio A to D converters at pin 91 (VAADCP) is generated by the IC itself, using the internal bandgap reference. This gives the best power supply rejection ratio for the digital audio outputs. If the audio supply voltage is 5 V; pin 91 must be connected to the external 5 V supply. This results in a reduced power supply rejection ratio for the digital audio outputs. 29. Signals HV_PRIM and HV_SEC must be generated by the digital video processor using a 13.5 MHz clock. Where pulse widths are specified in clock pulses, a 13.5 MHz clock is assumed (1 clock pulse is 74.1 ns). To enable detection of the vertical blanking interval, a larger pulse width is used for a number of lines during the vertical blanking period; see Figs 9 and 10. 30. Most timing parameters in this section are expressed in number of clock cycles, abbreviated as ck. 31. The east-west drive circuit is a voltage to current converter circuit, that requires an external conversion resistor. The open drain output transistor can only sink current. The relation between input voltage and output current is as follows: Vi I o = ------------------- where Rew is the external conversion resistor. The voltage across the external conversion resistor is 4 × R ew equal to Vi/4. The voltage at output pin EWIOUT must not be lower than Vi/4 + 0.25 V. The output current must not be larger than 1.2 mA. 32. The switching levels of pins SDA and SCL are compatible with an external signal amplitude of 3.3 V and 5 V. 33. The IRQ output is an open-drain output; active LOW. The pin IRQ must be loaded with a pull-up resistor. 2004 Oct 04 38 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 MBC212 100% 92% 16 % 30% for negative modulation 100% = 10% rest carrier Fig.3 Video output signal. MBC211 handbook, full pagewidth 100 (%) 86 72 58 44 30 10 12 22 26 32 36 40 44 48 Fig.4 Test signal waveform. 2004 Oct 04 39 52 56 60 64 time (µs) Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 −3.2 dB handbook, full pagewidth −10 dB −13.2 dB −13.2 dB −30 dB −30 dB SC CC PC SC CC PC MBC213 BLUE YELLOW PC SC Σ ATTENUATOR TEST CIRCUIT SPECTRUM ANALYZER gain setting adjusted for blue CC MCE436 Input signal conditions: SC = sound carrier; CC = colour carrier; PC = picture carrier. All amplitudes with respect to top sync level. V O at 3.58 MHz or 4.4 MHz Value at 0.9 MHz or 1.1 MHz = 20 log -------------------------------------------------------------------------- + 3.6 dB V O at 0.92 MHz or 1.1 MHz V O at 3.58 MHz or 4.4 MHz Value at 2.66 MHz or 3.3 MHz = 20 log -------------------------------------------------------------------------V O at 2.66 MHz or 3.3 MHz Fig.5 Test set-up intermodulation. 2004 Oct 04 40 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 MCE431 225 handbook, full pagewidth td(g) (ns) 175 125 75 25 −25 0 1 2 3 4 f (MHz) 5 Fig.6 Group delay characteristic without group delay correction (sound trap: 5.5 MHz). MCE432 400 handbook, full pagewidth td(g) (ns) 300 200 100 0 −100 0 1 2 3 4 f (MHz) Fig.7 Group delay characteristic with group delay correction (sound trap: 5.5 MHz). 2004 Oct 04 41 5 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 handbook, halfpage CVBS_in handbook, halfpage normal lines 0.6 µs clamp disable lines HV pulse clamp disable detection 5.33 µs (72 ck) HGATE Vsync lines 5.92 µs (80 ck) vert. sync detection clamp pulse position CLP 3.26 µs (44 ck) Fig.8 MCE434 MCE433 Timing of some horizontal timing signals compared to incoming CVBS signal (1fH mode). Fig.9 Horizontal timing of HV pulses (1fH mode). line counter reset in digital decoder handbook, full pagewidth video second field first field HV pulse detected V pulse det det no norm video first field second field HV pulse detected V pulse det det no norm Fig.10 Recommended vertical timing of incoming HV pulses (1fH mode). 2004 Oct 04 42 MCE435 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 13 TEST AND APPLICATION INFORMATION 13.1 Power supply decoupling For optimal THD and SNR performance of the analog and digital audio channels, it is important to have stable 5 V and 8 V supply voltages for the audio part of the PNX3000. The following pins need a stable supply voltage without disturbances in the baseband audio frequency range: • Pins VCC(1ASW) and VCC(2ASW) (pins 98 and 88); the supply voltage for the analog audio switches. The supply current to both of these pins is less than 5 mA. Note that this supply voltage may be 5 V or 8 V. • Pin VAADCP (pin 91); the 5 V full scale reference for the audio ADCs. The current consumption of this pin is about 0.25 mA. This pin must only be connected to the 5 V supply if an audio supply voltage (pins VCC(1ASW) and VCC(2ASW)) of 5 V is used. If an audio supply of 8 V is used, this pin must not be connected to the 5 V supply voltage. In this case the reference voltage is generated by the IC itself, and only a decoupling capacitor should be connected to this pin. • Pin VCC(AADC) (pin 77) is the 5 V supply voltage for the audio ADCs. The supply current for this pin is about 23 mA. 2004 Oct 04 43 Philips Semiconductors Preliminary specification Analog front end for digital video processors Application diagram VCC_audio SAW TUNERAGC 93 92 90 470 470 nF nF L3 R2 L2 R1 L1 L3 R2 470 470 470 nF nF nF GND(2ASW) VCC(2ASW) VAADCREF VAADCN MIC1P GND(1ASW) VCC(1AASW) SIFINP VAADCP 91 89 88 87 86 85 84 83 82 (1) (1) 100 nF 100 nF CVBS2 (1) 100 nF Y3 1.6 kΩ 1.2 kΩ 8 9 (1) 11 12 13 14 15 16 17 18 19 20 21 (1) 100 nF C3 10 100 nF Y4 C4 100 nF (2) 2.2 µF (1) 100 nF (1) 100 nF (2) 100 nF VCC5 47 kΩ 470 nF VDEFLS 7 VDEFLO 6 CVBSOUTA 5 TESTPIN3 4 AMEXT 3 CCOMB 2 YCOMB 100 nF (1) RREF L5 128 1 VCC(FILT) 100 nF (1) FUSE CVBS1 GND(FILT) 100 nF (1) CVBS/Y4 CVBS0 BGDEC 100 nF (2) GND(VSW) CVBS_IF SCART1 VCC5 C3 180 Ω 94 (2) 100 nF L2 PNX3000 VAUDS 180 Ω 95 VIFPLL 111 GND(1IF) 112 2NDSIFEXT 113 2NDSIFAGC 114 GND(2IF) 115 DTVOUTP 116 DTVOUTN 117 VCC(SUP) 118 FUSE 119 CVBSOUTIF 120 GND(SUP) 121 VCC(1VSW) 122 CVBS0 123 TESTPIN1 124 VCC(2VSW) 125 CVBS1 126 R5 127 CVBS2 68 Ω 96 100 10 (2) µF nF R1 106 VIFINP 107 VIFINN 108 DTVIFPLL 109 VCC(IF) 110 CVBS/Y3 2.2 µF to DTV channel decoder 2.2 kΩ 97 470 nF CVBS_DTV CC5 100 nF (2) 10 nF 100 pF 2nd SIFext 98 10 µF L1 (2) 100 nF 105 VAUDO V 99 MIC2 470 nF 10 Ω 2.2 µF FUSE 1 µF 82 kΩ 100 nF 390 Ω SIFINN 102 101 100 103 104 DTVIFINP DTVIFINN SAW SIFAGC DTVIFAGC SIFIN DTVIFIN MIC1 100 nF (2) SAW ATVIFIN 220 Ω(3) MIC2P 2.2 µF FUSE 2.2 µF VCC5 10 µF 10 Ω 5.6 kΩ TUNERAGC MIC1N DTV AGC control MIC2N handbook, full pagewidth C4 13.2 PNX3000 1.8 kΩ 1.2 kΩ AMext A Y C B 3D-CMB VCC5 = 5 V analog supply. VCC_audio = 5 V or 8 V for audio switch matrix. 330 Ω (1) foil or ceramic capacitor. (2) ceramic multi-layer capacitor for supply decoupling. (3) This resistor is only used when VCC_audio = 5 V, remove if VCC_audio = 8 V. Fig.11 Application diagram (continued in Fig.12). 2004 Oct 04 2.2 kΩ 44 68 Ω CVBS SCART2 MCE437 Philips Semiconductors Preliminary specification Analog front end for digital video processors handbook, full pagewidth PNX3000 SCART1 L R VCC5 47 Ω R3 L4 L LINE R SCART2 R L DSND1 22 µF R4 DSND2 (1) 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VCC(I2D) 64 63 62 61 60 59 48 47 (1) 100 nF (1) B1 VCC5 (1) (1) 100 nF (1) 100 nF R2 G2 B2 3.3 nF GND(DIG) data link 1 GNDD data link 2 data link 3 VCCD5 100 nF (2) 100 nF (2) VD2V5 GNDD HV_PRIM 46 HV_SEC 45 SCL 44 SDA 43 IRQ 42 FUSE 41 XREF 40 ADR 39 38 37 ADOC or AVIP VCCD5 100 nF (2) 4.7 kΩ 3.3 V 4.7 kΩ 10 kΩ HV_PRIM HV_SEC SCL SDA IRQ (13.5 or 27 MHz) fref 750 Ω (2) 100 nF EWVIN VCC5 Vdeflection A Vaudio B MCE438 4.7 µF 2.2 kΩ 4.7 µF EWIOUT 330 Ω 68 Ω VCC5 = 5 V analog supply. VCCD5 = 5 V digital supply. GNDD = digital ground. (1) foil or ceramic capacitor. (2) ceramic multi-layer capacitor for supply decoupling. CVBS SCART3 Fig.12 Application diagram (continued from Fig.11). 2004 Oct 04 3.3 nF REW EWVIN 36 EWIOUT 35 VCC(VADC) 34 GND(VADC) 33 FUSE 32 B2/PB2/U2 31 G2/Y2/Y2 R2/PR2/V2 30 100 (2) 100 nF 100 nF nF (1) 100 nF R1 G1 29 GND(RGB) 28 VCC(RGB) 27 B1/PB1/U1 26 G1/Y1/Y1 25 R1/PR1/V1 24 TESTPIN2 FUSE CVBSOUTB 23 DATA1P DATA1N STROBE1P STROBE1N GND(I2D) DATA2P 58 DATA2N 57 STROBE2P 56 STROBE2N 55 FUSE 54 DATA3P 53 DATA3N 52 STROBE3P 51 STROBE3N 50 VCC(DIG) 49 PNX3000 22 3.3 nF SCART2R SCART2L LINER LINEL SCART1R SCART1L 3.3 nF FUSE DSNDR2 DSNDL2 DSNDR1 DSNDL1 470 470 470 470 nF nF nF nF GND(AADC) VCC(AADC) FUSE R4 L4 R3 470 470 470 100 nF nF nF nF 45 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 14 PACKAGE OUTLINE LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm SOT425-1 c y X A 102 103 65 64 ZE e E HE A A2 A 1 (A 3) θ wM Lp bp pin 1 index L detail X 39 128 1 38 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 14.1 13.9 0.5 HD HE 22.15 16.15 21.85 15.85 L Lp v w y 1 0.75 0.45 0.2 0.12 0.1 Z D(1) Z E(1) θ 0.81 0.59 7 o 0 0.81 0.59 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT425-1 136E28 MS-026 2004 Oct 04 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-20 46 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 with a high component density, as solder bridging and non-wetting can present major problems. 15 SOLDERING 15.1 Introduction to soldering surface mount packages To overcome these problems the double-wave soldering method was specifically developed. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; Reflow soldering – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. • below 225 °C (SnPb process) or below 245 °C (Pb-free process) A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. 15.4 Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards 2004 Oct 04 Manual soldering 47 Philips Semiconductors Preliminary specification Analog front end for digital video processors 15.5 PNX3000 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE REFLOW(2) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable(4) suitable PLCC(5), SO, SOJ suitable suitable not recommended(5)(6) suitable SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable LQFP, QFP, TQFP not suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar soldering or manual soldering is suitable for PMFP packages. 2004 Oct 04 48 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 16 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17 DEFINITIONS 18 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Oct 04 49 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 19 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2004 Oct 04 50 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R24/03/pp51 Date of release: 2004 Oct 04 Document order number: 9397 750 14086