Cirrus CS43L22-CNZ Low power, stereo dac w/headphone & speaker amp Datasheet

Confidential Draft
3/4/10
CS43L22
Low Power, Stereo DAC w/Headphone & Speaker Amps
FEATURES
Class D Stereo/Mono Speaker Amplifier
 98 dB Dynamic Range (A-wtd)
 No External Filter Required
 88 dB THD+N
 Headphone Amplifier - GND Centered
– No DC-Blocking Capacitors Required
– Integrated Negative Voltage Regulator
– 2 x 23 mW into Stereo 16 Ω @ 1.8 V
– 2 x 44 mW into Stereo 16 Ω @ 2.5V
 Stereo Analog Input Passthrough Architecture
–
–
Analog Input Mixing
Analog Passthrough with Volume Control
 High Stereo Output Power at 10% THD+N
– 2 x 1.00 W into 8 Ω @ 5.0 V
PCM Input w/Independent Vol Control
–
–
Master Digital Volume Control and Limiter
Soft-Ramp & Zero-Cross Transitions
–
2 x 230 mW into 8 Ω @ 2.5 V
–
1 x 1.00 W into 4 Ω @ 3.7 V
–
1 x 350 mW into 4 Ω @ 2.5 V
 Direct Battery Powered Operation
– Battery Level Monitoring & Compensation
 81% Efficiency at 800 mW
 Programmable Peak-Detect and Limiter
 Beep Generator w/Full Tone Control
–
–
–
–
2 x 550 mW into 8 Ω @ 3.7 V
 High Mono Output Power at 10% THD+N
– 1 x 1.90 W into 4 Ω @ 5.0 V
 Digital Signal Processing Engine
– Bass & Treble Tone Control, De-Emphasis
–
–
Tone Selections Across Two Octaves
Separate Volume Control
Programmable On and Off Time Intervals
Continuous, Periodic, One-Shot Beep
Selections
+1.65 V to +3.47 V
Interface Supply
 Phase-Aligned PWM Output Reduces Idle
Channel Current
 Spread Spectrum Modulation
 Low Quiescent Current
+1.60 V to +5.25 V
Battery
Battery Level Monitoring & Compensation
+
-
Control Port
Reset
Level Shifter
Serial
Audio
Input
Serial Audio Port
Pulse-Width
Modulator
I²C
Control
+
-
Class D Amps
Digital Volume,
Mono Mix,
Limiter, Bass,
Treble Adjust
Left HP/Line
Output
Multi-bit
ΔΣ DAC
Right HP/Line
Output
Ground-Centered
Amps
Beep
Generator
Σ
Summing
Amplifiers
Σ
-VHP
+VHP
Charge Pump
+1.65 V to +2.63 V
Digital Supply
http://www.cirrus.com
Stereo/Mono
Full-Bridge
Speaker
Outputs
12 3 4
1 23 4
Left
Inputs
Right
Inputs
Copyright  Cirrus Logic, Inc. 2010
(All Rights Reserved)
Speaker/HP
Switch
+1.65 V to +2.63 V
Headphone Supply
+1.65 V to +2.63 V
Analog Supply
MARCH '10
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Confidential Draft
3/4/10
CS43L22
System Features
General Description
 12, 24, and 27 MHz Master Clock Support in
The CS43L22 is a highly integrated, low power stereo DAC
with headphone and Class D speaker amplifiers. The
CS43L22 offers many features suitable for low power, portable system applications.
Addition to Typical Audio Clock Rates
 High Performance 24-bit Converters
–
–
Multi-bit Delta–Sigma Architecture
Very Low 64Fs Oversampling Clock Reduces
Power Consumption
 Low Power Operation
– Stereo Analog Passthrough: 10 mW @ 1.8 V
– Stereo Playback: 14 mW @ 1.8 V
 Variable Power Supplies
– 1.8 V to 2.5 V Digital & Analog
– 1.6 V to 5 V Class D Amplifier
– 1.8 V to 2.5 V Headphone Amplifier
– 1.8 V to 3.3 V Interface Logic
 Power Down Management
– DAC, Passthrough Amplifier, Headphone
Amplifier, Speaker Amplifier
 Flexible Clocking Options
– Master or Slave Operation
– Quarter-Speed Mode - (i.e. allows 8 kHz Fs
while maintaining a flat noise floor up to 16 kHz)
– 4 kHz to 96 kHz Sample Rates




I²CTM Control Port Operation
Headphone/Speaker Detection Input
Pop and Click Suppression
Pin-Compatible w/CS42L52
Applications
 PDA’s
 Personal Media Players
 Portable Game Consoles
2
The DAC output path includes a digital signal processing engine with various fixed function controls. Tone Control
provides bass and treble adjustment of four selectable corner
frequencies. Digital Volume controls may be configured to
change on soft ramp transitions while the analog controls can
be configured to occur on every zero crossing. The DAC also
includes de-emphasis, limiting functions and a BEEP generator delivering tones selectable across a range of two full
octaves.
The stereo headphone amplifier is powered from a separate
positive supply and the integrated charge pump provides a
negative supply. This allows a ground-centered analog output
with a wide signal swing and eliminates the need for external
DC-blocking capacitors.
The Class D stereo speaker amplifier does not require an
external filter and provides the high efficiency amplification required by power sensitive portable applications. The speaker
amplifier may be powered directly from a battery while the internal DC supply monitoring and compensation provides a
constant gain level as the battery’s voltage decays.
The CS43L22 accommodates analog routing of the analog input signal directly to the headphone amplifier. This feature is
useful in applications that utilize an FM tuner where audio recovered over-the-air must be transmitted to the headphone
amplifier directly.
In addition to its many features, the CS43L22 operates from a
low voltage analog and digital core making it ideal for portable
systems that require extremely low power consumption in a
minimal amount of space.
The CS43L22 is available in a 40-pin QFN package in Commercial (-40 to +85 °C) grade. The CS43L22 Customer
Demonstration board is also available for device evaluation
and implementation suggestions. Please refer to “Ordering Information” on page 66 for complete ordering information.
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CS43L22
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 7
1.1 I/O Pin Characteristics ..................................................................................................................... 8
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 9
3. CHARACTERISTIC AND SPECIFICATIONS ...................................................................................... 10
RECOMMENDED OPERATING CONDITIONS .................................................................................. 10
ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 10
ANALOG OUTPUT CHARACTERISTICS .......................................................................................... 11
ANALOG PASSTHROUGH CHARACTERISTICS .............................................................................. 12
PWM OUTPUT CHARACTERISTICS ................................................................................................. 13
HEADPHONE OUTPUT POWER CHARACTERISTICS ..................................................................... 14
LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS .................................................................... 15
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................. 15
SWITCHING SPECIFICATIONS - SERIAL PORT .............................................................................. 16
SWITCHING SPECIFICATIONS - I²C CONTROL PORT .................................................................... 17
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 18
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS .................................................... 18
POWER CONSUMPTION ................................................................................................................... 19
4. APPLICATIONS ................................................................................................................................... 20
4.1 Overview ........................................................................................................................................ 20
4.1.1 Basic Architecture ................................................................................................................. 20
4.1.2 Line Inputs ............................................................................................................................. 20
4.1.3 Line & Headphone Outputs ................................................................................................... 20
4.1.4 Speaker Driver Outputs ......................................................................................................... 20
4.1.5 Fixed Function DSP Engine .................................................................................................. 20
4.1.6 Beep Generator ..................................................................................................................... 20
4.1.7 Power Management .............................................................................................................. 20
4.2 DSP Engine .................................................................................................................................. 21
4.2.1 Beep Generator ..................................................................................................................... 22
4.2.2 Limiter .................................................................................................................................... 22
4.3 Analog Passthrough ....................................................................................................................... 24
4.4 Analog Outputs .............................................................................................................................. 25
4.5 PWM Outputs ................................................................................................................................. 26
4.5.1 Mono Speaker Output Configuration ..................................................................................... 27
4.5.2 VP Battery Compensation ..................................................................................................... 27
4.5.2.1 Maintaining a Desired Output Level ........................................................................... 27
4.6 Serial Port Clocking ....................................................................................................................... 29
4.7 Digital Interface Formats ................................................................................................................ 30
4.7.1 DSP Mode ............................................................................................................................. 31
4.8 Initialization .................................................................................................................................... 31
4.9 Recommended Power-Up Sequence ............................................................................................ 31
4.10 Recommended Power-Down Sequence ...................................................................................... 31
4.11 Required Initialization Settings ..................................................................................................... 32
5. CONTROL PORT OPERATION ........................................................................................................... 33
5.1 I²C Control ...................................................................................................................................... 33
5.1.1 Memory Address Pointer (MAP) ............................................................................................ 34
5.1.1.1 Map Increment (INCR) ............................................................................................... 34
6. REGISTER QUICK REFERENCE ........................................................................................................ 35
7. REGISTER DESCRIPTION .................................................................................................................. 37
7.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 37
7.1.1 Chip I.D. (Read Only) ............................................................................................................ 37
7.1.2 Chip Revision (Read Only) .................................................................................................... 37
7.2 Power Control 1 (Address 02h) ...................................................................................................... 37
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7.2.1 Power Down .......................................................................................................................... 37
7.3 Power Control 2 (Address 04h) ...................................................................................................... 38
7.3.1 Headphone Power Control .................................................................................................... 38
7.3.2 Speaker Power Control ......................................................................................................... 38
7.4 Clocking Control (Address 05h) ..................................................................................................... 38
7.4.1 Auto-Detect ........................................................................................................................... 38
7.4.2 Speed Mode .......................................................................................................................... 39
7.4.3 32kHz Sample Rate Group ................................................................................................... 39
7.4.4 27 MHz Video Clock .............................................................................................................. 39
7.4.5 Internal MCLK/LRCK Ratio ................................................................................................... 39
7.4.6 MCLK Divide By 2 ................................................................................................................. 40
7.5 Interface Control 1 (Address 06h) .................................................................................................. 40
7.5.1 Master/Slave Mode ............................................................................................................... 40
7.5.2 SCLK Polarity ........................................................................................................................ 40
7.5.3 DSP Mode ............................................................................................................................. 40
7.5.4 DAC Interface Format ........................................................................................................... 40
7.5.5 Audio Word Length ................................................................................................................ 41
7.6 Interface Control 2 (Address 07h) .................................................................................................. 41
7.6.1 SCLK equals MCLK .............................................................................................................. 41
7.6.2 Speaker/Headphone Switch Invert ........................................................................................ 41
7.7 Passthrough x Select: PassA (Address 08h), PassB (Address 09h) ............................................. 42
7.7.1 Passthrough Input Channel Mapping .................................................................................... 42
7.8 Analog ZC and SR Settings (Address 0Ah) ................................................................................... 42
7.8.1 Ch. x Analog Soft Ramp ........................................................................................................ 42
7.8.2 Ch. x Analog Zero Cross ....................................................................................................... 42
7.9 Passthrough Gang Control (Address 0Ch) .................................................................................... 42
7.9.1 Passthrough Channel B=A gang Control .............................................................................. 42
7.10 Playback Control 1 (Address 0Dh) ............................................................................................... 43
7.10.1 Headphone Analog Gain ..................................................................................................... 43
7.10.2 Playback Volume Setting B=A ............................................................................................ 43
7.10.3 Invert PCM Signal Polarity .................................................................................................. 43
7.10.4 Master Playback Mute ......................................................................................................... 43
7.11 Miscellaneous Controls (Address 0Eh) ........................................................................................ 44
7.11.1 Passthrough Analog ............................................................................................................ 44
7.11.2 Passthrough Mute ............................................................................................................... 44
7.11.3 Freeze Registers ................................................................................................................. 44
7.11.4 HP/Speaker De-Emphasis .................................................................................................. 44
7.11.5 Digital Soft Ramp ................................................................................................................ 44
7.11.6 Digital Zero Cross ................................................................................................................ 45
7.12 Playback Control 2 (Address 0Fh) ............................................................................................... 45
7.12.1 Headphone Mute ................................................................................................................. 45
7.12.2 Speaker Mute ...................................................................................................................... 45
7.12.3 Speaker Volume Setting B=A .............................................................................................. 45
7.12.4 Speaker Channel Swap ....................................................................................................... 45
7.12.5 Speaker MONO Control ...................................................................................................... 46
7.12.6 Speaker Mute 50/50 Control ............................................................................................... 46
7.13 Passthrough x Volume: PASSAVOL (Address 14h) & PASSBVOL (Address 15h) .................... 46
7.13.1 Passthrough x Volume ........................................................................................................ 46
7.14 PCMx Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh) ................................................... 47
7.14.1 PCM Channel x Mute .......................................................................................................... 47
7.14.2 PCM Channel x Volume ...................................................................................................... 47
7.15 Beep Frequency & On Time (Address 1Ch) ................................................................................ 47
7.15.1 Beep Frequency .................................................................................................................. 47
7.15.2 Beep On Time ..................................................................................................................... 48
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7.16 Beep Volume & Off Time (Address 1Dh) ..................................................................................... 48
7.16.1 Beep Off Time ..................................................................................................................... 48
7.16.2 Beep Volume ....................................................................................................................... 49
7.17 Beep & Tone Configuration (Address 1Eh) .................................................................................. 49
7.17.1 Beep Configuration .............................................................................................................. 49
7.17.2 Beep Mix Disable ................................................................................................................ 49
7.17.3 Treble Corner Frequency .................................................................................................... 50
7.17.4 Bass Corner Frequency ...................................................................................................... 50
7.17.5 Tone Control Enable ........................................................................................................... 50
7.18 Tone Control (Address 1Fh) ........................................................................................................ 50
7.18.1 Treble Gain .......................................................................................................................... 50
7.18.2 Bass Gain ............................................................................................................................ 51
7.19 Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h) ....................................... 51
7.19.1 Master Volume Control ........................................................................................................ 51
7.20 Headphone Volume Control: HPA (Address 22h) & HPB (Address 23h) .................................... 51
7.20.1 Headphone Volume Control ................................................................................................ 51
7.21 Speaker Volume Control: SPKA (Address 24h) & SPKB (Address 25h) ..................................... 52
7.21.1 Speaker Volume Control ..................................................................................................... 52
7.22 PCM Channel Swap (Address 26h) ............................................................................................. 52
7.22.1 PCM Channel Swap ............................................................................................................ 52
7.23 Limiter Control 1, Min/Max Thresholds (Address 27h) ................................................................. 53
7.23.1 Limiter Maximum Threshold ................................................................................................ 53
7.23.2 Limiter Cushion Threshold .................................................................................................. 53
7.23.3 Limiter Soft Ramp Disable ................................................................................................... 53
7.23.4 Limiter Zero Cross Disable .................................................................................................. 54
7.24 Limiter Control 2, Release Rate (Address 28h) ........................................................................... 54
7.24.1 Peak Detect and Limiter ...................................................................................................... 54
7.24.2 Peak Signal Limit All Channels ........................................................................................... 54
7.24.3 Limiter Release Rate ........................................................................................................... 54
7.25 Limiter Attack Rate (Address 29h) ............................................................................................... 55
7.25.1 Limiter Attack Rate .............................................................................................................. 55
7.26 Status (Address 2Eh) (Read Only) .............................................................................................. 55
7.26.1 Serial Port Clock Error (Read Only) .................................................................................... 55
7.26.2 DSP Engine Overflow (Read Only) ..................................................................................... 55
7.26.3 PCMx Overflow (Read Only) ............................................................................................... 56
7.27 Battery Compensation (Address 2Fh) .......................................................................................... 56
7.27.1 Battery Compensation ......................................................................................................... 56
7.27.2 VP Monitor ........................................................................................................................... 56
7.27.3 VP Reference ...................................................................................................................... 57
7.28 VP Battery Level (Address 30h) (Read Only) .............................................................................. 57
7.28.1 VP Voltage Level (Read Only) ............................................................................................ 57
7.29 Speaker Status (Address 31h) (Read Only) ................................................................................ 57
7.29.1 Speaker Current Load Status (Read Only) ......................................................................... 57
7.29.2 SPKR/HP Pin Status (Read Only) ....................................................................................... 58
7.30 Charge Pump Frequency (Address 34h) ..................................................................................... 58
7.30.1 Charge Pump Frequency .................................................................................................... 58
8. ANALOG PERFORMANCE PLOTS .................................................................................................... 59
8.1 Headphone THD+N versus Output Power Plots ............................................................................ 59
9. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 61
9.1 Auto Detect Enabled ................................................................................................................... 61
9.2 Auto Detect Disabled ................................................................................................................... 61
10. PCB LAYOUT CONSIDERATIONS ................................................................................................... 62
10.1 Power Supply, Grounding ............................................................................................................ 62
10.2 QFN Thermal Pad ........................................................................................................................ 62
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11. DIGITAL FILTER PLOTS ................................................................................................................... 63
12. PARAMETER DEFINITIONS .............................................................................................................. 64
13. PACKAGE DIMENSIONS .................................................................................................................. 65
THERMAL CHARACTERISTICS ......................................................................................................... 65
14. ORDERING INFORMATION .............................................................................................................. 66
15. REFERENCES .................................................................................................................................... 66
16. REVISION HISTORY .......................................................................................................................... 66
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 9
Figure 2. Headphone Output Test Load .................................................................................................... 14
Figure 3. Serial Audio Interface Timing ..................................................................................................... 16
Figure 4. Control Port Timing - I²C ............................................................................................................ 17
Figure 5. DSP Engine Signal Flow ............................................................................................................ 21
Figure 6. Beep Configuration Options ....................................................................................................... 22
Figure 7. Peak Detect & Limiter ................................................................................................................ 23
Figure 8. Analog Passthrough Signal Flow ............................................................................................... 24
Figure 9. Analog Outputs .......................................................................................................................... 25
Figure 10. PWM Output Stage .................................................................................................................. 26
Figure 11. Battery Compensation ............................................................................................................. 28
Figure 12. I²S Format ................................................................................................................................ 30
Figure 13. Left-Justified Format ................................................................................................................ 30
Figure 14. Right-Justified Format\ ............................................................................................................. 30
Figure 15. DSP Mode Format) .................................................................................................................. 31
Figure 16. Control Port Timing, I²C Write .................................................................................................. 33
Figure 17. Control Port Timing, I²C Read .................................................................................................. 33
Figure 18. THD+N vs. Output Power per Channel at 1.8 V (16 Ω load) ................................................... 59
Figure 19. THD+N vs. Output Power per Channel at 2.5 V (16 Ω load) ................................................... 59
Figure 20. THD+N vs. Output Power per Channel at 1.8 V (32 Ω load) ................................................... 60
Figure 21. THD+N vs. Output Power per Channel at 2.5 V (32 Ω load) ................................................... 60
Figure 22. Passband Ripple ...................................................................................................................... 63
Figure 23. Stopband .................................................................................................................................. 63
Figure 24. DAC Transition Band ............................................................................................................... 63
Figure 25. Transition Band (Detail) ........................................................................................................... 63
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TSTO
DGND
VD
VL
RESET
SPKR/HP
36
35
34
33
32
31
MCLK
37
SDIN
SCLK
39
38
LRCK
SDA
1
30
AIN1B
SCL
2
29
AIN1A
AD0
3
28
AFILTB
SPKR_OUTA+
4
27
AFILTA
VP
5
26
AIN2B
SPKR_OUTA-
6
25
AIN2A
SPKR_OUTB+
7
24
AIN3B
VP
8
23
AIN3A
SPKR_OUTB-
9
22
AIN4B
-VHPFILT
10
21
AIN4A
Pin Name
SDA
SCL
AD0
SPKR_OUTA+
SPKR_OUTASPKR_OUTB+
SPKR_OUTBVP
-VHPFILT
FLYN
FLYP
+VHP
HP/LINE_OUTB, A
VA
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1. PIN DESCRIPTIONS
#
1
2
3
4
6
7
9
5
8
10
GND/Thermal Pad
11
12
13
14
15
16
17
18
19
20
FLYN
FLYP
+VHP
HP/LINE_OUTB
HP/LINE_OUTA
VA
AGND
FILT+
VQ
TSTO
Top-Down (Through-Package) View
40-Pin QFN Package
Pin Description
Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode.
Serial Control Port Clock (Input) - Serial clock for the serial control port.
Address Bit 0 (I²C) (Input) - AD0 is a chip address pin in I²C Mode.
PWM Speaker Output (Output) - Full-bridge amplified PWM speaker outputs.
Power for PWM Drivers (Input) - Power supply for the PWM output driver stages.
Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge
pump that provides the negative rail for the headphone/line amplifiers.
11 Charge Pump Cap Negative Node (Output) - Negative node for the inverting charge pump’s flying capacitor.
12 Charge Pump Cap Positive Node (Output) - Positive node for the inverting charge pump’s flying
capacitor.
13 Positive Analog Power for Headphone (Input) - Positive voltage rail and power for the internal
headphone amplifiers and inverting charge pump.
14,15 Headphone/Line Audio Output (Output) - Stereo headphone or line level analog outputs.
16 Analog Power (Input) - Positive power for the internal analog section.
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AGND
FILT+
VQ
17
18
19
20,36
TSTO
AIN4A,B
AIN3A,B
AIN2A,B
AIN1A,B
AFILTA,AFILTB
SPKR/HP
RESET
VL
VD
DGND
MCLK
SCLK
SDIN
LRCK
GND/Thermal Pad
1.1
CS43L22
Analog Ground (Input) - Ground reference for the internal analog section.
Positive Voltage Reference (Output) - Filter connection for the internal sampling circuits.
Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no
connection external to the pin).
21,22
23,24
Line-Level Analog Inputs (Input) - Single-ended stereo line-level analog inputs.
25,26
29,30
27,28 Anti-alias Filter Connection (Output) - Anti-alias filter connection for analog passthrough mode.
31 Speaker/Headphone Switch (Input) - Powers down the left and/or right channel of the speaker
and/or headphone outputs.
32 Reset (Input) - The device enters a low power mode when this pin is driven low.
33 Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port.
34 Digital Power (Input) - Positive power for the internal digital section.
35 Digital Ground (Input) - Ground reference for the internal digital section.
37 Master Clock (Input) - Clock source for the delta-sigma modulators.
38 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
39 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
40 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on
the serial audio data line.
Ground reference for PWM power FETs and charge pump; thermal relief pad for optimized heat
dissipation.
I/O Pin Characteristics
Input and output levels and associated power supply voltage are shown in the table below. Logic levels
should not exceed the corresponding power supply voltage.
Power
Supply
VL
Pin Name
I/O
Internal
Connections
Driver
Receiver
RESET
AD0
SCL
SDA
Input
Input
Input
Input/
Output
Input
Input/
Output
Input/
Output
Input
Input
Output
Output
Output
Output
-
1.65 V - 3.47 V, CMOS/Open
Drain
1.65 V - 3.47 V, CMOS
1.65 V - 3.47 V, with Hysteresis
1.65 V - 3.47 V, with Hysteresis
1.65 V - 3.47 V, with Hysteresis
1.65 V - 3.47 V, with Hysteresis
1.65 V - 3.47 V, CMOS
1.65 V - 3.47 V
1.6 V - 5.25 V Power MOSFET
1.6 V - 5.25 V Power MOSFET
1.6 V - 5.25 V Power MOSFET
1.6 V - 5.25 V Power MOSFET
1.65 V - 3.47 V
1.65 V - 2.63 V
-
MCLK
LRCK
SCLK
VA
VP
8
SDIN
SPKR/HP
SPKR_OUTA+
SPKR_OUTASPKR_OUTB+
SPKR_OUTB-
Weak Pull-up
(~1 MΩ)
Weak Pull-up
(~1 MΩ)
-
1.65 V - 3.47 V
1.65 V - 3.47 V
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2. TYPICAL CONNECTION DIAGRAM
+1.8 V to +2.5 V
+1.8 V to +2.5 V
1 µF
0.1 µF
0.1 µF
0.1 µF
VD
VA
1 µF
See Note 4
+VHP
Line Level Out
Left & Right
47 kΩ
0.022 µF
Note 1
1 µF
**
FLYP
HP/LINE_OUTB
FLYN
HP/LINE_OUTA
Headphone Out
Left & Right
51.1 Ω
0.022 µF
Note 2
-VHPFILT
1 µF
51.1 Ω
SPKR/HP
**
CS43L22
VP
0.1 µF
10 µF
+1.6 V to
Stereo Speakers
+5 V
SPKR_OUTA+
SPKR_OUTAVP
0.1 µF
SPKR_OUTB+
SPKR_OUTB-
MCLK
SCLK
LRCK
SDIN
Digital Audio
Processor
**
AIN1A
100 Ω
RESET
1 µF
Left 1
100 kΩ
Analog
Input 1
SCL
SDA
100 Ω
AIN1B
**
AIN2A
100 Ω
1 µF
2 kΩ
+1.8 V to +3.3 V
Right 1
1 µF
AD0
2 kΩ
100 kΩ
**
100 Ω
AIN2B
VL
Left 2
100 kΩ
Analog
Input 2
100 kΩ
**
Right 2
1 µF
0.1 µF
**
AIN3A
100 Ω
1 µF
100 Ω
AIN3B
Left 3
100 kΩ
100 kΩ
**
Right 3
1 µF
Notes:
1. Recommended values for the default charge pump switching
frequency. The required capacitance follows an inverse
relationship with the charge pump’s switching frequency. When
increasing the switching frequency, the capacitance may
decrease; when lowering the switching frequency, the
capacitance must increase.
2. Larger capacitance reduces the ripple on the internal
amplifier’s supply. This may reduce the distortion at higher
output power levels.
3. Additional bulk capacitance may be added to improve PSRR
at low frequencies.
4. Series resistance in the path of the power supplies must be
avoided. Any voltage drop on VHP will directly impact the
negative charge pump supply (-VHPFILT) and clip the audio
output.
**
AIN4A
100 Ω
1 µF
Left 4
100 kΩ
Analog
Input 4
100 kΩ
**
100 Ω
AIN4B
Analog
Input 3
Right 4
1 µF
Note 3
AGND
*
TSTO
150 pF
AFILTA
AFILTB
TSTO
*
150 pF
1 µF
10 µF
VQ
FILT+
DGND
* Capacitors must be C0G or equivalent
** Low ESR, X7R/X5R dielectric capacitors.
Figure 1. Typical Connection Diagram
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3. CHARACTERISTIC AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
AGND=DGND=0 V, all voltages with respect to ground.
Parameters
DC Power Supply
Analog
Headphone Amplifier
Speaker Amplifier
Digital
Serial/Control Port Interface
Ambient Temperature
Commercial
Symbol
Min
Max
Units
VA
+VHP
VP
VD
VL
TA
1.65
1.65
1.60
1.65
1.65
-40
2.63
2.63
5.25
2.63
3.47
+85
V
V
V
V
V
°C
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V; all voltages with respect to ground.
Parameters
DC Power Supply
Input Current
Analog Input Voltage
Analog
Speaker
Digital
Serial/Control Port Interface
(Note 1)
(Note 2)
External Voltage Applied to Analog Input
(Note 2)
External Voltage Applied to Analog Output
External Voltage Applied to Digital Input
Ambient Operating Temperature (power applied)
Storage Temperature
(Note 2)
Symbol
Min
Max
Units
VA, VHP
VP
VD
VL
Iin
-0.3
-0.3
-0.3
-0.3
AGND-0.7
3.0
5.5
3.0
4.0
±10
VA+0.7
V
V
V
V
mA
AGND-0.3
VA+0.3
V
VIN
-VHP - 0.3
+VHP + 0.3
V
VIND
TA
Tstg
-0.3
-50
-65
VL+ 0.3
+115
+150
V
°C
°C
VIN
VIN
V
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
Notes:
1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
2. The maximum over/under voltage is limited by the input current.
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ANALOG OUTPUT CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA; TA = +25°C;
Sample Frequency = 48 kHz; Measurement bandwidth is 20 Hz to 20 kHz; Test load RL = 10 kΩ, CL = 10 pF for the line output
(see Figure 2); Test load RL = 16 Ω, CL = 10 pF (see Figure 2) for the headphone output; HP_GAIN[2:0] = 011.
VA = 2.5 V
Min
Typ
Max
Parameters (Note 3)
VA = 1.8 V
Min
Typ
Max
Unit
RL = 10 kΩ
Dynamic Range
18 to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
16-Bit
92
89
-
98
95
96
93
-
89
86
-
95
92
93
90
-
dB
dB
dB
dB
-
-86
-75
-35
-86
-73
-33
-80
-29
-
-
-88
-72
-32
-88
-70
-30
-82
-26
-
dB
dB
dB
dB
dB
dB
92
89
-
98
95
96
93
-
89
86
-
95
92
93
90
-
dB
dB
dB
dB
-
-75
-75
-35
-75
-73
-33
-69
-29
-
-
-75
-72
-32
-75
-70
-30
-69
-26
-
dB
dB
dB
dB
dB
dB
RL = 16 Ω
Dynamic Range
18 to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Other Characteristics for RL = 16 Ω or 10 kΩ
Output Parameters
Modulation Index (MI)
0.6787
0.6787
V/V
(Note 4)
Analog Gain Multiplier (G)
0.6047
0.6047
V/V
Full-scale Output Voltage (2•G•MI•VA) (Note 4)
Refer to Table “Headphone Output Power CharacterisVpp
tics” on page 14
Full-scale Output Power (Note 4)
Refer to Table “Headphone Output Power Characteristics” on
page 14
Interchannel Isolation (1 kHz)
16 Ω
80
80
dB
10 kΩ
95
93
dB
Speaker Amp to HP Amp Isolation
80
80
dB
Interchannel Gain Mismatch
0.1
0.25
0.1
0.25
dB
Gain Drift
±100
±100
ppm/°C
AC-Load Resistance (RL)
(Note 5)
16
16
Ω
Load Capacitance (CL)
(Note 5)
-
-
150
-
-
150
pF
3. One (least-significant bit) LSB of triangular PDF dither is added to data.
4. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog
Gain” on page 43. High gain settings at certain VA and VHP supply levels may cause clipping when the
audio signal approaches full-scale, maximum power output, as shown in Figures 18 - 21 on page 60.
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5. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively
move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recommended 150 pF can cause the internal op-amp to become unstable.
ANALOG PASSTHROUGH CHARACTERISTICS
Test Conditions (unless otherwise specified): Input sine wave (relative to full-scale): 1 kHz through passive input filter;
Passthrough Amplifier and HP/Line Gain = 0 dB; All Supplies = VA; TA = +25°C; Sample Frequency = 48 kHz; Measurement
Bandwidth is 20 Hz to 20 kHz.
Min
VA = 2.5 V
Typ
Max
A-weighted
unweighted
-1 dBFS
-20 dBFS
-60 dBFS
-
-96
-93
-70
-73
-33
0.91•VA
0.84•VA
0/-0.3
A-weighted
unweighted
-1 dBFS
-20 dBFS
-60 dBFS
-
-96
-93
-70
-73
-33
0.91•VA
0.84•VA
32
0/-0.3
Parameters
Min
VA = 1.8 V
Typ
Max
Unit
-
-
-94
-91
-70
-71
-31
0.91•VA
0.84•VA
0/-0.3
-
dB
dB
dB
dB
dB
Vpp
Vpp
dB
-
-
-94
-91
-70
-71
-31
0.91•VA
0.84•VA
17
0/-0.3
-
dB
dB
dB
dB
dB
Vpp
Vpp
mW
dB
Analog In to HP/Line Amp
RL = 10 kΩ
Dynamic Range
Total Harmonic Distortion + Noise
Full-scale Input Voltage
Full-scale Output Voltage
Passband Ripple
RL = 16 Ω
Dynamic Range
Total Harmonic Distortion + Noise
Full-scale Input Voltage
Full-scale Output Voltage
Output Power
Passband Ripple
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PWM OUTPUT CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full scale 997 Hz signal; MCLK = 12.2880 MHz; Measurement
Bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 8 Ω for stereo full-bridge, RL = 4 Ω for mono parallel
full-bridge; VD = VL = VA = VHP = 1.8V; PWM Modulation Index of 0.85; PWM Switch Rate = 384 kHz.
Parameters (Note 7)
Symbol
VP = 5.0 V
Power Output per Channel
Stereo Full-Bridge
PO
Mono Parallel Full-Bridge
Total Harmonic Distortion + Noise
THD+N
Stereo Full-Bridge
Mono Parallel Full-Bridge
Dynamic Range
Min
Typ
Max
Units
THD+N < 10%
THD+N < 1%
THD+N < 10%
THD+N < 1%
-
1.00
0.80
1.90
1.50
-
Wrms
Wrms
Wrms
Wrms
PO = 0 dBFS = 0.8W
PO = -3 dBFS = 0.75 W
PO = 0 dBFS = 1.5 W
-
0.52
0.10
0.50
-
%
%
%
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
-
91
88
91
88
-
dB
dB
dB
dB
THD+N < 10%
THD+N < 1%
THD+N < 10%
THD+N < 1%
-
0.55
0.45
1.00
0.84
-
Wrms
Wrms
Wrms
Wrms
PO = 0 dBFS = 0.43 W
PO = -3 dBFS = 0.41 W
PO = 0 dBFS = 0.81 W
-
0.54
0.09
0.45
-
%
%
%
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
-
91
88
95
92
-
dB
dB
dB
dB
THD+N < 10%
THD+N < 1%
THD+N < 10%
THD+N < 1%
-
0.23
0.19
0.44
0.35
-
Wrms
Wrms
Wrms
Wrms
PO = 0 dBFS = 0.18 W
PO = -3 dBFS = 0.17 W
PO = 0 dBFS = 0.35 W
-
0.50
0.08
0.43
-
%
%
%
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
VP = 5.0V, Id = 0.5 A
VP = 3.7V, Id = 0.5 A
-
91
88
94
91
600
640
-
dB
dB
dB
dB
mΩ
mΩ
DR
Stereo Full-Bridge
Mono Parallel Full-Bridge
VP = 3.7 V
Power Output per Channel
Stereo Full-Bridge
PO
Mono Parallel Full-Bridge
Total Harmonic Distortion + Noise
THD+N
Stereo Full-Bridge
Mono Parallel Full-Bridge
Dynamic Range
DR
Stereo Full-Bridge
Mono Parallel Full-Bridge
VP =2.5 V
Power Output per Channel
Stereo Full-Bridge
PO
Mono Parallel Full-Bridge
Total Harmonic Distortion + Noise
THD+N
Stereo Full-Bridge
Mono Parallel Full-Bridge
Dynamic Range
DR
Stereo Full-Bridge
Mono Parallel Full-Bridge
MOSFET On Resistance
MOSFET On Resistance
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Conditions
RDS(ON)
RDS(ON)
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Parameters (Note 7)
MOSFET On Resistance
Efficiency
CS43L22
Symbol
Conditions
Min
Typ
Max
Units
RDS(ON)
η
VP = 2.5V, Id = 0.5 A
VP = 5.0 V, PO = 2 x 0.8 W, RL =
8Ω
-
760
81
-
mΩ
%
-
0.8
1.5
5.0
A
µA
Output Operating Peak Current
VP Input Current During Reset
IPC
IVP
RESET, pin 32, is held low
6. The PWM driver should be used in captive speaker systems only.
7. Optimal PWM performance is achieved when MCLK > 12 MHz.
HEADPHONE OUTPUT POWER CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; Sample Frequency = 48 kHz;
Measurement Bandwidth is 20 Hz to 20 kHz; Test load RL = 16 Ω, CL = 10 pF (see Figure 2); “Required Initialization Settings”
on page 32 written on power up.
Parameters
Min
VA = 2.5V
Typ
Max
Min
VA = 1.8V
Typ
Unit
Max
AOUTx Power Into RL = 16 Ω
HP_GAIN[2:0]
000
Analog
Gain (G)
0.3959
001
0.4571
010
0.5111
011 (default)
0.6047
100
0.7099
101
0.8399
110
1.0000
111
1.1430
VHP
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
-
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
14
14
19
19
23
23
(Note 8)
32
(Note 8)
44
-
7
7
10
10
12
12
17
17
23
23
(Note 4) See Figure 18 on
page 59
32
(Note 4, 8) See Figures 18 and 19 on page 59
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
mWrms
8. VHP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC
may not achieve the full THD+N performance at full-scale output voltage and power.
AOUTx
51 Ω
C
L
R
L
0.022 μF
AGND
Figure 2. Headphone Output Test Load
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CS43L22
LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 20 Hz
to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 10 kΩ, CL = 10 pF (see Figure 2); “Required Initialization Settings” on
page 32 written on power up.
Parameters
Min
VA = 2.5V
Typ
Max
Min
2.15
-
1.41
-
-
-
VA = 1.8V
Typ
Unit
Max
AOUTx Voltage Into RL = 10 kΩ
HP_GAIN[2:0]
000
Analog
Gain (G)
0.3959
001
0.4571
010
0.5111
011 (default)
0.6047
100
0.7099
101
0.8399
110
1.0000
111
1.1430
VHP
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.8 V
2.5 V
1.95
-
1.34
1.34
1.55
1.55
1.73
1.73
2.05
2.05
2.41
2.41
2.85
2.85
3.39
3.39
(See (Note 8)
3.88
-
0.97
0.97
1.12
1.12
1.25
1.25
1.48
1.48
1.73
1.73
2.05
2.05
2.44
2.44
2.79
2.79
1.55
-
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameters (Note 9)
Frequency Response 10 Hz to 20 kHz
Passband
to -0.05 dB corner
to -3 dB corner
StopBand
StopBand Attenuation (Note 10)
Group Delay
De-emphasis Error
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Min
Typ
Max
Unit
-0.01
-
+0.08
dB
0
0
-
0.4780
0.4996
Fs
Fs
0.5465
-
-
Fs
50
-
-
dB
-
9/Fs
-
s
-
-
+1.5/+0
+0.05/-0.25
-0.2/-0.4
dB
dB
dB
9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 22 and 25 on
page 63) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
10. Measurement Bandwidth is from Stopband to 3 Fs.
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SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = DGND; Logic 1 = VL.
Parameters
Symbol
RESET pin Low Pulse Width
MCLK Frequency (Note 12)
(Note 11)
MCLK Duty Cycle
Min
Max
1
-
Units
ms
(See “Serial Port Clocking” on page 29)
45
55
MHz
(See “Serial Port Clocking” on page 29)
45
55
64•Fs
45
55
40
20
20
-
kHz
(See “Serial Port Clocking” on page 29)
45
55
12.0000
68•Fs
64•Fs
45
55
20
20
-
Hz
%
Slave Mode
Sample Rate (LRCK)
Fs
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
1/tP
ts(LK-SK)
ts(SD-SK)
th
%
Hz
%
ns
ns
ns
Master Mode
Sample Rate (LRCK)
Fs
LRCK Duty Cycle
SCLK Frequency
SCLK=MCLK mode
MCLK=12.0000 MHz
all other modes
SCLK Duty Cycle
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
1/tP
1/tP
1/tP
ts(SD-SK)
th
%
MHz
Hz
Hz
%
ns
ns
11. After powering up the CS43L22, RESET should be held low after the power supplies and clocks are
settled.
12. See “Example System Clock Frequencies” on page 61 for typical MCLK frequencies.
//
LRCK
ts(LK-SK)
//
tP
//
SCLK
//
ts(SD-SK)
SDIN
//
MSB
//
th
MSB-1
Figure 3. Serial Audio Interface Timing
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CS43L22
SWITCHING SPECIFICATIONS - I²C CONTROL PORT
Inputs: Logic 0 = DGND; Logic 1 = V; SDA CL = 30 pF.
Parameters
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RESET Rising Edge to Start
tirs
550
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
SDA Hold Time from SCL Falling
(Note 13)
thdd
0
-
µs
tsud
250
-
ns
Rise Time of SCL and SDA
trc
-
1
µs
Fall Time SCL and SDA
tfc
-
300
ns
SDA Setup time to SCL Rising
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
13. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RESET
t irs
Stop
Repeated
Start
Start
Stop
SDA
t buf
t
t high
t hdst
tf
hdst
t susp
SCL
t
low
t
hdd
t sud
t sust
tr
Figure 4. Control Port Timing - I²C
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DC ELECTRICAL CHARACTERISTICS
AGND = 0 V; all voltages with respect to ground.
Parameters
Min
Typ
Max
Units
-
0.5•VA
23
-
1
V
kΩ
μA
VQ Characteristics
Nominal Voltage
Output Impedance
DC Current Source/Sink
Power Supply Rejection Ratio Characteristics
PSRR @ 1 kHz (Note 14)
DAC (HP & Line Amps)
-
60
-
dB
PSRR @ 60 Hz (Note 14)
DAC (HP & Line Amps)
-
60
-
dB
Full-Bridge PWM Outputs
-
56
-
dB
PSRR @ 217 Hz
14. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also
increase the PSRR.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 15)
Input Leakage Current
Symbol
Min
Max
Units
Iin
-
±10
μA
-
10
pF
Input Capacitance
1.8 V - 3.3 V Logic
High-Level Output Voltage (IOH = -100 μA)
VOH
VL - 0.2
-
V
Low-Level Output Voltage (IOL = 100 μA)
VOL
-
0.2
V
VIH
0.85•VL
0.77•VL
0.68•VL
0.65•VL
-
V
V
V
V
VIL
-
0.30•VL
V
High-Level Input Voltage
Low-Level Input Voltage
VL = 1.65 V
VL = 1.8 V
VL = 2.0 V
VL > 2.0 V
15. See “I/O Pin Characteristics” on page 8 for serial and control port power rails.
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POWER CONSUMPTION See (Note 16)
PDN_HPA[1:0]
PDN_SPKB[1:0]
PDN_SPKA[1:0]
Typical Current (mA)
PDN_HPB[1:0]
Register Settings
02h
04h
PDN[7:0]
Operation
x
x
x
x
x
Standby (Note 18)
0x9F
x
x
3
Stereo Passthrough to Headphone
0x9E 10 10
4
Mono Playback to Headphone
0x9E 10 11
5
Stereo Playback to Headphone
0x9E 10 10
6
Mono Playback to Speaker
0x9E 11
11
7
Stereo Playback to Speaker
0x9E 11
11
1
Off (Note 17)
2
iVHP
iVA
iVD
iVL
iVP
VL=3.3V
(Note 19)
VP=3.7V
0.00
0.00
0.00
0.00
0.01
0.00
0.01
0.00
0.01
0.00
0.01
1.00
0.01
1.00
Total
Power
(mWrms)
V
1.8
2.5
x
x 1.8
2.5
11 11 1.8
2.5
11 11 1.8
2.5
11 11 1.8
2.5
10 10 1.8
2.5
10 10 1.8
2.5
0.00
0.00
0.00
0.00
2.79
3.18
1.59
2.07
2.77
3.27
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
1.91
2.14
1.99
2.62
2.00
2.63
0.20
0.22
0.20
0.22
0.00
0.00
0.01
0.02
1.06
1.81
2.72
4.27
2.91
4.28
4.42
6.77
4.38
6.80
0.00
0.00
0.02
0.05
10.39
17.85
11.36
22.43
13.84
25.48
12.05
21.21
11.98
21.28
16. Unless otherwise noted, test conditions are as follows: All zeros input, Slave Mode, sample
rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode
and master/slave operation.“Required Initialization Settings” on page 32 written on power up.
17. RESET pin 25 held LO, all clocks and data lines are held LO.
18. RESET pin 25 held HI, all clocks and data lines are held HI.
19. VL current will slightly increase in Master Mode.
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CS43L22
4. APPLICATIONS
4.1
4.1.1
Overview
Basic Architecture
The CS43L22 is a highly integrated, low power, 24-bit audio DAC comprised of a Digital Signal Processing
Engine, headphone amplifiers, a digital PWM modulator and two full-bridge power back-ends. Other features include battery level monitoring and compensation and temperature monitoring. The DAC is designed using multi-bit delta-sigma techniques and operates at an oversampling ratio of 128Fs, where Fs
is equal to the system sample rate.
The PWM modulator operates at a fixed frequency of 384 kHz. The power MOSFETs are configured for
either stereo full-bridge or mono parallel full bridge output. The DAC operates in one of four sample rate
speed modes: Quarter, Half, Single and Double. It accepts and is capable of generating serial port clocks
(SCLK, LRCK) derived from an input Master Clock (MCLK).
4.1.2
Line Inputs
4 pairs of stereo analog inputs are provided for applications that require analog passthrough directly to
the HP/Line amplifiers. This analog input portion allows selection from and configuration of multiple combinations of these stereo sources.
4.1.3
Line & Headphone Outputs
The analog output portion of the CS43L22 includes a headphone amplifier capable of driving headphone
and line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale
output swing centered around ground. This eliminates the need for large DC-Blocking capacitors and allows the amplifier to deliver more power to headphone loads at lower supply voltages.
4.1.4
Speaker Driver Outputs
The Class D power amplifiers drive 8 Ω (stereo) and 4 Ω (mono) speakers directly, without the need for
an external filter. The power MOSFETS are powered directly from a battery eliminating the efficiency loss
associated with an external regulator. Battery level monitoring and compensation maintains a steady output as battery levels fall. A temperature monitor continually measures the die temperature and registers
when predefined thresholds are exceeded. NOTE: The CS43L22 should only be used in captive speaker
systems where the outputs are permanently tied to the speaker terminals.
4.1.5
Fixed Function DSP Engine
The fixed-function digital signal processing engine processes the PCM serial input data. Independent volume control, left/right channel swaps, mono mixes, tone control and limiting functions also comprise the
DSP engine.
4.1.6
Beep Generator
The beep generator delivers tones at select frequencies across approximately two octave major scales.
With independent volume control, beeps may be configured to occur continuously, periodically, or at single time intervals.
4.1.7
Power Management
Two control registers provide independent power-down control of the DAC, Headphone and Speaker output blocks in the CS43L22 allowing operation in select applications with minimal power consumption.
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4.2
CS43L22
DSP Engine
Fixed Function DSP
LIMARATE[7:0]
LIMRRATE[7:0]
LMAX[2:0]
CUSH[2:0]
LIMSRDIS
LIMZCDIS
LIMIT
MSTAVOL[7:0]
MSTBVOL[7:0]
+12dB/-102dB
0.5dB steps
PCM Serial Interface
Chnl Vol.
Settings
Limiter
PWM
Modulator
PCMAMUTE
PCMBMUTE
PCMAVOL[6:0]
PCMBVOL[6:0]
+12dB/-51.5dB
0.5dB steps
Demph
DEEMPH
Peak
Detect
PCMASWAP[1:0]
PCMBSWAP[1:0]
VOL
Σ
Channel
Swap
INV_PCMA
INV_PCMB
MSTAMUTE
MSTBMUTE
DIGSFT
DIGZC
PLYBCKB=A
BPVOL[4:0]
OFFTIME[2:0]
ONTIME[3:0]
FREQ[3:0]
BEEP[1:0]
BEEPMIXDIS
0dB/-50dB
2.0dB steps
Beep
Generator
VOL
VOL
Bass/
Treble/
Control
TC_EN
BASS_CF[1:0]
TREB_CF[1:0]
BASS[3:0]
TREB[3:0]
+12.0dB/-10.5dB
1.5dB steps
DAC
Figure 5. DSP Engine Signal Flow
Referenced Control
Register Location
DSP
DEEMPH .............................
PCMxMUTE ........................
PCMxVOL[6:0] ....................
INV_PCMx...........................
PCMxSWAP[1:0] .................
MSTxVOL[7:0].....................
MSTxMUTE.........................
DIGSFT ...............................
DIGZC .................................
PLYBCKB=A........................
TC_EN.................................
BASS_CF[1:0] .....................
TREB_CF[1:0] .....................
BASS[3:0]............................
TREB[3:0]............................
LIMIT ...................................
LIMSRDIS ...........................
LIMZCDIS............................
LMAX[2:0]............................
CUSH[2:0] ...........................
LIMARATE[7:0]....................
LIMRRATE[7:0] ...................
“HP/Speaker De-Emphasis” on page 44
“PCM Channel x Mute” on page 47
“PCM Channel x Volume” on page 47
“Invert PCM Signal Polarity” on page 43
“PCM Channel Swap” on page 52
“Master Volume Control” on page 51
“Master Playback Mute” on page 43
“Digital Soft Ramp” on page 44
“Digital Zero Cross” on page 45
“Playback Volume Setting B=A” on page 43
“Tone Control Enable” on page 50
“Bass Corner Frequency” on page 50
“Treble Corner Frequency” on page 50
“Bass Gain” on page 51
“Treble Gain” on page 50
“Peak Detect and Limiter” on page 54
“Limiter Soft Ramp Disable” on page 53
“Limiter Zero Cross Disable” on page 54
“Limiter Maximum Threshold” on page 53
“Limiter Cushion Threshold” on page 53
“Limiter Attack Rate” on page 55
“Limiter Release Rate” on page 54
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4.2.1
CS43L22
Beep Generator
The Beep Generator generates audio frequencies across approximately two octave major scales. It offers
three modes of operation: Continuous, multiple and single (one-shot) beeps. Sixteen on and eight off
times are available.
Note: The Beep is generated before the limiter and may affect desired limiting performance. If the limiter function is used, it may be required to set the beep volume sufficiently below the threshold to prevent
the peak detect from triggering. Since the master volume control, MSTxVOL[7:0], will affect the beep volume, DAC volume may alternatively be controlled using the PCMxVOL[6:0] bits.
BEEP[1:0] =
'11'
CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains on
until BEEP is cleared.
BEEP[1:0] =
'10'
MULTI-BEEP: Beep turns on at a configurable frequency (FREQ)
and volume (BPVOL) for the duration of ONTIME and turns off for
the duration of OFFTIME. On and off cycles are repeated until
BEEP is cleared.
BEEP[1:0] =
'01'
SINGLE-BEEP: Beep turns on at a
configurable frequency (FREQ) and
volume (BPVOL) for the duration of
ONTIME. BEEP must be cleared
and set for additional beeps.
...
BPVOL[4:0]
FREQ[3:0]
ONTIME[3:0]
OFFTIME[2:0]
Figure 6. Beep Configuration Options
4.2.2
Referenced Control
Register Location
MSTxVOL[7:0].....................
PCMxVOL[6:0] ....................
OFFTIME[2:0] .....................
ONTIME[3:0] .......................
FREQ[3:0] ...........................
BEEP[1:0]............................
BEEPMIXDIS ......................
BPVOL[4:0] .........................
“Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)” on page 51
“PCMx Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh)” on page 47
“Beep Off Time” on page 48
“Beep On Time” on page 48
“Beep Frequency” on page 47
“Beep Configuration” on page 49
“Beep Mix Disable” on page 49
“Beep Volume” on page 49
Limiter
When enabled, the limiter monitors the digital input signal before the DAC and PWM modulators, detects
when levels exceed the maximum threshold settings and lowers the master volume at a programmable
attack rate below the maximum threshold. When the input signal level falls below the maximum threshold,
the AOUT volume returns to its original level set in the Master Volume Control register at a programmable
release rate. Attack and release rates are affected by the DAC soft ramp/zero cross settings and sample
rate, Fs. Limiter soft ramp and zero cross dependency may be independently enabled/disabled.
Notes:
1. Recommended settings: Best limiting performance may be realized with the fastest attack and
slowest release setting with soft ramp enabled in the control registers. The MIN bits allow the user to
set a threshold slightly below the maximum threshold for hysteresis control - this cushions the sound
as the limiter attacks and releases.
2. The Limiter maintains the output signal between the CUSH and MAX thresholds. As the digital input
signal level changes, the level-controlled output may not always be the same but will always fall within
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CS43L22
the thresholds.
Referenced Control
Register Location
Limiter Controls ................... “Limiter Control 2, Release Rate (Address 28h)” on page 54, “Limiter Attack Rate (Address 29h)” on page 55
Master Volume Control........ “Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)” on page 51
In p u t
M A X [2 :0 ]
L im ite r
A T T A C K /R E L E A S E S O U N D
C U S H IO N
V o lu m e
O u tp u t
(a fte r L im ite r)
C U S H [2 :0 ]
M A X [2 :0 ]
A R A T E [5 :0 ]
R R A T E [5 :0 ]
Figure 7. Peak Detect & Limiter
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4.3
CS43L22
Analog Passthrough
The CS43L22 accommodates analog routing of the analog input signal directly to the headphone amplifiers
by using the PASSTHRUx mux. This feature is useful in applications that utilize an FM tuner where audio
recovered over-the-air must be transmitted to the headphone amplifier directly. This analog passthrough
path reduces power consumption and is immune to modulator switching noise that could interfere with some
tuners.
Four analog input channels can be chosen or summed by using the PASSxSEL bits as shown in Figure 8
to provide input to the CS43L22 when in analog passthrough mode. A pair of passthrough amplifiers can be
used to mute and apply gain to the input signals.
PASSASEL[4:1]
ANLGSFTA
ANLGGZCA
PASSB=A
PASSAMUTE
PASSAVOL[7:0]
+12dB/-60dB
0.5 dB steps
PASSTHRUA
DAC A
Output
AIN1A
AIN2A
AIN3A
AIN4A
Σ
Analog Passthru
Amplifiers
AIN4B
AIN3B
AIN2B
AIN1B
ANALOG PASS
THRU TO
HEADPHONE
AMPLIFIER MUX
Σ
PASSBSEL[4:1]
ANLGSFTB
ANLGGZCB
PASSB=A
PASSBMUTE
PASSBVOL[7:0]
+12dB/-60dB
0.5 dB steps
DAC B
Output
PASSTHRUB
Figure 8. Analog Passthrough Signal Flow
Referenced Control
Register Location
Analog Front End
PASSB=A ............................
ANLGSFTx ..........................
ANLGZCx ............................
PASSxSEL4,3,2,1 ................
PASSxMUTE .......................
PASSxVOL[7:0] ...................
PASSTHRUx........................
“Passthrough Channel B=A Gang Control” on page 42
“Ch. x Analog Soft Ramp” on page 42
“Ch. x Analog Zero Cross” on page 42
“Passthrough Input Channel Mapping” on page 42
“Passthrough Mute” on page 44
“Passthrough x Volume” on page 46
“Passthrough Analog” on page 44
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4.4
CS43L22
Analog Outputs
PDN_HPA[1:0]
PDN_HPB[1:0]
HPAMUTE
HPBMUTE
HPA_VOL[7:0]
HPB_VOL[7:0]
+0dB/-102dB
0.5dB steps
from DSP
Engine
HPGAIN[2:0]
A
DAC
VOL
HP/Line
Outputs
B
Analog Passthru Input
Signal
Charge
Pump
VOL
PASSTHRUA
PASSTHRUB
PASSAMUTE
PASSBMUTE
PASSAVOL[7:0]
PASSBVOL[70]
+12dB/-60dB
0.5dB steps
CHGFREQ[3:0]
Figure 9. Analog Outputs
Referenced Control
Register Location
Analog Output
HPxMUTE ...........................
HPxVOL[7:0] .......................
PDN_HPx[1:0] .....................
HPGAIN[2:0]........................
PASSTHRUx .......................
PASSxMUTE .......................
PASSxVOL[7:0] ...................
CHGFREQ ..........................
“Headphone Mute” on page 45
“Headphone Volume Control” on page 51
“Headphone Power Control” on page 38
“Headphone Analog Gain” on page 43
“Passthrough Analog” on page 44
“Passthrough Mute” on page 44
“Passthrough x Volume” on page 46
“Charge Pump Frequency” on page 58
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4.5
CS43L22
PWM Outputs
Note:
The PWM speaker amplifiers should not be used in the 384x MCLK modes (18.4320 and
16.9344 MHz).
SPKAMUTE
SPKBMUTE
MUTE50/50
SPKMONO
SPKSWAP
SPKB=A
SPKAVOL[7:0]
SPKBVOL[7:0]
+0dB/-102dB
0.5dB steps
from DSP
Engine
BATTCMP
VPREF[3:0]
VPLVL[7:0]
Battery
Compensation
PWM
Modulator
VOL
+ A
+ B
-
Gate
Drive
Speaker
Outputs
PDN_SPKA[1:0]
PDN_SPKB[1:0]
Short
Circuit
SPKASHRT
SPKBSHRT
Figure 10. PWM Output Stage
Referenced Control
Register Location
PWM Control
SPKxMUTE .........................
MUTE50/50 .........................
SPKMONO ..........................
SPKxVOL[7:0] .....................
SPKSWAP...........................
SPKB=A ..............................
BATTCMP ...........................
VPREF[3:0] .........................
VPLVL[7:0] ..........................
PDN_SPKx[1:0]...................
SPKxSHRT..........................
“Speaker Mute” on page 45
“Speaker Mute 50/50 Control” on page 46
“Speaker MONO Control” on page 46
“Speaker Volume Control” on page 52
“Speaker Channel Swap” on page 45
“Speaker Volume Setting B=A” on page 45
“Battery Compensation” on page 56
“VP Reference” on page 57
“VP Voltage Level (Read Only)” on page 57
“Speaker Power Control” on page 38
“Speaker Current Load Status (Read Only)” on page 57
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4.5.1
CS43L22
Mono Speaker Output Configuration
The CS43L22 accommodates a stereo as well as a mono speaker output configuration. In mono mode
the output drivers of each channel are connected in parallel to deliver maximum power to a 4 ohm speaker. Refer to the table below for pin mapping in mono configuration.
Speaker Output
SPKMONO=0
SPKMONO=1
SPKSWAP=0
SPKSWAP=1
SPKSWAP=0
SPKSWAP=1
SPKOUTA+
SPKOUTB+
SPKOUTA+
SPKOUTB+
SPKOUTASPKOUTBSPKOUTA+
SPKOUTB+
SPKOUTB+
SPKOUTA+
SPKOUTASPKOUTBSPKOUTBSPKOUTASPKOUTASPKOUTB-
Pin
4
6
7
9
Referenced Control
Register Location
SPKMONO.......................... “Speaker MONO Control” on page 46
SPKSWAP........................... “Speaker Channel Swap” on page 45
4.5.2
VP Battery Compensation
The CS43L22 provides the option to maintain a desired power output level, independent of the VP supply.
When enabled, this feature works by monitoring the voltage on the VP supply and reducing the attenuation on the speaker outputs when VP voltage levels fall.
Note: The internal ADC that monitors the VP supply operates from the VA supply. Calculations are based
on typical VA levels of 1.8 V and 2.5 V using the VPREF bits.
4.5.2.1
Maintaining a Desired Output Level
Using SPKxVOL, the speaker output level must first be attenuated by the decibel equivalent of the expected VP supply range (MAX relative to MIN). The CS43L22 then gradually reduces the attenuation as the
VP supply drops from its maximum level, maintaining a nearly constant power output.
Compensation Example 1 (VP Battery supply ranges from 4.5 V to 3.0 V)
1. Set speaker attenuation (SPKxVOL) to -3.5 dB. The VP supply changes ~3.5 dB.
2. Set the reference VP supply (VPREF) to 4.5 V.
3. Enable battery compensation (BATTCMP).
The CS43L22 automatically adjusts the output level as the battery discharges.
Compensation Example 2 (VP Battery supply ranges from 5.0 V to 1.6 V)
1. Set speaker attenuation (SPKxVOL) to -10 dB. The VP supply changes ~9.9 dB.
2. Set the reference VP supply (VPREF) to 5.0 V.
3. Enable battery compensation (BATTCMP).
The CS43L22 automatically adjusts the output level as the battery discharges. Refer to Figure 11 on
page 28. In this example, the VP supply changes over a wide range, illustrating the accuracy of the
CS43L22’s battery compensation.
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CS43L22
-6
Battery Compensated
PWM Output Level
PWM Output Level (dB)
-8
-10
-12
Uncompensated
PWM Output
Level
-14
-16
-18
-20
-22
-24
4.9
4.6
4.3
4
3.7
3.4
3.1
2.8
2.5
2.2
1.9
1.6
VP Supply (V)
Figure 11. Battery Compensation
28
Referenced Control
Register Location
VPREF ................................
SPKxVOL ............................
“VP Reference” on page 57
“Speaker Volume Control” on page 52
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4.6
CS43L22
Serial Port Clocking
The CS43L22 serial audio interface port operates either as a slave or master, determined by the M/S bit. It
accepts externally generated clocks in Slave Mode and will generate synchronous clocks derived from an
input master clock (MCLK) in Master Mode. Refer to the tables below for the required setting in register 05h
and 06h associated with a given MCLK and sample rate.
Referenced Control
Register Location
M/S................................... “Master/Slave Mode” on page 40
Register 05h...................... “Clocking Control (Address 05h)” on page 38
Register 06h...................... “Interface Control 1 (Address 06h)” on page 40
MCLK
(MHz)
12.2880
11.2896
18.4320
(Slave
Mode
ONLY)
16.9344
(Slave
Mode
ONLY)
12.0000
24.0000
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Sample Rate,
Fs (kHz)
8.0000
12.0000
16.0000
24.0000
32.0000
48.0000
96.0000
11.0250
22.0500
44.1000
88.2000
8.0000
12.0000
16.0000
24.0000
32.0000
48.0000
96.0000
*8.0182...
11.0250
22.0500
44.1000
88.2000
8.0000
*11.0294...
12.0000
16.0000
*22.0588...
24.0000
32.0000
*44.1176...
48.0000
*88.2353...
96.0000
8.0000
*11.0294...
12.0000
16.0000
*22.0588...
24.0000
32.0000
*44.1176...
48.0000
*88.2353...
96.0000
SPEED[1:0]
(AUTO=’0’b)
11
11
10
10
01
01
00
11
10
01
00
11
11
10
10
01
01
00
11
11
10
01
00
11
11
11
10
10
10
01
01
01
00
00
11
11
11
10
10
10
01
01
01
00
00
32kGROUP
VIDEOCLK
RATIO[1:0]
MCLKDIV2
1
0
1
0
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
10
00
00
00
00
01
11
01
01
11
01
01
11
01
11
01
01
11
01
01
11
01
01
11
01
11
01
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
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MCLK
(MHz)
Sample Rate,
Fs (kHz)
8.0000
12.0000
24.0000
32.0000
*44.1176...
48.0000
*11.0294...
*22.0588...
16.0000
27.0000
Note:
SPEED[1:0]
(AUTO=’0’b)
11
11
10
01
01
01
11
10
10
CS43L22
32kGROUP
VIDEOCLK
RATIO[1:0]
MCLKDIV2
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
01
01
01
01
11
01
11
11
01
0
0
0
0
0
0
0
0
0
*The marked sample rate values are not exact representations of the actual frame clock frequency
They have been truncated to 4 decimal places. The exact value can be calculated by dividing the
MCLK being used by the desired MCLK/LRCK ratio.
Table 1. Serial Port Clocking
4.7
Digital Interface Formats
The serial port operates in standard I²S, Left-Justified, Right-Justified, or DSP Mode digital interface formats
with varying bit depths from 16 to 24. Data is clocked into the DAC on the rising edge of SCLK.
LRCK
L e ft C h a n n e l
R ig ht C h a n n el
SCLK
MSB
SDIN
M SB
LSB
MSB
LS B
AOUTA
AOUTB
Figure 12. I²S Format
Left Channel
LRCK
Right Channel
SCLK
MSB
LSB
MSB
LSB
SDIN
MSB
AOUTB
AOUTA
Figure 13. Left-Justified Format
LRCK
L e ft C h a n n e l
R ig h t C h a n n e l
SCLK
SDIN
MSB
LSB
AO UTA
MSB
LS B
AO UTB
Audio W ord Length (AW L)
Figure 14. Right-Justified Format\
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4.7.1
CS43L22
DSP Mode
In DSP Mode, the LRCK acts as a frame sync for 2 data-packed words (left and right channel) input on
SDIN. The MSB is input on the first SCLK rising edge after the frame sync rising edge. The right channel
immediately follows the left channel.
1/fs
LRCK
SCLK
SDIN
L SB MSB
L eft C h a n n el
LS B M SB
HP/LINE OUTA
R ig ht C h a n n el
LSB M SB
HP/LINE OUTB
Audio Word Length (AWL)
Figure 15. DSP Mode Format)
4.8
Initialization
The CS43L22 enters a Power-Down state upon initial power-up. The interpolation and decimation filters,
delta-sigma and PWM modulators and control port registers are reset. The internal voltage reference, and
switched-capacitor low-pass filters are powered down.
The device will remain in the Power-Down state until the RESET pin is brought high. The control port is accessible once RESET is high and the desired register settings can be loaded per the interface descriptions
in the “Register Description” on page 37.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+, will begin powering up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then
applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the
MCLK/LRCK frequency ratio and normal operation begins.
4.9
Recommended Power-Up Sequence
1. Hold RESET low until the power supplies are stable.
2. Bring RESET high.
3. The default state of the “Power Ctl. 1” register (0x02) is 0x01. Load the desired register settings while
keeping the “Power Ctl 1” register set to 0x01.
4. Load the required initialization settings listed in Section 4.11.
5. Apply MCLK at the appropriate frequency, as discussed in Section 4.6. SCLK may be applied or set to
master at any time; LRCK may only be applied or set to master while the PDN bit is set to 1.
6. Set the “Power Ctl 1” register (0x02) to 0x9E.
7. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
4.10
Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the DAC in standby,
1. Mute the DAC’s and PWM outputs.
2. Disable soft ramp and zero cross volume transitions.
3. Set the “Power Ctl 1” register (0x02) to 0x9F.
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4. Wait at least 100 µs.
The device will be fully powered down after this 100 µs delay. Prior to the removal of the master clock
(MCLK), this delay of at least 100 µs must be implemented after step 3 to avoid premature disruption
of the DAC’s power down sequence.
A disruption in the device’s power down sequence (i.e. removing the MCLK signal before this 100 µs
delay) has consequences on both the headphone and PWM speaker amplifiers: The charge pump may
stop abruptly, causing the headphone amplifiers to drive the outputs up to the +VHP supply. Also, the
last state of each ‘+’ and ‘-’ PWM output terminal before the premature removal of MCLK could randomly
be held at either VP or AGND. When this event occurs, it is possible for each PWM terminal to output
opposing potentials, creating a DC source into the speaker voice coil.
The disruption of the device’s power down sequence may also cause clicks and pops on the output of
the DAC’s as the modulator holds the last output level before the MCLK signal was removed.
5. MCLK may be removed at this time.
6. To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be
reset to their default state.
4.11
Required Initialization Settings
Various sections in the device must be adjusted by implementing the initialization settings shown below after
power-up sequence step 3. All performance and power consumption measurements were taken with the
following settings:
1. Write 0x99 to register 0x00.
2. Write 0x80 to register 0x47.
3. Write ‘1’b to bit 7 in register 0x32.
4. Write ‘0’b to bit 7 in register 0x32.
5. Write 0x00 to register 0x00.
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5. CONTROL PORT OPERATION
The control port is used to access the registers allowing the CS43L22 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins
should remain static if no operation is required.
The control port operates using an I²C interface with the CS43L22 acting as a slave device.
5.1
I²C Control
SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL. The AD0 pin
sets the LSB of the chip address; ‘0’ when connected to DGND, ‘1’ when connected to VL. This pin may be
driven by a host controller or directly connected to VL or DGND. The AD0 pin state is sensed and the LSB
of the chip address is set upon the release of the RESET signal (a low-to-high transition).
The signal timings for a read and write cycle are shown in Figure 16 and Figure 17. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is defined as a rising transition
of SDA while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent
to the CS43L22 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read,
low for a write).
The upper 6 bits of the address field are fixed at 100101. To communicate with the CS43L22, the chip address field, which is the first byte sent to the CS43L22, should match 100101 followed by the setting of the
AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory
Address Pointer (MAP), which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK
bit is output from the CS43L22 after each input byte is read and is input to the CS43L22 from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
24 25 26 27 28
19
SCL
CHIP ADDRESS (WRITE)
1
SDA
0
0
1
0
1
AD0
MAP BYTE
0
6
INCR
5
4
3
2
1
0
7
ACK
6
1
ACK
DATA +n
DATA +1
DATA
0
7
6
1
0
7
6
1
0
ACK
ACK
STOP
START
Figure 16. Control Port Timing, I²C Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
1
0
0
1
0 1 AD0 0
INCR
ACK
START
STOP
MAP BYTE
6
5
4
3
2
1
CHIP ADDRESS (READ)
1
0
0
0
1
0
DATA
1 AD0 1
ACK
START
7
ACK
DATA +1
0
7
ACK
0
DATA + n
7
0
NO
ACK
STOP
Figure 17. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 17, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
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Send start condition.
Send 10010100 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto-increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10010101 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
5.1.1
Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudo code above for implementation details.
5.1.1.1
Map Increment (INCR)
The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads. If INCR is set to 1, MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.
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6. REGISTER QUICK REFERENCE
Default values are shown below the bit names. Unless otherwise specified, all “Reserved” bits must maintain their
default value.
Adr.
01h
p 37
02h
p 37
03h
Function
ID
7
CHIPID4
1
Power Ctl 1
PDN7
0
Reserved
Reserved
0
04h Power Ctl 2
PDN_HPB1
p 38
0
05h Clocking Ctl
AUTO
p 38
1
06h Interface Ctl 1
M/S
p 40
0
07h Interface Ctl 2
Reserved
p 41
0
08h Passthrough A
Reserved
p 42 Select
1
09h Passthrough B
Reserved
p 42 Select
1
0Ah Analog ZC and
Reserved
p 42 SR Settings
1
0Bh Reserved
Reserved
0
0Ch Passthrough
PASSB=A
p 42 Gang Control
0
0Dh Playback Ctl 1
HPGAIN2
p 43
0
0Eh Misc. Ctl
PASSTHRUB
p 44
0
0Fh Playback Ctl 2
HPBMUTE
p 45
0
10h- Reserved
Reserved
13h
0
14h Passthrough A PASSAVOL7
p 46 Vol
0
15h Passthrough B PASSBVOL7
p 46 Vol
0
16h- Reserved
Reserved
17h
0
18h- Reserved
Reserved
19h
1
1Ah PCMA Vol
PCMAMUTE
p 47
0
1Bh PCMB Vol
PCMBMUTE
p 47
0
1Ch BEEP Freq,
FREQ3
p 47 On Time
0
1Dh BEEP Vol,
OFFTIME2
p 48 Off Time
0
1Eh BEEP,
BEEP1
p 49 Tone Cfg.
0
1Fh Tone Ctl
TREB3
p 50
1
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6
CHIPID3
1
PDN6
0
Reserved
0
PDN_HPB0
0
SPEED1
0
INV_SCLK
0
SCLK=MCLK
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
HPGAIN1
1
PASSTHRUA
0
HPAMUTE
0
Reserved
0
PASSAVOL6
0
PASSBVOL6
0
Reserved
0
Reserved
0
PCMAVOL6
0
PCMBVOL6
0
FREQ2
0
OFFTIME1
0
BEEP0
0
TREB2
0
5
CHIPID2
1
PDN5
0
Reserved
0
PDN_HPA1
0
SPEED0
1
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
1
Reserved
0
Reserved
0
HPGAIN0
1
PASSBMUTE
0
SPKBMUTE
0
Reserved
0
PASSAVOL5
0
PASSBVOL5
0
Reserved
0
Reserved
0
PCMAVOL5
0
PCMBVOL5
0
FREQ1
0
OFFTIME0
0
BEEPMIXDIS
0
TREB1
0
4
CHIPID1
0
PDN4
0
Reserved
0
PDN_HPA0
0
32kGROUP
0
DSP
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
PLYBCKB=A
0
PASSAMUTE
0
SPKAMUTE
0
Reserved
0
PASSAVOL4
0
PASSBVOL4
0
Reserved
0
Reserved
0
PCMAVOL4
0
PCMBVOL4
0
FREQ0
0
BPVOL4
0
TREB_CF1
0
TREB0
0
3
CHIPID0
0
PDN3
0
Reserved
0
PDN_SPKB1
0
VIDEOCLK
0
DACDIF1
0
INV_SWCH
0
PASSASEL4
0
PASSBSEL4
0
ANLGSFTB
0
Reserved
0
Reserved
0
INV_PCMB
0
FREEZE
0
SPKB=A
0
Reserved
0
PASSAVOL3
0
PASSBVOL3
0
Reserved
0
Reserved
0
PCMAVOL3
0
PCMBVOL3
0
ONTIME3
0
BPVOL3
0
TREB_CF0
0
BASS3
1
2
REVID2
x
PDN2
0
Reserved
1
PDN_SPKB0
1
RATIO1
0
DACDIF0
0
Reserved
0
PASSASEL3
0
PASSBSEL3
0
ANLGZCB
1
Reserved
0
Reserved
0
INV_PCMA
0
DEEMPH
0
SPKSWAP
Reserved
0
PASSAVOL2
0
PASSBVOL2
0
Reserved
0
Reserved
0
PCMAVOL2
0
PCMBVOL2
0
ONTIME2
0
BPVOL2
0
BASS_CF1
0
BASS2
0
1
REVID1
x
PDN1
0
Reserved
1
PDN_SPKA1
0
RATIO0
0
AWL1
0
Reserved
0
PASSASEL2
0
PASSBSEL2
0
ANLGSFTA
0
Reserved
0
Reserved
0
MSTBMUTE
0
DIGSFT
1
SPKMONO
0
Reserved
0
PASSAVOL1
0
PASSBVOL1
0
Reserved
0
Reserved
0
PCMAVOL1
0
PCMBVOL1
0
ONTIME1
0
BPVOL1
0
BASS_CF0
0
BASS1
0
0
REVID0
x
PDN0
1
Reserved
1
PDN_SPKA0
1
MCLKDIV2
0
AWL0
0
Reserved
0
PASSASEL1
1
PASSBSEL1
1
ANLGZCA
1
Reserved
0
Reserved
0
MSTAMUTE
0
DIGZC
0
MUTE50/50
0
Reserved
0
PASSAVOL0
0
PASSBVOL0
0
Reserved
0
Reserved
0
PCMAVOL0
0
PCMBVOL0
0
ONTIME0
0
BPVOL0
0
TC_EN
0
BASS0
0
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Adr.
20h
p 51
21h
p 51
22h
p 51
23h
p 51
24h
p 52
25h
p 52
26h
p 52
27h
p 53
28h
p 54
29h
p 55
2Ah
Function
Master A Vol
Master B Vol
Headphone A
Volume
Headphone B
Volume
Speaker A
Volume
Speaker B
Volume
Channel Mixer
& Swap
Limit Ctl 1,
Thresholds
Limit Ctl 2,
Release Rate
Limiter Attack
Rate
Reserved
2Bh Reserved
2Ch2Dh
2Eh
p 55
2Fh
p 56
30h
p 57
31h
p 57
32h
Reserved
Overflow &
Clock Status
Battery Compensation
VP Battery
Level
Speaker Status
Reserved
33h Reserved
34h Charge Pump
p 58 Frequency
36
7
6
5
MSTAVOL7 MSTAVOL6 MSTAVOL5
0
0
0
MSTBVOL7 MSTBVOL6 MSTBVOL5
0
0
0
HPAVOL7
HPAVOL6
HPAVOL5
0
0
0
HPBVOL7
HPBVOL6
HPBVOL5
0
0
0
SPKAVOL7 SPKAVOL6 SPKAVOL5
0
0
0
SPKBVOL7 SPKBVOL6 SPKBVOL5
0
0
0
PCMASWP1 PCMASWP0 PCMBSWP1
0
0
0
LMAX2
LMAX1
LMAX0
0
0
0
LIMIT
LIMIT_ALL LIMRRATE5
0
1
1
Reserved
Reserved
LIMARATE5
0
0
0
Reserved
Reserved
Reserved
0
0
0
Reserved
Reserved
Reserved
0
0
1
Reserved
Reserved
Reserved
0
0
0
Reserved
SPCLKERR DSPBOVFL
0
0
0
BATTCMP VPMONITOR Reserved
0
0
0
VPLVL7
VPLVL6
VPLVL5
0
0
0
Reserved
Reserved
SPKASHRT
0
0
0
Reserved
Reserved
Reserved
0
0
1
Reserved
Reserved
Reserved
0
0
0
CHGFREQ3 CHGFREQ2 CHGFREQ1
0
1
0
CS43L22
4
3
2
1
MSTAVOL4 MSTAVOL3 MSTAVOL2 MSTAVOL1
0
0
0
0
MSTBVOL4 MSTBVOL3 MSTBVOL2 MSTBVOL1
0
0
0
0
HPAVOL4
HPAVOL3
HPAVOL2
HPAVOL1
0
0
0
0
HPBVOL4
HPBVOL3
HPBVOL2
HPBVOL1
0
0
0
0
SPKAVOL4 SPKAVOL3 SPKAVOL2 SPKAVOL1
0
0
0
0
SPKBVOL4 SPKBVOL3 SPKBVOL2 SPKBVOL1
0
0
0
0
PCMBSWP0
Reserved
Reserved
Reserved
0
0
0
0
CUSH2
CUSH1
CUSH0
LIMSRDIS
0
0
0
0
LIMRRATE4 LIMRRATE3 LIMRRATE2 LIMRRATE1
1
1
1
1
LIMARATE4 LIMARATE3 LIMARATE2 LIMARATE1
0
0
0
0
Reserved
Reserved
Reserved
Reserved
0
0
0
0
Reserved
Reserved
Reserved
Reserved
1
1
1
1
Reserved
Reserved
Reserved
Reserved
0
0
0
0
DSPAOVFL PCMAOVFL PCMBOVFL
Reserved
0
0
0
0
Reserved
VPREF3
VPREF2
VPREF1
0
0
0
0
VPLVL4
VPLVL3
VPLVL2
VPLVL1
0
0
0
0
SPKBSHRT
SPKR/HP
Reserved
Reserved
0
0
0
0
Reserved
Reserved
Reserved
Reserved
1
1
0
1
Reserved
Reserved
Reserved
Reserved
0
0
0
0
CHGFREQ0
Reserved
Reserved
Reserved
1
1
1
1
0
MSTAVOL0
0
MSTBVOL0
0
HPAVOL0
0
HPBVOL0
0
SPKAVOL0
0
SPKBVOL0
0
Reserved
0
LIMZCDIS
0
LIMRRATE0
1
LIMARATE0
0
Reserved
0
Reserved
1
Reserved
0
Reserved
0
VPREF0
0
VPLVL0
0
Reserved
0
Reserved
1
Reserved
0
Reserved
1
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CS43L22
7. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are
read only. See the following bit definition tables for bit assignment information. The default state of each bit after a
power-up sequence or reset is shown as shaded in the table. Unless otherwise specified, all “Reserved” bits must
maintain their default value.
7.1
Chip I.D. and Revision Register (Address 01h) (Read Only)
7
CHIPID4
7.1.1
6
CHIPID3
5
CHIPID2
4
CHIPID1
3
CHIPID0
2
REVID2
1
REVID1
0
REVID0
3
PDN3
2
PDN2
1
PDN1
0
PDN0
Chip I.D. (Read Only)
I.D. code for the CS43L22.
7.1.2
CHIPID[4:0]
Device
11100
CS43L22
Chip Revision (Read Only)
CS43L22 revision level.
7.2
REVID[2:0]
Revision Level
000
A0
001
A1
010
B0
011
B1
Power Control 1 (Address 02h)
7
PDN7
7.2.1
6
PDN6
5
PDN5
4
PDN4
Power Down
Configures the power state of the CS43L22.
PDN[7:0]
Status
0000 0001
Powered Down - same as setting 1001 1111
1001 1110
Powered Up
1001 1111
Powered Down - same as setting 0000 0001
Note:
1. All states of PDN[7:0] not shown in the table are reserved.
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7.3
CS43L22
Power Control 2 (Address 04h)
7
PDN_HPB1
7.3.1
6
PDN_HPB0
5
PDN_HPA1
4
PDN_HPA0
3
PDN_SPKB1
2
PDN_SPKB0
1
PDN_SPKA1
0
PDN_SPKA0
Headphone Power Control
Configures how the SPK/HP_SW pin, 6, controls the power for the headphone amplifier.
7.3.2
PDN_HPx[1:0]
Headphone Status
00
Headphone channel is ON when the SPK/HP_SW pin, 6, is LO.
Headphone channel is OFF when the SPK/HP_SW pin, 6, is HI.
01
Headphone channel is ON when the SPK/HP_SW pin, 6, is HI.
Headphone channel is OFF when the SPK/HP_SW pin, 6, is LO.
10
Headphone channel is always ON.
11
Headphone channel is always OFF.
Speaker Power Control
Configures how the SPK/HP_SW pin, 6, controls the power for the speaker amplifier.
7.4
PDN_SPKx[1:0]
Speaker Status
00
Speaker channel is ON when the SPK/HP_SW pin, 6, is LO.
Speaker channel is OFF when the SPK/HP_SW pin, 6, is HI.
01
Speaker channel is ON when the SPK/HP_SW pin, 6, is HI.
Speaker channel is OFF when the SPK/HP_SW pin, 6, is LO.
10
Speaker channel is always ON.
11
Speaker channel is always OFF.
Clocking Control (Address 05h)
7
AUTO
7.4.1
6
SPEED1
5
SPEED0
4
32k_GROUP
3
VIDEOCLK
2
RATIO1
1
RATIO0
0
MCLKDIV2
Auto-Detect
Configures the auto-detect circuitry for detecting the speed mode of the CS43L22 when operating as a
slave.
AUTO
Auto-detection of Speed Mode
0
Disabled
1
Enabled
Application:
“Serial Port Clocking” on page 29
Notes:
1. The SPEED[1:0] bits are ignored and speed is determined by the MCLK/LRCK ratio.
2. When AUTO is disabled and the CS43L22 operates in Master Mode, the MCLKDIV2 bit is ignored.
3. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
(“32kHz Sample Rate Group” on page 39) and/or the VIDEOCLK bit (“27 MHz Video Clock” on
page 39) and RATIO[1:0] bits (“Internal MCLK/LRCK Ratio” on page 39). Low sample rates may also
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
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7.4.2
CS43L22
Speed Mode
Configures the speed mode of the DAC in Slave Mode and sets the appropriate MCLK divide ratio for
LRCK and SCLK in Master Mode.
SPEED[1:0]
Slave Mode
Master Mode
Serial Port Speed
MCLK/LRCK Ratio
SCLK/LRCK Ratio
00
Double-Speed Mode (DSM - 50 kHz -100 kHz Fs)
512
64
01
Single-Speed Mode (SSM - 4 kHz -50 kHz Fs)
256
64
10
Half-Speed Mode (HSM - 12.5kHz -25 kHz Fs)
128
64
11
Quarter-Speed Mode (QSM - 4 kHz -12.5 kHz Fs)
128
64
Application:
“Serial Port Clocking” on page 29
Notes:
1. Slave/Master Mode is determined by the M/S bit in “Master/Slave Mode” on page 40.
2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
(“32kHz Sample Rate Group” on page 39) and/or the VIDEOCLK bit (“27 MHz Video Clock” on
page 39) and RATIO[1:0] bits (“Internal MCLK/LRCK Ratio” on page 39). Low sample rates may also
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
3. These bits are ignored when the AUTO bit (“Auto-Detect” on page 38) is enabled.
7.4.3
32kHz Sample Rate Group
Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.
32kGROUP
7.4.4
8 kHz, 16 kHz or 32 kHz sample rate?
0
No
1
Yes
Application:
“Serial Port Clocking” on page 29
27 MHz Video Clock
Specifies whether or not the external MCLK frequency is 27 MHz
VIDEOCLK
7.4.5
27 MHz MCLK?
0
No
1
Yes
Application:
“Serial Port Clocking” on page 29
Internal MCLK/LRCK Ratio
Configures the internal MCLK/LRCK ratio.
RATIO[1:0]
DS792F2
Internal MCLK Cycles per LRCK
SCLK/LRCK Ratio in Master Mode
00
128
64
01
125
62
10
132
66
11
136
68
Application:
“Serial Port Clocking” on page 29
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7.4.6
CS43L22
MCLK Divide By 2
Divides the input MCLK by 2 prior to all internal circuitry.
MCLKDIV2
No divide
1
Divided by 2
Application:
“Serial Port Clocking” on page 29
Note:
7.5
MCLK signal into DAC
0
In Slave Mode, this bit is ignored when the AUTO bit (“Auto-Detect” on page 38) is disabled.
Interface Control 1 (Address 06h)
7
M/S
7.5.1
6
INV_SCLK
5
Reserved
4
DSP
3
DACDIF1
2
DACDIF0
1
AWL1
0
AWL0
Master/Slave Mode
Configures the serial port I/O clocking.
M/S
7.5.2
Serial Port Clocks
0
Slave (input ONLY)
1
Master (output ONLY)
SCLK Polarity
Configures the polarity of the SCLK signal.
INV_SCLK
7.5.3
SCLK Polarity
0
Not Inverted
1
Inverted
DSP Mode
Configures a data-packed interface format for the DAC.
DSP
DSP Mode
0
Disabled
1
Enabled
Application:
“DSP Mode” on page 31
Notes:
1. Select the audio word length using the AWL[1:0] bits (“Audio Word Length” on page 41).
2. The interface format for the DAC must be set to “Left-Justified” when DSP Mode is enabled.
7.5.4
DAC Interface Format
Configures the digital interface format for data on SDIN.
DACDIF[1:0]
DAC Interface Format
00
Left Justified, up to 24-bit data
01
I²S, up to 24-bit data
10
Right Justified
11
Reserved
Application:
“Digital Interface Formats” on page 30
Note: Select the audio word length for Right Justified using the AWL[1:0] bits (“Audio Word Length” on
page 41).
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7.5.5
CS43L22
Audio Word Length
Configures the audio sample word length used for the data into SDIN.
Audio Word Length
AWL[1:0]
DSP Mode
Right Justified
00
32-bit data
24-bit data
01
24-bit data
20-bit data
10
20-bit data
18-bit data
11
16-bit data
16-bit data
Application:
“DSP Mode” on page 31
Note: When the internal MCLK/LRCK ratio is set to 125 in Master Mode, the 32-bit data width option
for DSP Mode is not valid unless SCLK=MCLK.
7.6
Interface Control 2 (Address 07h)
7
Reserved
7.6.1
6
SCLK=MCLK
5
Reserved
4
Reserved
3
INV_SWCH
2
Reserved
1
Reserved
0
Reserved
SCLK equals MCLK
Configures the SCLK signal source for Master Mode.
SCLK=MCLK
0
Re-timed signal, synchronously derived from MCLK
1
Non-retimed, MCLK signal
Note:
7.6.2
Output SCLK
This bit is only valid for MCLK = 12.0000 MHz.
Speaker/Headphone Switch Invert
Determines the control signal polarity of the SPK/HP_SW pin.
DS792F2
INV_SWCH
SPK/HP_SW pin 6 Control
0
Not inverted
1
Inverted
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7.7
Passthrough x Select: PassA (Address 08h), PassB (Address 09h)
7
Reserved
7.7.1
CS43L22
6
Reserved
5
Reserved
4
Reserved
3
2
1
0
PASSASEL4 PASSASEL3 PASSASEL2 PASSASEL1
Passthrough Input Channel Mapping
Selects one or sums/mixes the analog input signal into the passthrough Amplifier. Each bit of the
PASSx_SEL[4:1] word corresponds to individual channels (i.e. PASSx_SEL1 selects AIN1x,
PASSx_SEL2 selects AIN2x, etc.).
PASSxSEL[4:1]
Selected Input to Passthrough Channel x
00000
No inputs selected
00001
AIN1x
00010
AIN2x
00100
AIN3x
01000
AIN4x
Application:
“Analog Passthrough” on page 24
Note: Table does not show all possible combinations.
7.8
Analog ZC and SR Settings (Address 0Ah)
7
Reserved
7.8.1
6
Reserved
5
Reserved
4
Reserved
3
ANLGSFTB
2
ANLGZCB
1
ANLGSFTA
0
ANLGZCA
Ch. x Analog Soft Ramp
Configures an incremental volume ramp from the current level to the new level at the specified rate.
7.8.2
ANLGSFTx
Volume Changes
0
Do not occur with a soft ramp
Affected Analog Volume Controls
1
Occur with a soft ramp
Ramp Rate:
1/2 dB every 16 LRCK cycles
PASSxVOL[7:0] (“Passthrough x Volume” on page 46)
Ch. x Analog Zero Cross
Configures when the signal level changes occur for the analog volume controls.
ANLGZCx
Volume Changes
Affected Analog Volume Controls
0
Do not occur on a zero crossing
PASSxVOL[7:0] (“Passthrough x Volume” on page 46)
1
Occur on a zero crossing
Note: If the signal does not encounter a zero crossing, the requested volume change will occur after a
timeout period of 1024 sample periods (approximately 10.7 ms at 48 kHz sample rate).
7.9
Passthrough Gang Control (Address 0Ch)
7
PASSB=A
7.9.1
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Passthrough Channel B=A Gang Control
Configures independent or ganged control of the passthrough channel settings. Mute is not affected.
PASSB=A
42
Single Volume Control
0
Disabled
1
Enabled
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7.10
CS43L22
Playback Control 1 (Address 0Dh)
7
HPGAIN2
6
HPGAIN1
5
HPGAIN0
4
PLYBCKB=A
3
INV_PCMB
2
INV_PCMA
1
MSTBMUTE
0
MSTAMUTE
7.10.1 Headphone Analog Gain
Selects the gain multiplier for the headphone/line outputs.
HPGAIN[2:0]
Headphone/Line Gain Setting (G)
000
0.3959
001
0.4571
010
0.5111
011
0.6047
100
0.7099
101
0.8399
110
1.000
111
1.1430
Note: Refer to “Headphone Output Power Characteristics” on page 14 and “Headphone Output Power
Characteristics” on page 14.
7.10.2 Playback Volume Setting B=A
Configures independent or ganged volume control of all playback channels. Mute is not affected.
PLYBCKB=A
Single Volume Control for all Playback Channels
0
Disabled
1
Enabled
7.10.3 Invert PCM Signal Polarity
Configures the polarity of the digital input signal.
INV_PCMx
PCM Signal Polarity
0
Not Inverted
1
Inverted
7.10.4 Master Playback Mute
Configures a digital mute on the master volume control for channel x.
MSTxMUTE
Master Mute
0
Not Inverted
1
Inverted
Note: The muting function is affected by the DIGSFT (“Digital Soft Ramp” on page 44) and DIGZC
(“Digital Zero Cross” on page 45) bits.
DS792F2
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7.11
Miscellaneous Controls (Address 0Eh)
7
6
5
4
PASSTHRUB PASSTHRUA PASSBMUTE PASSAMUTE
7.11.1
CS43L22
3
FREEZE
2
DEEMPH
1
DIGSFT
0
DIGZC
Passthrough Analog
Configures an analog passthrough from the analog inputs to the headphone/line outputs.
PASSTHRUx
7.11.2
Analog In Routed to HP/Line Output
0
Disabled
1
Enabled
Passthrough Mute
Configures an analog mute on the channel x analog in to analog out passthrough.
PASSxMUTE
7.11.3
Passthrough Mute
0
Disabled
1
Enabled
Freeze Registers
Configures a hold on all register settings.
7.11.4
FREEZE
Control Port Status
0
Register changes take effect immediately
1
Modifications may be made to all control port registers without the changes taking effect until after the
FREEZE is disabled.
HP/Speaker De-Emphasis
Configures a 15μs/50μs digital de-emphasis filter response on the headphone/line and speaker outputs.
DEEMPHASIS
7.11.5
Control Port Status
0
Disabled
1
Enabled
Digital Soft Ramp
Configures an incremental volume ramp from the current level to the new level at the specified rate.
DIGSFT
Volume Changes
0
Does not occur with a soft ramp MSTxMUTE (“Master Playback Mute” on page 43),
HPxMUTE, SPKxMUTE (“Playback Control 2 (Address 0Fh)” on page 45),
PCMxMUTE, PCMxVOL[7:0] (“PCM Channel x Volume” on page 47),
MSTxVOL[7:0] (“Master Volume Control” on page 51),
Occurs with a soft ramp
HPxVOL[7:0] (“Headphone Volume Control” on page 51),
SPKxVOL[7:0] (“Speaker Volume Control” on page 52),
1
Ramp Rate:
44
Affected Digital Volume Controls
1/8 dB every LRCK cycle
DS792F2
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7.11.6
CS43L22
Digital Zero Cross
Configures when the signal level changes occur for the digital volume controls.
DIGZC
Volume Changes
Affected Digital Volume Controls
0
Do not occur on a zero crossing
1
Occur on a zero crossing
MSTxMUTE (“Master Playback Mute” on page 43),
HPxMUTE, SPKxMUTE (“Playback Control 2 (Address 0Fh)” on page 45),
PCMxMUTE, PCMxVOL[7:0] (“PCM Channel x Volume” on page 47),
MSTxVOL[7:0] (“Master Volume Control” on page 51),
HPxVOL[7:0] (“Headphone Volume Control” on page 51),
SPKxVOL[7:0] (“Speaker Volume Control” on page 52),
Notes:
1. If the signal does not encounter a zero crossing, the requested volume change will occur after a
timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate).
2. The zero cross function is independently monitored and implemented for each channel.
3. The DIS_LIMSFT bit (“Limiter Soft Ramp Disable” on page 53) is ignored when zero cross is enabled.
7.12
Playback Control 2 (Address 0Fh)
7
HPBMUTE
6
HPAMUTE
5
SPKBMUTE
4
SPKAMUTE
3
SPKB=A
2
SPKSWAP
1
SPKMONO
0
MUTE50/50
7.12.1 Headphone Mute
Configures a digital mute on headphone channel x.
HPxMUTE
Headphone Mute
0
Disabled
1
Enabled
7.12.2 Speaker Mute
Configures a digital mute on speaker channel x.
SPKxMUTE
Speaker Mute
0
Disabled
1
Enabled
7.12.3 Speaker Volume Setting B=A
Configures independent or ganged volume control of the speaker volume. Mute is not affected.
SPKB=A
Single Volume Control for the Speaker Channel
0
Disabled
1
Enabled
7.12.4 Speaker Channel Swap
Configures a channel swap on the speaker channels.
SPKSWAP
DS792F2
Speaker Output
0
Channel A
1
Channel B
Application:
“Mono Speaker Output Configuration” on page 27
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7.12.5 Speaker MONO Control
Configures a parallel full bridge output for the speaker channels.
SPKMONO
Parallel Full Bridge Output
0
Disabled
1
Enabled
Application:
“Mono Speaker Output Configuration” on page 27
7.12.6 Speaker Mute 50/50 Control
Configures how the speaker channels mute.
7.13
MUTE50/50
Speaker Mute 50/50
0
Disabled; The PWM amplifiers outputs modulated silence when SPKxMUTE is enabled.
1
Enabled; The PWM amplifiers switch at an exact 50%-duty-cycle signal (not modulated) when SPKxMUTE is
enabled.
Passthrough x Volume: PASSAVOL (Address 14h) & PASSBVOL (Address 15h)
7
PASSxVOL7
6
PASSxVOL6
5
PASSxVOL5
4
PASSxVOL4
3
PASSxVOL3
2
PASSxVOL2
1
PASSxVOL1
0
PASSxVOL0
7.13.1 Passthrough x Volume
Sets the volume/gain of the analog input signal routed to the headphone/line output.
PASSxVOL[7:0]
Gain
0111 1111
12 dB
...
...
0001 1000
12 dB
...
...
0000 0001
+0.5 dB
0000 0000
0 dB
11111 1111
-0.5 dB
...
...
1000 1000
-60.0 dB
...
...
1000 0000
-60.0 dB
Step Size:
0.5 dB (approximate)
Application:
“Passthrough Analog” on page 44
Notes:
1. This register is ignored when the PASSTHRUx bit (“Passthrough Analog” on page 44) is disabled.
2. The step size may deviate from 0.5 dB at settings below -40 dB. Code settings 0x95, 0xA1, 0xAD and
0xB9 are not guaranteed to be monotonic.
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7.14
CS43L22
PCMx Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh)
7
PCMxMUTE
6
PCMxVOL6
5
PCMxVOL5
4
PCMxVOL4
3
PCMxVOL3
2
PCMxVOL2
1
PCMxVOL1
0
PCMxVOL0
7.14.1 PCM Channel x Mute
Configures a digital mute on the PCM data from the serial data input (SDIN) to the DSP.
PCMxMUTE
PCM Mute
0
Disabled
1
Enabled
7.14.2 PCM Channel x Volume
Sets the volume/gain of the PCM data from the serial data input (SDIN) to the DSP.
7.15
PCMxVOL[6:0]
Volume
001 1000
+12.0 dB
...
...
000 0001
+0.5 dB
000 0000
0 dB
111 1111
-0.5 dB
...
...
001 1001
-51.5 dB
Step Size:
0.5 dB
Beep Frequency & On Time (Address 1Ch)
7
FREQ3
6
FREQ2
5
FREQ1
4
FREQ0
3
ONTIME3
2
ONTIME2
1
ONTIME1
0
ONTIME0
7.15.1 Beep Frequency
Sets the frequency of the beep signal.
DS792F2
FREQ[3:0]
Frequency (Fs = 12, 24, 48 or 96 kHz)
Pitch
0000
260.87 Hz
C4
0001
521.74 Hz
C5
0010
585.37 Hz
D5
0011
666.67 Hz
E5
0100
705.88 Hz
F5
0101
774.19 Hz
G5
0110
888.89 Hz
A5
0111
1000.00 Hz
B5
1000
1043.48 Hz
C6
1001
1200.00 Hz
D6
1010
1333.33 Hz
E6
1011
1411.76 Hz
F6
1100
1600.00 Hz
G6
1101
1714.29 Hz
A6
1110
2000.00 Hz
B6
1111
2181.82 Hz
C7
Application:
“Beep Generator” on page 22
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Notes:
1. This setting must not change when BEEP is enabled.
2. Beep frequency will scale directly with sample rate, Fs, but is fixed at the nominal Fs within each
speed mode.
7.15.2 Beep On Time
Sets the on duration of the beep signal.
ONTIME[3:0]
On Time (Fs = 12, 24, 48 or 96 kHz)
0000
~86 ms
0001
~430 ms
0010
~780 ms
0011
~1.20 s
0100
~1.50 s
0101
~1.80 s
0110
~2.20 s
0111
~2.50 s
1000
~2.80 s
1001
~3.20 s
1010
~3.50 s
1011
~3.80 s
1100
~4.20 s
1101
~4.50 s
1110
~4.80 s
1111
~5.20 s
Application:
“Beep Generator” on page 22
Notes:
1. This setting must not change when BEEP is enabled.
2. Beep on time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed
mode.
7.16
Beep Volume & Off Time (Address 1Dh)
7
OFFTIME2
6
OFFTIME1
5
OFFTIME0
4
BPVOL4
3
BPVOL3
2
BPVOL2
1
BPVOL1
0
BPVOL0
7.16.1 Beep Off Time
Sets the off duration of the beep signal.
48
OFFTIME[2:0]
Off Time (Fs = 48 or 96 kHz)
000
~1.23 s
001
~2.58 s
010
~3.90 s
011
~5.20 s
100
~6.60 s
101
~8.05 s
110
~9.35 s
111
~10.80 s
Application:
“Beep Generator” on page 22
DS792F2
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CS43L22
Notes:
1. This setting must not change when BEEP is enabled.
2. Beep off time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed
mode.
7.16.2 Beep Volume
Sets the volume of the beep signal.
BEEPVOL[4:0]
Gain
00110
+6.0 dB
···
···
00000
-6 dB
11111
-8 dB
11110
-10 dB
···
···
00111
-56 dB
Step Size:
2 dB
Application:
“Beep Generator” on page 22
Note:
7.17
This setting must not change when BEEP is enabled.
Beep & Tone Configuration (Address 1Eh)
7
BEEP1
6
BEEP0
5
BEEPMIXDIS
4
TREBCF1
3
TREBCF0
2
BASSCF1
1
BASSCF0
0
TCEN
7.17.1 Beep Configuration
Configures a beep mixed with the HP/Line and SPK output.
BEEP[1:0]
Beep Occurrence
00
Off
01
Single
10
Multiple
11
Continuous
Application:
“Beep Generator” on page 22
Notes:
1. When used in analog pass through mode, the output alternates between the signal from the
Passthrough Amplifier and the beep signal. The beep signal does not mix with the analog signal from
the Passthrough Amplifier.
2. Re-engaging the beep before it has completed its initial cycle will cause the beep signal to remain ON
for the maximum ONTIME duration.
7.17.2 Beep Mix Disable
Configures how the beep mixes with the serial data input.
BEEPMIXDIS
Beep Output to HP/Line and Speaker
0
Mix Enabled; The beep signal mixes with the digital signal from the serial data input.
1
Mix Disabled; The output alternates between the signal from the serial data input and the beep signal. The
beep signal does not mix with the digital signal from the serial data input.
Application:
“Beep Generator” on page 22
Note:
DS792F2
This setting must not change when BEEP is enabled.
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7.17.3 Treble Corner Frequency
Sets the corner frequency (-3 dB point) for the treble shelving filter.
TREBCF[1:0]
Treble Corner Frequency Setting
00
5 kHz
01
7 kHz
10
10 kHz
11
15 kHz
7.17.4 Bass Corner Frequency
Sets the corner frequency (-3 dB point) for the bass shelving filter.
BASSCF[1:0]
Bass Corner Frequency Setting
00
50 Hz
01
100 Hz
10
200 Hz
11
250 Hz
7.17.5 Tone Control Enable
Configures the treble and bass activation.
7.18
TCEN
Bass and Treble Control
0
Disabled
1
Enabled
Application:
“Beep Generator” on page 22
Tone Control (Address 1Fh)
7
TREB3
6
TREB2
5
TREB1
4
TREB0
3
BASS3
2
BASS2
1
BASS1
0
BASS0
7.18.1 Treble Gain
Sets the gain of the treble shelving filter.
50
TREB[3:0]
Gain Setting
0000
+12.0 dB
···
···
0111
+1.5 dB
1000
0 dB
1001
-1.5 dB
···
···
1111
-10.5 dB
Step Size:
1.5 dB
DS792F2
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CS43L22
7.18.2 Bass Gain
Sets the gain of the bass shelving filter.
7.19
TREB[3:0]
Gain Setting
0000
+12.0 dB
···
···
0111
+1.5 dB
1000
0 dB
1001
-1.5 dB
···
···
1111
-10.5 dB
Step Size:
1.5 dB
Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)
7
MSTxVOL7
6
MSTxVOL6
5
MSTxVOL5
4
MSTxVOL4
3
MSTxVOL3
2
MSTxVOL2
1
MSTxVOL1
0
MSTxVOL0
7.19.1 Master Volume Control
Sets the volume of the signal out the DSP.
7.20
MSTxVOL[7:0]
Master Volume
0001 1000
+12.0 dB
···
···
0000 0000
0 dB
1111 1111
-0.5 dB
1111 1110
-1.0 dB
···
···
0011 0100
-102 dB
···
···
0001 1001
-102 dB
Step Size:
0.5 dB
Headphone Volume Control: HPA (Address 22h) & HPB (Address 23h)
7
HPxVOL7
6
HPxVOL6
5
HPxVOL5
4
HPxVOL4
3
HPxVOL3
2
HPxVOL2
1
HPxVOL1
0
HPxVOL0
7.20.1 Headphone Volume Control
Sets the volume of the signal out the DAC.
HPxVOL[7:0]
DS792F2
Headphone Volume
0000 0000
0 dB
1111 1111
-0.5 dB
1111 1110
-1.0 dB
···
···
0011 0100
-96.0 dB
···
···
0000 0001
Muted
Step Size:
0.5 dB
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7.21
CS43L22
Speaker Volume Control: SPKA (Address 24h) & SPKB (Address 25h)
7
SPKxVOL7
6
SPKxVOL6
5
SPKxVOL5
4
SPKxVOL4
3
SPKxVOL3
2
SPKxVOL2
1
SPKxVOL1
0
SPKxVOL0
2
Reserved
1
Reserved
0
Reserved
7.21.1 Speaker Volume Control
Sets the volume of the signal out the PWM modulator.
SPKxVOL[7:0]
0 dB
1111 1111
-0.5 dB
1111 1110
-1.0 dB
···
···
0100 0000
-96.0 dB
···
···
0000 0001
Muted
Step Size:
0.5 dB
Note:
7.22
Speaker Volume
0000 0000
The maximum step size error is +/-0.15 dB.
PCM Channel Swap (Address 26h)
7
PCMASWP1
6
PCMASWP0
5
PCMBSWP1
4
PCMBSWP0
3
Reserved
7.22.1 PCM Channel Swap
Configures a mix/swap of the PCM data to the headphone/line or speaker outputs.
PCMxSWP[1:0]
PCM to HP/LINEOUTA
PCM to HP/LINEOUTB
00
Left
Right
(Left + Right)/2
(Left + Right)/2
Right
Left
01
10
11
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7.23
CS43L22
Limiter Control 1, Min/Max Thresholds (Address 27h)
7
LMAX2
6
LMAX1
5
LMAX0
4
CUSH2
3
CUSH1
2
CUSH0
1
LIMSRDIS
0
LIMZCDIS
7.23.1 Limiter Maximum Threshold
Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack
rate (LIMARATE - “Limiter Release Rate” on page 54).
LMAX[2:0]
Threshold Setting
000
0 dB
001
-3 dB
010
-6 dB
011
-9 dB
100
-12 dB
101
-18 dB
110
-24 dB
111
-30 dB
Application:
“Limiter” on page 22
Note: Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may
trigger an attack.
7.23.2 Limiter Cushion Threshold
Sets the minimum level at which to disengage the Limiter’s attenuation at the release rate (LIMRRATE “Limiter Release Rate” on page 54) until levels lie between the LMAX and CUSH thresholds.
CUSH[2:0]
Threshold Setting
000
0 dB
001
-3 dB
010
-6 dB
011
-9 dB
100
-12 dB
101
-18 dB
110
-24 dB
111
-30 dB
Application:
“Limiter” on page 22
Note:
This setting is usually set slightly below the LMAX threshold.
7.23.3 Limiter Soft Ramp Disable
Configures an override of the digital soft ramp setting.
LIMSRDIS
OFF; Limiter Attack Rate is dictated by the DIGSFT (“Digital Soft Ramp” on page 44) setting
1
ON; Limiter volume changes take effect in one step, regardless of the DIGSFT setting.
Application:
“Limiter” on page 22
Note:
DS792F2
Limiter Soft Ramp Disable
0
This bit is ignored when the DIGZC (“Digital Zero Cross” on page 45) is enabled.
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CS43L22
7.23.4 Limiter Zero Cross Disable
Configures an override of the digital zero cross setting.
7.24
LIMZCDIS
Limiter Zero Cross Disable
0
OFF; Limiter Attack Rate is dictated by the DIGZC (“Digital Zero Cross” on page 45) setting
1
ON; Limiter volume changes take effect in one step, regardless of the DIGZC setting.
Application:
“Limiter” on page 22
Limiter Control 2, Release Rate (Address 28h)
7
LIMIT
6
LIMIT_ALL
5
LIMRRATE5
4
LIMRRATE4
3
LIMRRATE3
2
LIMRRATE2
1
LIMRRATE1
0
LIMRRATE0
7.24.1 Peak Detect and Limiter
Configures the peak detect and limiter circuitry.
LIMIT
Limiter Status
0
Disabled
1
Enabled
Application:
“Limiter” on page 22
7.24.2 Peak Signal Limit All Channels
Sets how channels are attenuated when the limiter is enabled.
LIMIT_ALL
Limiter action:
0
Apply the necessary attenuation on a specific channel only when the signal amplitude on that specific channel rises above LMAX.
Remove attenuation on a specific channel only when the signal amplitude on that specific channel falls below
CUSH.
1
Apply the necessary attenuation on BOTH channels when the signal amplitude on any ONE channel rises
above LMAX.
Remove attenuation on BOTH channels only when the signal amplitude on BOTH channels fall below CUSH.
Application:
“Limiter” on page 22
7.24.3 Limiter Release Rate
Sets the rate at which the limiter releases the digital attenuation from levels below the CUSH[2:0] threshold (“Limiter Cushion Threshold” on page 53) and returns the analog output level to the MSTxVOL[7:0]
(“Master Volume Control” on page 51) setting.
LIMRRATE[5:0]
Release Time
00 0000
Fastest Release
···
···
11 1111
Slowest Release
Application:
“Limiter” on page 22
Note: The limiter release rate is user-selectable but is also a function of the sampling frequency, Fs,
and the DIGSFT (“Digital Soft Ramp” on page 44) and DIGZC (“Digital Zero Cross” on page 45) setting.
54
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7.25
CS43L22
Limiter Attack Rate (Address 29h)
7
Reserved
6
Reserved
5
LIMARATE5
4
LIMARATE4
3
LIMARATE3
2
LIMARATE2
1
LIMARATE1
0
LIMARATE0
7.25.1 Limiter Attack Rate
Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold
(“Limiter Maximum Threshold” on page 53).
LIMARATE[5:0]
Attack Time
00 0000
Fastest Attack
···
···
11 1111
Slowest Attack
Application:
“Limiter” on page 22
Note: The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and
the DIGSFT (“Digital Soft Ramp” on page 44) and DIGZC (“Digital Zero Cross” on page 45) setting unless
the respective disable bit (“Limiter Soft Ramp Disable” on page 53 or “Limiter Zero Cross Disable” on
page 54) is enabled.
7.26
Status (Address 2Eh) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
7
Reserved
6
SPCLKERR
5
DSPAOVFL
4
DSPBOVFL
3
PCMAOVFL
2
PCMBOVFL
1
Reserved
0
Reserved
7.26.1 Serial Port Clock Error (Read Only)
Indicates the status of the MCLK to LRCK ratio.
SPCLKERR
Serial Port Clock Status:
0
MCLK/LRCK ratio is valid.
1
MCLK/LRCK ratio is not valid.
Application:
“Serial Port Clocking” on page 29
Note:
nizes.
On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-
7.26.2 DSP Engine Overflow (Read Only)
Indicates the over-range status in the DSP data path.
DS792F2
DSPxOVFL
DSP Overflow Status:
0
No digital clipping has occurred in the data path after the DSP.
1
Digital clipping has occurred in the data path after the DSP.
Application:
“DSP Engine” on page 21
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7.26.3 PCMx Overflow (Read Only)
Indicates the over-range status in the PCM data path.
7.27
PCMxOVFL
PCM Overflow Status:
0
No digital clipping has occurred in the data path of the PCM (“PCM Channel x Volume” on page 47) of the
DSP.
1
Digital clipping has occurred in the data path of the PCM of the DSP.
Application:
“DSP Engine” on page 21
Battery Compensation (Address 2Fh)
7
BATTCMP
6
VPMONITOR
5
Reserved
4
Reserved
3
VPREF3
2
VPREF2
1
VPREF1
0
VPREF0
7.27.1 Battery Compensation
Configures automatic adjustment of the speaker volume when VP deviates from VPREF[3:0].
BATTCMP
Automatic Battery Compensation
0
Disabled
1
Enabled
Application:
“Maintaining a Desired Output Level” on page 27
7.27.2 VP Monitor
Configures the internal ADC that monitors the VP voltage level.
VPMONITOR
VP ADC Status
0
Disabled
1
Enabled
Notes:
1. The internal ADC that monitors the VP supply is enabled automatically when BATTCMP is enabled, regardless of the VPMONITOR setting. Conversely, when BATTCMP is disabled, the ADC may be enabled by enabling VPMONITOR; this provides a convenient battery monitor without enabling battery
compensation.
2. When enabled, VPMONITOR remains enabled regardless of the PDN bit setting.
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7.27.3 VP Reference
Sets the desired VP reference used for battery compensation.
VPREF[3:0]
Desired VP used to calculate the required attenuation on the speaker output:
0000
1.5 V
0001
2.0 V
(for VA = 1.8 V)
0010
2.5 V
0011
3.0 V
0100
3.5 V
0101
4.0 V
0110
4.5 V
0111
5.0 V
1000
1.5 V
1001
2.0 V
(for VA = 2.5 V)
7.28
1010
2.5 V
1011
3.0 V
1100
3.5 V
1101
4.0 V
1110
4.5 V
1111
5.0 V
Application:
“VP Battery Compensation” on page 27
VP Battery Level (Address 30h) (Read Only)
7
VPLVL7
6
VPLVL6
5
VPLVL5
4
VPLVL4
3
VPLVL3
2
VPLVL2
1
VPLVL1
0
VPLVL0
7.28.1 VP Voltage Level (Read Only)
Indicates the unsigned VP voltage level.
VPLVL[7:0]
VP Voltage
...
0101 1110
3.0 V (for VA = 2.0 V); apply formula using actual VA voltage to calculate VP voltage.
...
0111 0010
3.7 V (for VA = 2.0 V); apply formula using actual VA voltage to calculate VP voltage.
...
Formula:
7.29
VP Voltage = (Binary representation of VPLVL[7:0]) * VA / 63.3
Speaker Status (Address 31h) (Read Only)
7
Reserved
6
Reserved
5
SPKASHRT
4
SPKBSHRT
3
SPKR/HP
2
Reserved
1
Reserved
0
Reserved
7.29.1 Speaker Current Load Status (Read Only)
Indicates whether or not any of the speaker outputs is shorted to ground.
DS792F2
SPKxSHRT
Speaker Output Load
0
No overload detected
1
Overload detected
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7.29.2 SPKR/HP Pin Status (Read Only)
Indicates the status of the SPKR/HP pin.
7.30
SPKR/HP
Pin State
0
Pulled Low
1
Pulled High
Charge Pump Frequency (Address 34h)
7
CHGFREQ3
6
CHGFREQ2
5
CHGFREQ1
4
CHGFREQ0
3
Reserved
2
Reserved
1
Reserved
0
Reserved
7.30.1 Charge Pump Frequency
Sets the charge pump frequency on FLYN and FLYP.
CHGFREQ[3:0]
N
0000
0
...
0101
5
...
1111
15
Formula:
Frequency = (64xFs)/(N+2)
Note:
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8. ANALOG PERFORMANCE PLOTS
8.1
Headphone THD+N versus Output Power Plots
Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48 kHz.
-10
G = 0.6047
-15
VHP = VA = 1.8 V
G = 0.7099
-20
G = 0.8399
-25
-30
G = 1.0000
-35
G = 1.1430
-40
Legend
-45
d
B
r
A
-50
NOTE: Graph shows the output power per channel (i.e.
Output Power = 23 mW
into
single 16 Ω and 46 mW into
stereo 16 Ω with THD+N = 75 dB).
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
0
10m
20m
30m
40m
50m
60m
70m
80m
W
Figure 18. THD+N vs. Output Power per Channel at 1.8 V (16 Ω load)
-10
-15
G = 0.6047
VHP = VA = 2.5 V
G = 0.7099
-20
-25
G = 0.8399
-30
G = 1.0000
-35
G = 1.1430
-40
Legend
-45
d
B
r
A
NOTE: Graph shows the output power per channel (i.e.
Output Power = 44 mW
into
single 16 Ω and 88 mW into
stereo 16 Ω with THD+N = 75 dB).
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
0
10m
20m
30m
40m
50m
60m
70m
80m
W
Figure 19. THD+N vs. Output Power per Channel at 2.5 V (16 Ω load)
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CS43L22
G = 0.6047
VHP = VA = 1.8 V
G = 0.7099
-20
-30
G = 0.8399
-35
G = 1.0000
-40
G = 1.1430
-45
Legend
-50
NOTE: Graph shows the output power per channel (i.e.
Output Power = 22 mW
into
single 32 Ω and 44 mW into
stereo 32 Ω with THD+N = 75 dB).
-55
d
B
r
-60
A
-65
-70
-75
-80
-85
-90
-95
-100
0
6m
12m
18m
24m
30m
36m
42m
48m
54m
60m
W
Figure 20. THD+N vs. Output Power per Channel at 1.8 V (32 Ω load)
G = 0.6047
-20
VHP = VA = 2.5 V
-25
G = 0.7099
-30
G = 0.8399
-35
G = 1.0000
-40
G = 1.1430
-45
Legend
-50
-55
d
B
r
NOTE: Graph shows the output power per channel (i.e.
Output Power = 42 mW
into
single 32 Ω and 84 mW into
stereo 32 Ω with THD+N = 75 dB).
-60
A
-65
-70
-75
-80
-85
-90
-95
-100
0
5m
10m
15m
20m
25m
30m
35m
40m
45m
50m
55m
60m
W
Figure 21. THD+N vs. Output Power per Channel at 2.5 V (32 Ω load)
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9. EXAMPLE SYSTEM CLOCK FREQUENCIES
9.1
9.2
CS43L22
*The”MCLKDIV2” bit must be enabled.
Auto Detect Enabled
Sample Rate
LRCK (kHz)
1024x
MCLK (MHz)
1536x
2048x*
8
11.025
12
3072x*
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
24.5760
33.8688
36.8640
Sample Rate
LRCK (kHz)
512x
MCLK (MHz)
768x
1024x*
16
22.05
24
8.1920
11.2896
12.2880
Sample Rate
LRCK (kHz)
256x
32
44.1
48
8.1920
11.2896
12.2880
Sample Rate
LRCK (kHz)
128x
64
88.2
96
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
MCLK (MHz)
384x
512x*
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
MCLK (MHz)
192x
256x*
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
1536x*
24.5760
33.8688
36.8640
768x*
24.5760
33.8688
36.8640
384x*
24.5760
33.8688
36.8640
Auto Detect Disabled
DS792F2
Sample Rate
LRCK (kHz)
512x
8
11.025
12
6.1440
768x
MCLK (MHz)
1024x
1536x
2048x
3072x
6.1440
8.4672
9.2160
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
Sample Rate
LRCK (kHz)
256x
384x
512x
16
22.05
24
6.1440
6.1440
8.4672
9.2160
8.1920
11.2896
12.2880
Sample Rate
LRCK (kHz)
256x
32
44.1
48
8.1920
11.2896
12.2880
Sample Rate
LRCK (kHz)
128x
64
88.2
96
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
MCLK (MHz)
768x
12.2880
16.9344
18.4320
1024x
1536x
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
MCLK (MHz)
384x
512x
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
MCLK (MHz)
192x
256x
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
768x
24.5760
33.8688
36.8640
384x
24.5760
33.8688
36.8640
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10.PCB LAYOUT CONSIDERATIONS
10.1
Power Supply, Grounding
As with any high-resolution converter, the CS43L22 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 9 shows the recommended
power arrangements, with VA and VHP connected to clean supplies VD, which powers the digital circuitry,
may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a
ferrite bead. In this case, no additional devices should be powered from VD.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS43L22 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same
side of the board as the CS43L22 to minimize inductance effects.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the modulators. The VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to
minimize the electrical path from AGND. The CDB43L22 evaluation board demonstrates the optimum layout
and power supply arrangements.
10.2
QFN Thermal Pad
The CS43L22 is available in a compact QFN package. The underside of the QFN package reveals a large
metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS43L22 evaluation board demonstrates the optimum thermal pad and via configuration.
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11.DIGITAL FILTER PLOTS
DS792F2
Figure 22. Passband Ripple
Figure 23. Stopband
Figure 24. DAC Transition Band
Figure 25. Transition Band (Detail)
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12.PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channel pairs. Units in decibels.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
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13.PACKAGE DIMENSIONS
40L QFN (6 X 6 mm BODY) PACKAGE DRAWING
D
b
2.00REF
e
PIN #1CORNER
2.00REF
PIN #1IDENTIFIER
∅0.50±0.10
LASER MARKING
E2
E
A1
L
D2
A
DIM
A
A1
b
D
D2
E
E2
e
L
MIN
-0.0000
0.0071
0.1594
0.1594
0.0118
INCHES
NOM
--0.0091
0.2362 BSC
0.1614
0.2362 BSC
0.1614
0.0197 BSC
0.0157
MAX
0.0394
0.0020
0.0110
MIN
-0.00
0.18
0.1634
4.05
0.1634
4.05
0.0197
0.30
MILLIMETERS
NOM
--0.23
6.00 BSC
4.10
6.00 BSC
4.10
0.50 BSC
0.40
NOTE
MAX
1.00
0.05
0.28
4.15
4.15
0.50
1
1
1,2
1
1
1
1
1
1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm
from the terminal tip.
THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance
DS792F2
2 Layer Board
4 Layer Board
Symbol
Min
Typ
Max
Units
θJA
θJA
-
44
19
-
°C/Watt
°C/Watt
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14.ORDERING INFORMATION
Product
Description
Low-Power Stereo DAC
CS43L22 w/HP and Speaker Amps
for Portable Apps
CS43L22 Evaluation
CDB43L22
Board
Package Pb-Free
40L-QFN
Yes
-
No
Grade
Temp Range
Commercial -40 to +85° C
-
Container
Order #
Rail
CS43L22-CNZ
Tape & Reel CS43L22-CNZR
-
-
CDB43L22
15.REFERENCES
1. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000.
http://www.semiconductors.philips.com
16.REVISION HISTORY
Revision
Changes
F2
Added AD0 characteristics to “I/O Pin Characteristics” on page 8.
Added a description of the AD0 pin to “I²C Control” on page 33.
Added AD0 detail to Figure 16. Control Port Timing, I²C Write on page 33 and Figure 17. Control Port Timing, I²C
Read on page 33.
Updated the first paragraph in “Register Quick Reference” on page 35 and “Register Description” on page 37 to
allow for data sheet-specified control-writes to reserved registers.
Updated Note 3 on page 11.
Removed I²C address heading row from “Register Quick Reference” on page 35.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY
INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a trademark of Philips Semiconductor.
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