IDT IDT54FCT162H272ETPA Fast cmos 12-bit synchronous bus exchanger Datasheet

IDT54/74FCT162H272AT/CT/ET
FAST CMOS
12-BIT SYNCHRONOUS
BUS EXCHANGER
Integrated Device Technology, Inc.
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
multiplexers for use in synchronous memory interleaving
applications. All registers have a common clock and use a
clock enable (CExxx) on each data register to control data
sequencing. The output enables and mux select (OEA, OEB
and SEL) are also under synchronous control allowing direction changes to be edge triggered events.
The tri-port bus exchanger has three 12-bit ports. Data may
be transferred between the A port and either/both of the B
ports. The clock enable (CE1B, CE2B, CEA1B and CEA2B)
inputs control the data storage. Both B ports have a common
output enable (OEB) to aid in synchronously loading the B
registers from the B port.
The FCT162H272AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times-reducing
the need for external series terminating resistors.
The FCT162H272AT/CT/ET have "Bus Hold" which retains the input's last state whenever the input goes to high
impedance. This prevents "floating" inputs and eliminates the
need for pull-up/down resistors.
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage ≤ 1µA (max.)
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,
15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of -40°C to +85°C
Balanced Output Drivers:
±24mA (commercial)
±16mA (military)
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V, TA = 25°C
Bus Hold retains last active bus state during 3-state
Eliminates the need for external pull up resistors
DESCRIPTION:
The FCT162H272AT/CT/ET synchronous tri-port bus exchangers are high-speed, bidirectional,12-bit, registered, bus
FUNCTIONAL BLOCK DIAGRAM
CEA1B
CE A-1B
REGISTER
Q
D
CLK
CE1B
SEL
OEB
12
CONTROL
REGISTER
12
1B1:12
12
CE 1B-A
REGISTER
D
Q
12
OEA
A1:12
12
M1
U
X0
CE 2B-A
REGISTER
CE2B
12
12
CEA2B
Q
D
CE A-2B
REGISTER
Q
D
12
12
2B1:12
3071 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
5.5
AUGUST 1996
DSC-3071/3
1
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
PIN CONFIGURATIONS
CEA1B
1
56
CE1B
CEA1B
1
56
CE1B
CEA2B
2
55
CE2B
CEA2B
2
55
CE2B
2B3
3
54
2B4
2B3
3
54
2B4
GND
4
53
GND
GND
4
53
GND
2B2
5
52
2B5
2B2
5
52
2B5
2B1
6
51
2B6
2B1
6
51
2B6
VCC
7
50
VCC
VCC
7
50
VCC
A1
8
49
2B7
A1
8
49
2B7
A2
9
48
2B8
A2
9
48
2B8
A3
10
47
2B9
A3
10
47
2B9
GND
11
46
GND
GND
11
46
GND
A4
12
45
2B10
A4
12
45
2B10
A5
13
44
2B11
A5
13
44
2B11
A6
2B12
A6
14
43
2B12
A7
14 SO56-1 43
SO56-2
15 SO56-3 42
1B12
A7
15
42
1B12
A8
16
41
1B11
A8
16
41
1B11
A9
17
40
1B10
A9
17
40
1B10
GND
18
39
GND
GND
18
39
GND
A10
19
38
1B9
A10
19
38
1B9
A11
20
37
1B8
A11
20
37
1B8
A12
21
36
1B7
A12
21
36
1B7
VCC
22
35
VCC
VCC
22
35
VCC
1B1
23
34
1B6
1B1
23
34
1B6
1B2
24
33
1B5
1B2
24
33
1B5
GND
25
32
GND
GND
25
32
GND
1B3
26
31
1B4
1B3
26
31
1B4
OEA
27
30
OEB
OEA
27
30
OEB
SEL
28
29
CLK
SEL
28
29
SSOP/
TSSOP/TVSOP
TOP VIEW
E56-1
CLK
3071 drw 03
3071 drw 02
CERPACK
TOP VIEW
5.5
2
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
PIN DESCRIPTION
Signal
I/O
Description
A(1:12)
1B(1:12)
2B(1:12)
CLK
CEA1B
I/O
I/O
I/O
I
I
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.(1)
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.(1)
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.(1)
Clock Input.
Clock Enable Input for the A-1B Register. If CEA1B is LOW during the rising edge of CLK, data will be clocked
into register A-1B (Active LOW).
CEA2B
I
Clock Enable Input for the A-2B Register. If CEA2B is LOW during the rising edge of CLK, data will be clocked
into register A-2B (Active LOW).
CE1B
I
Clock Enable Input for the 1B-A Register. If CE1B is LOW during the rising edge of CLK, data will be clocked into
register 1B-A (Active LOW).
CE2B
I
Clock Enable Input for the 2B-A Register. If CE2B is LOW during the rising edge of CLK, data will be clocked into
register 2B-A (Active LOW).
SEL
I
1B or 2B Path Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to
A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port.
I
Synchronous Output Enable for A Port (Active LOW).
I
Synchronous Output Enable for 1B Port and 2B Port (Active LOW).
OEA
OEB
NOTES:
1. On FCT162H272T these pins have "Bus Hold". All other pins are standard inputs, outputs or I/Os.
ABSOLUTE MAXIMUM RATINGS(1)
FUNCTION TABLES(2)
Symbol
Description
Max.
VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0
GND
–0.5 to
VTERM(3) Terminal Voltage with Respect to
GND
VCC +0.5
TSTG
Storage Temperature
–65 to +150
Unit
V
°C
I OUT
mA
X
DC Output Current
–60 to +120
V
3071 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
Conditions
VIN = 0V
Typ.
3.5
VOUT = 0V
3.5
NOTE:
1. This parameter is measured at characterization but not tested.
2B
H
X
H
L
X
X
X
H
CE2B OEA
CLK
Output
A
↑
H
L
X
L
H
L
X
L
↑
L
H
H
X
L
↑
A(1)
L
X
L
L
↑
H
X
L
L
X
L
L
↑
L
X
X
L
X
H
L
↑
A(1)
X
X
X
X
X
H
↑
Inputs
A
Max. Unit
6.0
pF
8.0
Inputs
SEL CE1B
1B
Z
3071 tbl 04
CAPACITANCE (TA = +25°C, F = 1.0MHZ)
Symbol
Parameter(1)
CIN
Input
Capacitance
CI/O
I/O
Capacitance
3071 tbl 01
pF
3071 tbl 03
CEA1B CEA2B
Outputs
OEB
CLK
1B
2B
H
H
L
L
L
↑
H
L
L
L
L
↑
L
L
H
L
H
L
↑
H
B(1)
L
L
H
L
↑
L
B(1)
H
H
L
L
↑
B(1)
H
L
H
L
L
↑
B(1)
L
B(1)
B(1)
X
H
H
L
↑
X
X
X
H
↑
Z
Z
X
X
X
L
↑
Active
Active
3071 tbl 05
NOTES:
1. Output level before the indicated steady-state input conditions were
established.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
↑ = LOW-to-HIGH Transition
5.5
3
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD)
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
VIL
II H
Test Conditions(1)
Guaranteed Logic HIGH Level
Parameter
Input HIGH Level
Input LOW Level
Min.
2.0
Typ.(2)
—
Max.
—
Unit
V
Guaranteed Logic LOW Level
—
—
0.8
V
VCC = Max.
µA
Input
Standard
—
—
±1
HIGH
Standard I/O(5)
—
—
±1
Current(4)
Bus-Hold Input
—
—
±100
—
—
±100
Input
Standard Input(5)
—
—
±1
LOW
Standard
I/O(5)
—
—
±1
Current(4)
Bus-Hold Input
—
—
±100
Bus-Hold I/O
—
—
±100
VI = 2.0V
–50
—
—
VI = 0.8V
+50
—
—
VO = 2.7V
—
—
±1
Input(5)
VI = VCC
Bus-Hold I/O
II L
I BHH
Bus Hold
I BHL
Sustain
Current(4)
High Impedance Output Current
I OZH
Bus-Hold Input
VI = GND
VCC = Min.
VCC = Max.
pins) (5,6)
I OZL
(3-State Output
VIK
Clamp Diode Voltage
I OS
Short Circuit Current
VH
Input Hysteresis
I CCL
I CCH
I CCZ
Quiescent Power Supply Current
VO = 0.5V
VCC = Min., IIN = –18mA
VCC = Max., VO =
GND(3)
—
VCC = Max., VIN = GND or VCC
µA
µA
—
—
±1
—
–0.7
–1.2
V
–80
–140
–225
mA
—
100
—
mV
—
5
500
µA
3071 tbl 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162H272T
Symbol
I ODL
Parameter
Output LOW Current
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3)
Min.
60
Typ.(2)
115
Max.
200
Unit
mA
I ODH
Output HIGH Current
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
–60
–115
–200
mA
VOH
Output HIGH Voltage
2.4
3.3
—
V
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or V IL
VCC = Min.
VIN = VIH or V IL
—
0.3
0.55
V
I OH = –16mA MIL.
I OH = –24mA COM'L.
I OL = 16mA MIL.
I OL = 24mA COM'L.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
6. Does not include Bus Hold I/O pins.
5.5
3071 lnk 08
4
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
ICCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current (4)
IC
Total Power Supply Current (6)
∆ICC
Test Conditions(1)
VCC = Max.
VIN = 3.4V(3)
VCC = Max.
Outputs Open
One Output Port Enabled
CExx = GND
One Input Bit Toggling
One Output Bit Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
One Output Port Enabled
CExx = GND
One Input Bit Toggling
One Output Bit Toggling
VCC = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
One Output Port Enabled
CExx = GND
Twelve Input Bits Toggling
Twelve Output Bits Toggling
Min.
—
Typ.(2)
0.5
Max.
1.5
Unit
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
VIN = VCC
VIN = GND
—
0.6
1.5
mA
VIN = 3.4V
VIN = GND
—
0.9
2.3
VIN = VCC
VIN = GND
—
1.8
3.5 (5)
VIN = 3.4V
VIN = GND
—
4.8
12.5 (5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5.5
mA
3071 tbl 09
5
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162H272AT
Com'l.
Symbol
Parameter
tPLH
tPHL
tPLH
tPHL
Propagation Delay
CLK to 1Bx or CLK to 2Bx
Propagation SEL Stable
Delay
CExB Enabled
CLK to Ax
SEL Changing
CExB Disabled
SEL Changing
CExB Enabled
Output Enable Time
CLK to Ax, CLK to 1Bx, or
CLK to 2Bx
Output Disable Time
CLK to Ax, CLK to 1Bx, or
CLK to 2Bx
Set-Up Time, HIGH or LOW
Data to CLK
Set-Up Time, OEA to CLK,
tPZH
tPZL
tPHZ
tPLZ
tSU
tSU
FCT162H272CT
Mil.
Com'l.
FCT162H272ET
Mil.
Com'l.
Mil.
Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
C L = 50pF
R L = 500Ω
1.5
5.8
1.5
6.2
1.5
5.2
1.5
5.6
1.5
4.8
—
—
ns
1.5
6.0
1.5
6.4
1.5
5.4
1.5
5.8
1.5
5.0
—
—
ns
1.5
6.0
1.5
6.4
1.5
5.4
1.5
5.8
1.5
5.4
—
—
ns
1.5
7.6
1.5
7.9
1.5
6.6
1.5
7.0
1.5
5.6
—
—
ns
1.5
7.7
1.5
8.1
1.5
6.8
1.5
7.2
1.5
6.0
—
—
ns
1.5
6.4
1.5
6.8
1.5
6.0
1.5
6.4
1.5
5.6
—
—
ns
2.0
—
2.0
—
2.0
—
2.0
—
2.0
—
—
—
ns
2.0
—
2.0
—
2.0
—
2.0
—
2.0
—
—
—
ns
2.0
—
2.0
—
2.0
—
2.0
—
2.0
—
—
—
ns
2.0
—
2.0
—
2.0
—
2.0
—
2.0
—
—
—
ns
OEB to CLK
tSU
tSU
tH
tH
tH
tW
Set-Up Time, SEL to CLK
Set-Up Time, CEA1B to CLK,
CE1B to CLK, CE2B to CLK,
or CEA2B to CLK
Hold Time, CLK to Data
Hold Time, CLK to OEA,
CLK to OEB, CLK to SEL
Hold Time, CLK to CEA1B,
CLK to CE1B, CLK to CE2B,
CLK to CEA2B
Pulse Width, CLK HIGH (4)
tSK(o) Output
Skew (3)
0
—
0
—
0
—
0
—
0
—
—
—
ns
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
—
—
ns
0
—
0
—
0
—
0
—
0
—
—
—
ns
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
—
—
ns
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
—
ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
5.5
3071 tbl 10
6
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC
SWITCH POSITION
7.0V
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
500Ω
V OUT
VIN
Pulse
Generator
3032 tbl 11
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
D.U.T.
50pF
RT
Open
All Other Tests
500Ω
CL
3071 lnk 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
1.5V
0V
DATA
INPUT
t SU
tH
TIMING
INPUT
ASYNCHRONOUS CONTROL
1.5V
tW
t REM
HIGH-LOW-HIGH
PULSE
3V
1.5V
0V
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
1.5V
3071 lnk 06
t SU
3V
1.5V
0V
tH
3071 lnk 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
SAME PHASE
INPUT TRANSITION
t PLH
t PHL
ENABLE
3V
1.5V
0V
tPZL
OUTPUT
NORMALLY SWITCH
LOW CLOSED
tPZH
V OL
t PLH
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
CONTROL
INPUT
V OH
1.5V
OUTPUT
DISABLE
t PHL
3V
1.5V
OUTPUT SWITCH
NORMALLY OPEN
HIGH
0V
0V
tPLZ
3.5V
1.5V
3.5V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
3071 lnk 07
3071 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5.5
7
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
ORDERING INFORMATION
IDT
FCT X
XX
Drive
Temp. Range
X
Bus Hold
XXXX
Device Type
X
Package
X
Process
Blank
B
Commercial
MIL-STD-883, Class B
PV
PA
PF
E
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
272AT
272CT
272ET
12-Bit Synchronous Tri-Port Bus Exchanger
H
Bus Hold
162
54
74
16-Bit Balanced Drive
-55°C to +125°C
-40°C to +85°C
3071 drw 09
5.5
8
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