LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 LM3495 Emulated Peak Current Mode Buck Controller for Low Output Voltage Check for Samples: LM3495 FEATURES DESCRIPTION • • • • The LM3495 is a PWM buck regulator which implements a unique emulated peak current mode control. This control method eliminates the switching noise which typically limits current mode operation at extremely short duty cycles and high operating frequency. The switching frequency is programmable between 200 kHz and 1.5 MHz, and can also be synchronized to an external clock. The LM3495 is also very fault tolerant with both switch node short, hiccup mode, and adaptive duty cycle limit protection. A 0.6V 1% reference and glitch free pre-biased startup ensure the most demanding digital loads operate reliably. Internal soft start and the ability to track the output of another supply make the LM3495 versatile and efficient. 1 2 • • • • • • • • • • Input Voltage from 2.9V to 18V Output Voltage Adjustable from 0.6V to 5.5V Feedback Accuracy: ±1% Low-Side Sensing, Programmable Current Limit without Sense Resistor Input Under Voltage Lockout Hiccup Mode Current Limit Protection Eliminates Thermal Runaway During Fault Conditions Internal Soft Start with Tracking Capability 200 kHz to 1.5 MHz Switching Frequency, Synchronizable On-Chip Gate Drivers Soft Output Discharge During Shutdown Startup into Output Pre-Bias Operation from a Single Input Rail Adaptive Duty Cycle Limit TSSOP-16 Package APPLICATIONS • Wide Input Voltage Buck Converters with Low Voltage, High Accuracy Outputs Core Logic Regulators High-Efficiency Buck Regulation • • Typical Application CF D1 CDD VIN FPWM VIN VLIN5 BOOST CINX CIN CB FREQ/SYNC CSYNC Q1 HG RFRQ VLIN5 SW/CSH TRACK LM3495 RC CC L1 RILIM VO ILIM LG COMP/SD Q2 CO CSL RFB1 FB SNS SGND PGND RFB2 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Connection Diagram BOOST 1 16 PGND HG 2 15 LG SW/CSH 3 14 VLIN5 CSL 4 13 VIN ILIM 5 12 SGND FPWM 6 11 COMP/SD SNS 7 10 FB FREQ/SYNC 8 9 TRACK LM3495 Figure 1. 16-Lead Plastic TSSOP Package (Top View) See Package Number PW0016A θJA = 155°C/W PIN DESCRIPTIONS BOOST (Pin 1): Supply rail for the high-side FET gate drive. The voltage should be at least one gate threshold above the regulator input voltage to properly turn on the high-side FET. HG (Pin 2): Gate drive for the high-side N-channel FET. This signal is interlocked with LG to avoid shoot-through. SW/CSH (Pin 3): Return path for the high-side FET driver and top Kelvin sense point for the load current. Connect this pin as close as possible to the drain of the low-side FET with a separate trace. Also used along with CSL for zero crossing detection. CSL (Pin 4): Bottom sense point for the load current. Connect this as close as possible to the source of the low-side FET with a separate trace. ILIM (Pin 5): Current limit threshold setting. This pin sources a fixed 20 µA current. A resistor of appropriate value should be connected between this pin and the drain of the low-side FET. FPWM (Pin 6): Control mode select. An open circuit at this pin allows the IC to operate in skip mode at light loads. A logic low or connection to ground forces PWM operation at all times. This pin should not be pulled up to any voltage above 3.0V. SNS (Pin 7): Output voltage sense pin. Connect this pin as close as possible to the positive terminal of the output capacitor with a separate trace. This pin connects to an internal FET that discharges the output capacitor during shutdown. FREQ/SYNC (Pin 8): Switching frequency select pin and input for external clock. Connect a resistor from this pin to ground to determine switching frequency. Alternatively, a logic level clock signal between 200 kHz and 1.5 MHz can be applied to this pin through a 100 pF DC blocking capacitor to set the switching frequency. TRACK (Pin 9): Tracking pin. To force the output of the LM3495 to track another power supply, connect a resistor divider (smaller than 10 kΩ for better precision) from the output of the other supply directly to this pin. When not used, this pin should be connected directly to the VLIN5 pin. FB (Pin 10): Feedback pin. Connecting a resistor divider from the output voltage to this pin sets the DC level of the output voltage. COMP/SD (Pin 11): Output of the error amplifier. The voltage level on this pin is compared with an internally generated ramp signal to determine the duty cycle. This pin is necessary for compensating the control loop. This pin must be left floating for the converter to regulate the output voltage in steady state. Forcing this pin below 0.3V shuts down the regulator. SGND (Pin 12): Signal ground. Ground connection for the low power analog circuitry. Connect this pin to the PGND pin with a separate trace. VIN (Pin 13): Input voltage. Input to an internal 4.7V linear regulator. Bypass this pin with a minimum 1 µF ceramic capacitor. VLIN5 (Pin 14): Output of the internal 4.7V linear regulator. Provides power to the high-side bootstrap and low-side driver. Bypass this pin with a 2.2 µF ceramic capacitor to PGND. LG (Pin 15): Gate drive for the low-side N-channel FET. This signal is interlocked with HG to avoid shoot-through. PGND (Pin 16): Ground connection for the power circuitry. Connect to the source of the low-side FET and the output capacitor with heavy traces or a copper plane. 2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN, ILIM −0.3V to 20V SW/CSH (3) −0.5V to 20V BOOST, HG −0.3V to 25V BOOST to SW −0.3V to 6V FB −0.3V to 2V TRACK, FREQ, FPWM, VLIN5, SNS, LG, CSL −0.3V to 6V −65°C to +150°C Storage Temperature Soldering Information ESD Rating (1) (2) (3) (4) Lead Temperature (soldering, 10 sec) 260°C Infrared or Convection (15 sec) 235°C (4) 2kV Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. An extended negative voltage limit of –2V applies for a duration of 20 ns per switching cycle The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Operating Ratings (1) Supply Voltage Range (VIN) 2.9V to 18V BOOST to SW 2.5V to 5.5V −40°C to +125°C Junction Temperature (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 3 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Specifications with standard type are for TJ = 25°C only; limits in boldface type apply over the full Operating Junction Temperature (TJ) range. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise indicated, VIN = 12V. Symbol Min Typ (1) Max -20°C to 85°C 0.594 0.6 0.606 -40°C to 125°C 0.591 0.6 0.609 Parameter Conditions Units SYSTEM PARAMETERS VFB ΔVFB/VFB VON IQ IILIM VILIM-MAX ISD VHICCUP FB Pin Voltage Line Regulation 2.9V < VIN < 18V, COMP/SD = 1.5V 0.1 Load Regulation 1.1V < COMP/SD <1.8V 0.1 UVLO Thresholds % 2.55 2.6 2.7 VIN Falling 2.26 2.3 2.45 COMP/SD > 0.3V, Not switching 1.8 Quiescent Current COMP/SD < 0.3V, Shutdown, VIN = 18V 33 ILIM Pin Source Current 18 Maximum Current Limit Sense Voltage COMP/SD Pin Pull-up current % VIN Rising Operating VIN Current 20 2 COMP/SD Pin Hiccup Threshold V mA µA 22 200 COMP/SD = 0V V µA mV 2.6 µA 2 V tDELAY Hiccup Delay 16 Cycles tCOOL Cool Down Time Until Restart 4096 Cycles Internal Soft start Time 400 Cycles tSS VOVP Over Voltage Protection Threshold As a % of nominal output voltage IFPWM FPWM Pin Pull-up Current FPWM = 0V 4.5 VFPWM-LO 116 125 132 % µA FPWM Operation Threshold FPWM Voltage Falling 0.9 V RSNS SNS Pin Input Resistance SNS = 1.5V, COMP/SD > 0.3V 30 kΩ RDIS SNS Pin Discharge FET RDSON SNS = 1.5V, COMP/SD = 0V BOOST Pin Leakage Current BOOST - SW = 5.5V 25 nA RDS1 High-Side FET Driver Pull-up ON resistance BOOST - SW = 4.5V 4.5 Ω RDS2 High-Side FET Driver Pull-down ON resistance BOOST - SW = 4.5V 0.9 Ω RDS3 Low-Side FET Driver Pull-up ON resistance VLIN5 = 5.5V 1.4 Ω RDS4 Low-Side FET Driver Pull-down ON resistance VLIN5 = 5.5V 0.7 Ω 350 440 530 Ω GATE DRIVE IBOOST OSCILLATOR RADJ = 150 kΩ fSW PWM Frequency RADJ = 54.9 kΩ RADJ = 17.8 kΩ 200 450 500 550 kHz 1500 VSYNC-HI Threshold for SYNC on FREQ Pin SYNC Voltage Rising 1.2 V VSYNC-LO Threshold for SYNC on FREQ Pin SYNC Voltage Falling 0.3 V tON-SKIP On Time During Skip Mode VO = 1.5V, fSW = 500 kHz 125 ns tON-MAX Adaptive Maximum On-time Limit VO = 1.5V, fSW = 500 kHz 750 ns tOFF-MIN Minimum Off-time 300 ns ERROR AMP gM BW-3dB IFB (1) 4 Transconductance 750 µmho Open Loop Bandwidth COMP/SD Floating 5 MHz FB Pin Bias Current VFB = 0.6V 1 nA Typical specifications represent the most likely parametric norm at 25°C operation. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 Electrical Characteristics (continued) Specifications with standard type are for TJ = 25°C only; limits in boldface type apply over the full Operating Junction Temperature (TJ) range. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise indicated, VIN = 12V. Symbol ISOURCE Parameter Conditions Min Typ (1) Max Units COMP/SD Pin Source Current VFB = 0.5V, COMP/SD = 1.5V 40 µA COMP/SD Pin Sink Current VFB = 0.7V, COMP/SD = 1.5V 40 µA VCOMP-HI COMP/SD Pin Voltage High Clamp VFB = 0.5V 2 V VCOMP-LO COMP/SD Pin Voltage Low Clamp VFB = 0.7V 0.9 V 0.6 V 15 mV VIN = 12V, VLIN5 Current = 25 mA 4.72 V VIN = 3.3V, VLIN5 Current = 25 mA 3.0 V ISINK TRACKING VTEND VTRACK-OS Track End Threshold Track to FB Offset TRACK = 0.55V INTERNAL VOLTAGE REGULATOR VVLIN5 Voltage at VLIN5 Pin (2) LOGIC INPUTS AND OUTPUTS VSD-HI COMP/SD Pin Logic High Trip Point COMP/SD Pin Voltage Rising VSD-LO COMP/SD Pin Logic Low Trip Point COMP/SD Pin Voltage Falling 0.3 0.2 0.4 V 0.26 V THERMAL CHARACTERISTICS (2) θJA Junction-to-Ambient Thermal Resistance 155 °C/W TSD Thermal Shutdown Threshold 150 °C TSD-HYS Thermal Shutdown Hysteresis 15 °C VLIN5 provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 5 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics VIN = 12V unless specified, TA = 25°C unless specified. 6 FB Reference Voltage vs Temperature Switching Frequency vs Temperature Figure 2. Figure 3. VLIN5 Voltage vs Temperature Error Amplifier Transconductance vs Temperature Figure 4. Figure 5. VLIN5 Voltage vs VIN Efficiency in SKIP Mode VO = 2.2V, IO = 10 mA to 500 mA BOM in Table 2 Figure 6. Figure 7. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 Typical Performance Characteristics (continued) VIN = 12V unless specified, TA = 25°C unless specified. Efficiency in FPWM Mode VO = 1.0V, IO = 0.5A to 7A BOM in Table 1 Efficiency in FPWM Mode VO = 2.2V, IO = 0.5A to 7A BOM in Table 2 Figure 8. Figure 9. Load Transient Response VIN = 3.3V, VO = 2.2V BOM in Table 2 Load Transient Response VIN = 12V, VO = 1.0V BOM in Table 1 Figure 10. Figure 11. Soft-Start in SKIP Mode VIN = 12V, VO = 1.0V, IO = 0A BOM in Table 1 Soft-Start in FPWM Mode VIN = 3.3V, VO = 2.2V, IO = 0A BOM in Table 2 Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 7 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) VIN = 12V unless specified, TA = 25°C unless specified. 8 Soft-Start in FPWM Mode VIN = 12V, VO = 1.0V, IO = 5A BOM in Table 1 Soft-Start in FPWM Mode VIN = 3.3V, VO = 2.2V, IO = 5A BOM in Table 2 Figure 14. Figure 15. Soft-Start with Output Pre-bias VIN = 12V, VO = 1.0V, IO = 0A BOM in Table 1 Soft-Start with Output Pre-bias VIN = 3.3V, VO = 2.2V, IO = 0A BOM in Table 2 Figure 16. Figure 17. Shutdown VIN = 12V, VO = 1.0V, IO = 0A BOM in Table 1 Shutdown VIN = 12V, VO = 1.0V, IO = 5A BOM in Table 1 Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 Typical Performance Characteristics (continued) VIN = 12V unless specified, TA = 25°C unless specified. FA to SYNC Transition Clock Starts on Logic Low BOM in Table 1 FA to SYNC Transition Clock Starts on Logic High BOM in Table 1 Figure 20. Figure 21. SYNC to FA Transition Clock Ends on Logic Low BOM in Table 1 SYNC to FA Transition Clock Ends on Logic High BOM in Table 1 Figure 22. Figure 23. Tracking With Equal Soft Start Time VIN = 12V, VO = 1.0V, No Load BOM in Table 1 Tracking With Equal Soft Start Time VIN = 5V, VO = 2.2V, No Load BOM in Table 2 Figure 24. Figure 25. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 9 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) VIN = 12V unless specified, TA = 25°C unless specified. 10 Tracking With Equal Slew Rate VIN = 12V, VO = 1.0V, No Load BOM in Table 1 Tracking With Equal Slew Rate VIN = 5V, VO = 2.2V, No Load BOM in Table 2 Figure 26. Figure 27. SKIP to FPWM Transition VIN = 12V, VO = 1.0V, IO = 5A BOM in Table 1 fSW vs RFRQ VIN = 12V, VO = 1.0V, No Load BOM in Table 1 Figure 28. Figure 29. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 Typical Application Circuit CF 1 F D1 CDD VIN = 12V ± 10% 2.2 F MODE FPWM VIN VLIN5 BOOST CB FREQ/SYNC CSYNC 100 pF RFRQ SW/CSH TRACK RILIM CC L1 VO = 1.2V, 10A ILIM 3.32 k LG 1 H Q2 10 m CO COMP/SD 1.5 k 22 F 25V Q1 HG LM3495 RC CIN 54.9 k VLIN5 Shutdown Signal 0.1 F 25V CINX 0.1 F 10 nF CSL 2 x 100 F 6.3V RFB1 FB 10 k RFB2 SNS SGND PGND 10 k Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 11 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Block Diagram TRACK VLIN5 VIN INTERNAL 4.7V REGULATOR INTERNAL SOFTSTART VREF = 0.6V BOOST FROM LG IRAMP SHOOTTHROUGH PROTECT FB IFREQ + + + - RAMP GENERATOR AND SLOPE COMPENSATION EA gm HICCUP HG COMP /SD - SW/ CSH - + + x4 CLAMPED: LO 0.9V HI 2.0V 2V 20 PA 2 PA + PWM LOGIC CONTROL AND DRIVER CONTROL PWM COMP - - ILIM + IRAMP TO SHOOTTHROUGH PROTECT VLIN5 OSCILLATOR AND SYNCHRONIZATION CONTROL LG FREQ/ SYNC IFREQ ADAPTIVE DUTY CYCLE AND SKIP MODE CONTROL CSL 5 PA SHUTDOWN SNS 12 SGND FPWM Submit Documentation Feedback PGND Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 APPLICATIONS INFORMATION THEORY OF OPERATION The LM3495 is an advanced, current mode PWM synchronous controller. Unlike traditional peak current mode controllers which sense the current while the high-side FET is on, the LM3495 senses current while the low-side FET is on. The LM3495 then emulates the peak current waveform and uses that information to regulate the output voltage. High-side ON pulses as low as 50 ns are possible to achieve low duty cycle operation. The LM3495 therefore enjoys both excellent line transient response and the ability to regulate low output voltages from high input voltages. START UP The LM3495 will begin to operate when the COMP/SD pin is open-circuited and the voltage at the VIN pin has exceeded 2.6V. Once these two conditions have been met an internal soft start begins and lasts for 400 switching cycles. When soft start is complete the converter enters steady state operation. Current limit is enabled during soft start to protect against a short circuit at the output. START UP INTO OUTPUT PRE-BIAS If the output capacitor of the LM3495 regulator has been charged up to some pre-bias level before the converter is enabled, the soft start will ramp the output voltage from the pre-bias level up to the target output voltage without ever discharging the output capacitor. Note that the pre-bias voltage must not be greater than the target output voltage of the LM3495, otherwise the LM3495 will pull the pre-bias supply down during steady state operation. A zero-cross comparator prevents the current in the inductor from reversing during soft start and prevents discharge of the output capacitor through the low-side FET. In FPWM mode, once soft-start is complete the zero-cross threshold decreases over 16 cycles and then is disabled, allowing the converter to sink current at the output if needed. The LM3495 contains an internal N-FET with an on-resistance of approximately 500Ω connected between the SNS and PGND pins. When the converter is disabled, this FET is turned on to discharge the output capacitor in a controlled fashion. If the LM3495 is used in a system with a pre-bias at the output the power supply providing the pre-bias must be able to supply enough current for the 500Ω load that the internal FET creates. TRACKING The LM3495 can track the output of a master power supply during soft start by connecting a resistor divider to the TRACK pin (Figure 30). In this way, the output voltage slew rate of the LM3495 will be controlled by the master supply for loads that require precise sequencing. Because the output of the master supply is divided down, the output voltage of the LM3495 must be lower than the voltage of the master supply in order to track properly. When the tracking function is not being used, the TRACK pin should be connected directly to the VLIN5 pin. Master Power Supply VOUT1 VOUT2 RT2 VSS TRACK SNS LM3495 RFB2 RT1 FB VFB RFB1 Figure 30. Tracking Circuit Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 13 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com One way to use the tracking feature is to design the tracking resistor divider so that the master supply output voltage (VOUT1) and the LM3495 output voltage (VOUT2) both rise together and reach their target values at the same time. For this case, the equation governing the values of the tracking divider resistors RT1 and RT2 is: RT1 0.65V = VOUT1 RT1 + RT2 (1) The above equation is set equal to 0.65V in order to ensure that the final value of the track pin voltage exceeds the reference voltage of the LM3495, and this 50 mV offset will cause the LM3495 output voltage to reach regulation slightly before the master supply. A value of 10 kΩ 1% is recommended for RT2 as a good compromise between high precision and low quiescent current through the divider. If the master supply voltage VOUT1 is 5V, for example, then the value of RT1 needed to give the two supplies identical soft start times would be 1.5 kΩ 1%. A timing diagram for this example, the equal soft start time case, is shown in Figure 31. VOUT1 (Master Supply) VOUT2 (LM3495) Figure 31. Tracking with Equal Soft Start Time Alternatively, the tracking feature can be used to create equal slew rates between the output voltages of the LM3495 and the master supply. This method ensures that the output voltage of the LM3495 always reaches regulation before the output voltage of the master supply. In this case, the tracking resistors can be determined based on the following equation: 0.6V = VOUT2 RT1 RT1 + RT2 (2) Again, a value of 10 kΩ 1% is recommended for RT2. For the example case of VOUT1 = 5V and VOUT2 = 1.8V, RT1 would be 5.62 kΩ 1%. A timing diagram for this example, the case of equal slew rates, is shown in Figure 32. VOUT1 (Master Supply) VOUT2 (LM3495) Figure 32. Tracking with Equal Slew Rates 14 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 FPWM MODE OPERATION The LM3495 operates under forced PWM when the FPWM pin is connected to ground. While in FPWM operation, the LM3495 controls the output voltage by adjusting the duty cycle of the power FETs with trailing edge PWM. The output inductor and capacitor filter the square wave produced as the power FETs chop the input voltage, thereby creating a regulated output voltage. The DC level of the output voltage can be set anywhere from 0.6V up to 5.5V, and is determined by a pair of feedback resistors using the following equation: VO = 0.6V x RFB1 + RFB2 RFB1 (3) In steady state FPWM mode, the inductor current can flow from the drain to the source of the low-side FET, keeping the converter in continuous conduction mode (CCM) at all times. CCM has the advantage of constant frequency and nearly constant duty cycle (D = VO/VIN) over all load conditions, and it allows the converter to sink current at the output if needed. The switching frequency of the internal oscillator is set by a resistor, RFRQ, connected from the FREQ/SYNC pin to ground. The proper resistor for a desired switching frequency, fSW, can be determined by using the following equation: RFRQ = 25.26 x 103 k:, fSW in kHz fSW - 48.4 (4) SKIP MODE OPERATION If the FPWM pin is left open-circuited, the LM3495 can enter into SKIP mode operation, delivering better efficiency at light loads. As long as the inductor current is positive (flowing from the switch node to the output node), SKIP mode is identical to FPWM mode. Once the inductor current becomes negative, however, an internal zero-cross comparator will disable the low-side FET. This 'diode-emulation' mode allows the converter to operate in discontinuous conduction mode (DCM). In DCM, the duty cycle decreases as the load current decreases. A minimum on-time comparator prevents the duty cycle during DCM from decreasing below 80% of the steady state duty cycle, D. The converter will allow one on-time pulse, causing the output voltage to rise and the COMP/SD voltage to droop. If COMP/SD drops below the skip cycle comparator threshold of 1.05V, the control logic will disable the high-side FET for one cycle, effectively skipping a pulse. This skipping action continues until the COMP/SD voltage rises above the skip cycle threshold. Multiple pulses can be skipped depending on load, input voltage, and output voltage. Switching frequency is not fixed during SKIP Mode, but energy is saved because the high and low-side FETs are driven less frequently than in FPWM mode. In SKIP mode the regulator cannot sink current at the output. SKIP TO FPWM TRANSITION The LM3495 employs circuitry to transition from SKIP mode to FPWM mode with minimal discontinuity in inductor current and output voltage. When the FPWM pin is grounded, the threshold of the zero-cross comparator decreases from 0V to -9.9 mV over fifteen switching cycles. After fifteen cycles have elapsed, the zero-cross comparator is disabled entirely and the circuit switches to FPWM mode. Note that "on-the-fly" changes from FPWM mode to SKIP mode are not recommended due to the possibility of discontinuity in the inductor current and/or output voltage. FREQUENCY SYNCHRONIZATION The switching action of the LM3495 can be synchronized to external clocks or other fixed frequency signals in the range of 200 kHz to 1.5 MHz. The external clock should be applied through a 100 pF coupling capacitor, CSYNC, as shown in Figure 33. In order for the LM3495 to synchronize properly, the external clock should exceed 1.2V on each rising edge and remain above 1.2V for at least 100 ns. The external clock should also fall below 0.3V on each falling edge, and remain below 0.3V for at least 100 ns. Circuits that use an external clock should still have a resistor, RFRQ, connected from the FREQ/SYNC pin to signal ground. RFRQ should be selected using the equation from FPWM MODE OPERATION to match the external clock frequency. This allows the regulator to continue operating at approximately the same switching frequency if the external clock fails and the coupling capacitor on the clock side is grounded or pulled to a logic high. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 15 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com If the external clock fails low, timeout circuits will prevent the high-side FET from staying off for longer than 1.5 times the switching period (Switching period TSW = 1/fSW). At the end of this timeout period the regulator will begin to switch at the frequency set by RFRQ. If the external clock fails high, timeout circuits will again prevent the high-side FET from staying off longer than 1.5 times the switching period. After this timeout period, the internal oscillator takes over and switches at a fixed 1 MHz until the voltage on the FREQ/SYNC pin has decayed to approximately 0.6V. This decay follows the time constant of CSYNC and RFRQ, and once it is complete the regulator will switch at the frequency set by RFRQ. Care must be taken to prevent errant pulses from triggering the synchronization circuitry. In applications that will not synchronize to an external clock, CSYNC should be connected from the FREQ/SYNC pin to signal ground as a noise filter. When a clock pulse is first detected, the LM3495 begins switching at the external clock frequency. Noise or a short burst of clock pulses can result in off times as long as 7.5 µs for the high-side FET if they occur while the internal synchronization circuits are adjusting. LM3495 CSYNC External Clock FREQ/SYNC 100 pF RFRQ Figure 33. Clock Synchronization Circuit MOSFET GATE DRIVE The LM3495 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Power for the high-side driver is supplied through the BOOST pin. For the high-side gate drive to fully turn on the top FET, the BOOST pin voltage must be at least one threshold voltage, VGS(th), greater than VIN. This voltage is supplied from a local charge pump structure which consists of a Schottky diode and 0.1 µF capacitor, shown in Figure 34. Both the bootstrap and the low-side FET driver are fed from VLIN5, which is the output of a 4.7V internal linear regulator. This regulator has a dropout voltage of approximately 1V. If VIN drops below 4V, an internal switch shorts the VIN and VLIN5 pins together. The drive voltage for the top FET driver is therefore VLIN5-VD, where VD is the drop across the Schottky diode D1. This information is needed to select the type of MOSFETs to be used. D1 VLIN5 BOOST HG VIN CBOOT Q1 LM3495 L1 SW/CSH LG Q2 + Co Figure 34. Bootstrap Circuit INPUT VOLTAGE BELOW 5.5V The LM3495 includes an internal 4.7V linear regulator connected from the VIN pin to the VLIN5 pin. This linear regulator feeds the logic and FET drive circuitry. For input voltages less than 5.5V, the VIN and VLIN5 pins can be shorted together externally. The external short circuit bypasses both the internal linear regulator and the internal PMOS switch, allowing the full input voltage to be used for driving the power FETs and minimizing conduction loss in the LM3495 itself. For voltage inputs that range above and below 5.5V the LM3495 must not use a short from VIN to VLIN5. 16 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 UNDER VOLTAGE LOCK-OUT The 2.6V turn-on threshold on the voltage at VIN has a built in hysteresis of 300 mV. If input voltage drops below 2.3V the chip enters under voltage lock-out (UVLO) mode. UVLO consists of turning off both the top and bottom FETs and remaining in that condition until input voltage rises above 2.6V. BOOTSTRAP DIODE SELECTION Schottky diodes are the preferred choice for the bootstrap circuit because of their low forward voltage drop. For circuits that will operate at high ambient temperature the Schottky diode datasheet must be read carefully to ensure that the reverse leakage current at high temperature does not increase enough to deplete the charge on the bootstrap capacitor while the high-side FET is off. Some Schottky diodes increase their reverse leakage by as much as 1000x at their upper temperature limit. Fast recovery and PN junction diodes maintain low reverse leakage even at high ambient temperature. For high ambient temperature operation Schottky diodes with low leakage across temperature or fast recovery type diodes should be used. OVER VOLTAGE PROTECTION The LM3495 will shut down if the output voltage exceeds 125% of the steady state target voltage for longer than 4 µs. The high-side FET is turned off and the low-side FET is turned on. The LM3495 will remain in this condition until either the VIN pin voltage is cycled to ground, or the COMP/SD pin voltage is pulled to below 0.3V and then released. Either of these reset mechanisms will cause the device to perform a soft-start. LOW-SIDE CURRENT LIMIT The current limit of the LM3495 operates by sensing the current in the low-side FET while the load current, IO, circulates through it. The low-side FET drain-to-source voltage, VDS, is compared against the voltage of a fixed, internal 20 µA current source and a user-selected resistor, RILIM. The value of RILIM for a desired current limit threshold, ICL, can be selected with the following equation: RILIM = ICL x RDSON-LO 20 PA (5) RILIM is connected between the switch node and the ILIM pin. A current limit event is sensed when VDS exceeds VILIM. (VILIM = 20 µA x RILIM). The high-side switch is disabled for the following cycle and the low-side FET is kept on during this time. During long duration current limit conditions or a short circuit the output voltage droops. This in turn causes the COMP/SD pin voltage to rise. If the COMP/SD pin voltage exceeds 2V and a high-side FET on-pulse is skipped, the LM3495 increments a 4 bit counter. If 16 high-gate pulses are skipped consecutively while COMP/SD stays above 2V, the LM3495 will enter hiccup mode. The counter is reset when the COMP/SD pin goes below 2V. During soft-start the cycle skipping function of the low-side current limit is active, but the ability to enter hiccup mode is disabled. CURRENT LIMIT SENSE RESISTOR For applications that require a higher degree of accuracy for the low-side current limit, a dedicated current sense resistor can be added between ground and the source of the low-side FET. Figure 35 shows the circuit connection when using a dedicated current limit sensing resistor, RSNS. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 17 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com VIN HG Q1 L1 SW/CSH LM3495 LG Q2 RILIM ILIM RSNS CSL Figure 35. Current Limit Sense Resistor When using a dedicated current limit sensing resistor, the equation governing the low-side current limit becomes: RILIM = ICL x RSNS 20 PA (6) MAXIMUM CURRENT SENSE In order to keep the low-side current sense amplifier within its linear range, the peak sense voltage, VSNS, between the CSL and SW/CSH pins should remain below 200 mV. VSNS = IPK x (RDSON-LO + RSNS) (7) The value IPK can be determined by following the equations in the Output Inductor. HIGH-SIDE CURRENT LIMIT The LM3495 employs a second comparator that monitors the voltage across the high-side FET when it is on. This provides protection against a short circuit at the switch node, which the low-side current limit cannot detect. If the drain-to-source voltage of the high-side FET exceeds 500 mV while the FET is on, the LM3495 will immediately enter hiccup mode. A 200 ns blanking period after the high-side FET turns on is used to prevent switching transient voltages from tripping the high-side current limit without cause. HICCUP MODE During hiccup mode, the LM3495 disables both the high-side and low-side FETs and begins a cool down period of 4096 switching cycles. At the conclusion of this cool down period, the regulator performs an internal 400 cycle soft start identical to the soft start at turn-on. During soft start only the high-side current limit can put the LM3495 into hiccup mode. low-side current cannot put the LM3495 into hiccup mode during soft start, although it can limit duty cycle. If a short at the output persists when soft start is done, the part will begin counting high-side pulses skipped due to the low-side current limit and will re-enter hiccup mode 16 cycles later. The long term effect observed will be 4096 cycles with the power FETs disabled, and then 416 (400 + 16) cycles where they are enabled. The hiccup protection mode is designed to protect the external components of the circuit (output inductor, FETs and input voltage source) from thermal stress. For example, assume that the low–side current limit is10A. Once in hiccup mode the effective duty cycle for the high-side FET and output inductor will be D*(416/4096). For the low-side FET it will be (1-D)(416/4096). This means that even under the worst case conditions (minimum switching frequency and maximum duty cycle, DMAX = 96%), the average current through the inductor and highside FET will be 975 mA and the average current seen by the low-side FET will be 40 mA. 18 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 PARALLEL LOW-SIDE SCHOTTKY DIODE Many synchronous buck regulators include a Schottky diode in parallel with the low-side power FET. The low forward drop and short reverse recovery time of Schottky diodes can improve efficiency by preventing the FET's body diode from turning on. This technique is most effective in circuits with output currents of 5A or less. The parallel Schottky diode must be placed as close as possible to the power FET to prevent trace inductance from negating the gains in efficiency. ADAPTIVE DUTY CYCLE CLAMP The adaptive duty cycle clamp is an extra layer of protection used during high current conditions or large load transients. When a high-side pulse is skipped due to current limit, the output voltage tends to decrease rapidly. The steady state control loop of the LM3495 responds by commanding a higher duty cycle at the next high-side turn-on. The result is a combination of high voltage across the output inductor and long duty cycles that could result in inductor saturation. The adaptive duty cycle clamp prevents inductor saturation by providing a dynamic maximum duty cycle, DCLAMP. The clamp is based on the sensed input and output voltages. DCLAMP can be predicted with the following equation: DCLAMP = 3.2 x VO VIN (8) (9) DCLAMP cannot exceed 100% SHUTDOWN The LM3495 can be put into a low power shutdown mode by bringing the voltage at the COMP/SD pin below 0.3V. A signal-level BJT or FET can be controlled by most CMOS or TTL logic signals to perform this function. The collector-to-emitter or drain-to-source capacitance should be less than 20 pF to minimize the effect on the control loop compensation. During shutdown, both the high-side and low-side FETs are disabled. The output voltage is discharged through the SNS pin by an internal 500Ω FET. THERMAL SHUTDOWN The LM3495 will enter a thermal shutdown state if the die temperature exceeds 150°C. Both the high-side and low-side power FETs are turned off, the output voltage is discharged through an internal 500Ω FET, and the IC will remain in this condition until the die temperature has dropped to approximately 135°C. At this point the LM3495 will perform a soft-start. Design Considerations The most common circuit controlled by the LM3495 is a non-isolated, synchronous buck regulator. The buck regulator steps down the input voltage and has a duty cycle, D, of: D= VO VIN (10) The following is a design procedure for selecting all the components in the Typical Application circuit on the front page. This circuit delivers a 1.2V ± 1% output voltage at output currents up to 10A from an input voltage of 12V ± 10%. This circuit is typical of a point-of-load (POL) module. A BOM for this typical application is listed in Table 3 at the end of this datasheet. SWITCHING FREQUENCY The selection of switching frequency is based on the tradeoffs between size, cost, and efficiency. In general, a lower frequency means larger, more expensive inductors and capacitors will be needed. A higher switching frequency generally results in a smaller but less efficient solution, as the power FET gate capacitances must be charged and discharged more often in a given amount of time. For this application, a frequency of 500 kHz was selected because the space on a POL circuit board is limited. This frequency is a good compromise between the size of the inductor and FETs, transient response, and efficiency. Following the equation given for RFRQ in the Applications Information section, a 54.9 kΩ 1% resistor should be used to switch at 500 kHz. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 19 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com MOSFETS Selection of the power FETs is governed by the same tradeoffs as switching frequency. Breaking down the losses in the high-side and low-side FETs is one way to determine relative efficiencies between different FETs. When using discrete SO-8 FETs the LM3495 is most efficient for output currents of 2A to 10A. Losses in the power FETs can be broken down into conduction loss, gate charging loss, and switching loss. Conduction, or I2R loss, PC, is approximately: PC = D (IO2 x RDSON-HI x 1.3) (High-Side MOSFET) PC = (1 - D) x (IO2 x (RDSON-LO x 1.3 + RSNS)) (Low-Side MOSFET) (11) (12) In the above equations RDSON-HI and RDSON-LO refer to on-resistance of the high-side and low-side FETs, respectively. RSNS is 0 if it is not used. The factor 1.3 accounts for the increase in FET on-resistance due to heating. Alternatively, the factor of 1.3 can be ignored and the on-resistance of the FET can be estimated using the RDSON vs Temperature curves in the FET datasheets. Gate charging loss, PGC, results from the current driving the gate capacitance of the power FETs and is approximated as: PGC = n x (VLIN5 – VD) x QG-HI x fSW (High-Side MOSFET) PGC = n x VLIN5 x QG-LO x fSW (Low-Side MOSFET) (13) (14) In the above equations QG-HI and QG-LO refer to the gate charge of the high-side and low-side FETs, respectively. The factor ‘n’ is the number of FETs (if multiple devices have been placed in parallel) and QG is the total gate charge of the FET. If different types of FETs are used, the ‘n’ term can be ignored and their gate charges summed to form a cumulative QG. Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the LM3495 and not in the FET itself. Further loss in the LM3495 is incurred as the gate driving current passes through the internal linear regulator. This loss term is factored into the Chip Operating Loss portion of the Efficiency Calculations section. Switching loss, PSW, occurs during the brief transition period as the FET turns on and off. During the transition period both current and voltage are present in the channel of the FET. The loss can be approximated as: PSW = 0.5 x VIN x IO x (tR + tF) x fSW (15) Where tR and tF are the rise and fall times of the FET. Switching loss is calculated for the high-side FET only. Switching loss in the low-side FET is negligible because the body diode of the low-side FET turns on before the FET itself, minimizing the voltage from drain to source before turn-on. For this example, the maximum drain-to-source voltage applied to either FET is 13.2V. The maximum drive voltage at the gate of the high-side FET is 4.5V, and the maximum drive voltage for the low-side FET is 5V. Any FET selected must be able to withstand 13.2V plus any ringing from drain to source, and be able to handle at least 5V plus ringing from gate to source. One good choice of FET for the high-side has an RDSON of 9.6 mΩ, total gate charge QG of 11 nC, and rise and fall times of 5 and 8 ns, respectively. For the low-side FET, a good choice has an RDSON of 3.4 mΩ and gate charge of 33 nC. These values have been taken from the FET datasheets with a VGS of 4.5V. OUTPUT INDUCTOR The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is based on the desired ripple current, ΔiO, which flows in the inductor along with the load current. This ripple current will flow through the ESR and impedance of the output capacitor to create the output voltage ripple, ΔvO. Due to the unique control architecture of the LM3495, a second requirement for minimum inductance must be used based on the RDSON of the low-side FET and the desired switching frequency. As with switching frequency, the inductance used is a tradeoff between size and cost. Larger inductance means low current ripple and hence low output voltage ripple. However, less inductance results in smaller, less expensive devices. An inductance that gives a ripple current of 30% to 40% of the maximum load current is a good starting point (ΔiO = 30% to 40%*IO). Minimum inductance should be calculated from this value, using the maximum input voltage, as: LMIN1 = 20 VIN(MAX) - VO xD fSW x 'iO (16) Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 By calculating in terms of amperes, volts, and megahertz, the inductance value will come out in micro henries. The second minimum inductance equation specific to the LM3495 is: 64 x (RDSON-LO + RSNS) LMIN2 = x fSW VIN VIN + 2 (17) By calculating in terms of milliohms and kilohertz the inductance value will come out in micro henries. For this design: LMIN1 = 13.2V - 1.2V x 0.1 = 0.8 PH 500 kHz x 3A LMIN2 = 64 x 3.4 m: 12V x = 0.4 PH 500 kHz 12V + 2 (18) Whichever equation gives the higher value for inductance is the one which should be followed. The second criterion for selecting an inductor is the peak current carrying capability. This is the level above which the inductor will saturate. In saturation the inductance drops off severely, often to 20% to 30% of the rated value. In a buck converter, peak current, IPK, is equal to the maximum load current plus one half of the ripple current. For this example: IPK = 10A + 1.5A = 11.5A (19) Hence an inductor must be selected that has a peak current rating greater than 11.5A and an average current rating greater than 10A. To ensure a robust design, the inductor selected should maintain approximately 50% of its rated inductance during the worst-case peak current from an output short circuit. For a low-side current limit the peak current during an output short circuit can be estimated as ICL plus Δi(O-MAX). Δi(O-MAX) is calculated by substituting zero for output voltage in the expression for ΔiO. Inductor core materials with soft saturation characteristics are preferred. One inductor that meets the peak current guidelines is an off-the-shelf 1.0 µH component that can handle a peak current of 18A and an average current of 14A. The inductor current ripple and peak inductor current should be recalculated for the selected inductance value, LACTUAL, by rearranging the equation for minimum inductance: 'iO = 'iO = VIN(max) - VO fSW x LACTUAL xD 13.2V - 1.2V x 0.1 = 2.4AP-P 0.5 MHz x 1 PH IPK = 10A + 2.4A/2 = 11.2A (20) OUTPUT CAPACITOR The output capacitor in a switching regulator is selected on the basis of capacitance, equivalent series resistance (ESR), size, and cost. An important specification in switching converters is the output ripple voltage, ΔvO. At 500 kHz the impedance of most capacitors is very small compared to ESR, hence ESR becomes the main selection guide. In this design the load requires a 1% ripple, which results in a ΔvO of 10 mVP-P. Maximum ESR is then: ESRMAX = 'VO 'iO (21) ESRMAX is 10 mΩ. Multi-layer ceramic, aluminum electrolytic, tantalum, solid aluminum, organic, and niobium capacitors are all popular in switching converters. Generally, by the time enough capacitors have been paralleled to obtain the desired ESR, the bulk capacitance is more than enough to supply the load current during a transient from no-load to full load. In this example the load could transition quickly from 0A to 5A, (or from 5A to 0A), so moderate bulk capacitance is needed. Two MLCC capacitors rated 100 µF, 6.3V each with ESR of 1.5 mΩ will work well. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 21 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com VLIN5 DECOUPLING CAPACITOR The VLIN5 pin should always be decoupled with a 2.2 µF, 10V-rated ceramic capacitor placed as close as possible to the VLIN5 and PGND pins of the LM3495. The decoupling capacitor should have a minimum X5R or X7R type dielectric to ensure that the capacitance remains stable over the expected voltage and temperature range. INPUT CAPACITOR The input capacitors to a buck regulator are used to smooth the large current pulses drawn by the inductor and load when the high-side FET is on. Due to this large AC stress, input capacitors are usually selected on the basis of their AC rms current rating rather than bulk capacitance. Low ESR is beneficial because it reduces the power dissipation in the capacitors. Although any of the capacitor types mentioned in the OUTPUT CAPACITOR section can be used, MLCCs are common because of their low ESR and because in general the input to a buck converter does not require as much bulk capacitance as the output. Input current, Irms, can be calculated using the following equation: Irms = IO x D(1 - D) (22) A good estimate for the maximum AC rms current is one-half of the maximum load current. For this example, the rms input current can be estimated as 3.5A. Regardless of the type and number of capacitors used, every design will benefit from the addition of a 0.1 µF to 1 µF ceramic capacitor placed as close as possible to the drain of the high-side FET and the source of the low-side FET. In most applications for POL power supplies, the input voltage is the output of another switching converter. This output often has a lot of bulk capacitance. One 22 µF MLCC provides enough local smoothing and keeps the input impedance high enough to prevent power supply interaction from the source. For switching power supplies, the minimum quality dielectric that should be used is X5R. The preferred capacitor voltage rating for a 12V input voltage is 25V, due to the drop-off in capacitance of MLCCs under a DC bias. Capacitors with a 16V rating can still be used if size and cost are limiting factors. For this example the current rating of each of the capacitors should be at least 3Arms. The ESR of large-value ceramic caps is usually below 10 mΩ, which keeps the heating to a minimum. CURRENT LIMIT For this design, the trip point for the current limit circuitry should be below the peak current rating of the output inductor, which is 18A. To account for the tolerance of the internal current source, the change in the RDSON of the low-side FET, and to prevent excessive heating of the inductor, a target of 15A has been chosen. A 3.8A margin exists between the expected 11.2A peak current and the current limit threshold to allow for line and load transients. Following the equation from the Applications Information section the value used for RLIM should be 3.32 kΩ 1%. CONTROL LOOP COMPENSATION The LM3495 uses emulated peak current-mode PWM control to correct changes in output voltage due to line and load transients. This unique architecture combines the fast line transient response of peak current mode control with the ability to regulate at very low duty cycles. As a further advantage, the small signal characteristics of emulated peak current mode control are almost identical to those of traditional peak current mode control, and hence compensation can be selected using nearly identical calculations. The control loop is comprised of two parts. The first is the power stage, which consists of the duty cycle modulator, output filter, and the load. The second part is the error amplifier, which is a transconductance (gM) amplifier with a typical transconductance of 750 µmho and a typical output impedance of 72 MΩ. Figure 36 shows the regulator and voltage control loop components. 22 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 RL L VO + C O VIN RO + RC RFB2 + - VRAMP GM VC + C1 C2 R1 + - 0.6V RFB1 Figure 36. Power Stage and Error Amp One popular method for selecting the compensation components is to create Bode plots of gain and phase for the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the regulator easy to determine. Software tools such as Excel, MathCAD, and Matlab are useful for observing how changes in compensation or the power stage affect system gain and phase. The power stage in an emulated peak current mode buck converter consists of the DC gain, APS, a low frequency pole, fP, the ESR zero, fZ, and a higher frequency pole, fL, set by the ratio of the sensed current ramp to the emulated current ramp. The power stage transfer function (also called the Control-to-Output transfer function) can be written: GPS = APS x s 1+ Z Z s s (1 + Z )(1 + Z ) P L (23) Where the DC gain is defined as: APS = RO GI x RS x 1+ 1 (RO + RL) x (mC ± 0.5) L1 x fSW where • • • Se = Sn = ZZ = RS = RDSON-LO + RSNS mC = Se / Sn GI = 4 (24) ( V16 + 0.125) x f IN SW (25) VIN x GI x RS L1 (26) 1 R C x CO (27) The low frequency pole is: mC - 0.5 1 + ZP = RO x CO L x CO x fSW (28) Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 23 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com And the higher frequency pole is: ZL = fSW mC ± 0.5 (29) In the equation for APS, the output resistance, RO, is the output voltage divided by output current. DC gain is highest when output current is lowest. In order to design for the worst case, RO should be calculated for the minimum load current. For this example, no minimum load has been specified, so a load of 100 mA will be used (RO = 12Ω). 30 0 15 -30 POWER STAGE PHASE (°) POWER STAGE GAIN (dB) For this example, the value of DC gain is 24dB. The low frequency pole fP = ωP/ 2π is at 2.7kHz, the ESR zero fZ = ωZ/ 2π is at 1.06 MHz, and the higher frequency pole is at 48 kHz. Gain and phase plots for the power stage are shown in Figure 37. 0 -15 -30 -45 -60 100 1k 10k 100k 1M -60 -90 -120 -150 -180 100 FREQUENCY (Hz) 1k 10k 100k 1M FREQUENCY (Hz) Figure 37. Power Stage Gain and Phase The low frequency pole and higher frequency pole cause a roll-off in the gain of -20 dB/decade at lower frequency that increases to -40 dB/decade at higher frequency. The effect of the ESR zero is not seen because its frequency is beyond the switching frequency. If this loop were left uncompensated, the bandwidth would be 39 kHz and the phase margin 58°. This loop would be stable, but would suffer from poor regulation of the output voltage due to the low DC gain. In practice, this loop could change significantly due to the tolerances in the output inductor, output capacitor, changes in output current, or input voltage. Therefore, the loop is compensated using the error amplifier and a few passive components. In general the goal of the compensation circuit is to give high DC gain, a bandwidth that is between one-fifth and one-tenth of the switching frequency, and at least 45° of phase margin. The majority of both peak current mode and emulated peak current mode buck regulators can be compensated with just two components, R1 and C1, as shown in the Typical Application Circuit. For power stages where the ESR zero frequency is below one-half of the switching frequency a second capacitor, C2, may be needed to add another pole to the compensation. For power stages where the ESR zero frequency is beyond the control loop bandwidth, a compromise in bandwidth is needed to maintain good phase margin. The transfer function of the compensation block, GEA, can be derived by multiplying the impedance ZC = (R1 + 1/sC1)ll( 1/sC2) times the DC gain of the error amp to give the following equation: GEA = gm x sR1C1 + 1 VFB x VO s x (sR1C1C2 + C1 + C2) (30) This transfer function provides one pole at the origin, one zero at 1/(2πR1C1), and another pole at approximately 1/(2πR1C2) if C2 is used. If C2 is not used, a default value of 10 pF is substituted, representing the parasitic capacitance from the COMP/SD pin to ground. The value for R1 can be calculated using the following equation: R1 = 24 B gm (31) Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 The value, B, can be determined by evaluating the power stage transfer function at the desired cross-over frequency, or by reading the value graphically from the power stage gain plot. Setting B equal to the inverse of the linear gain will force the total loop gain to be 1 (0dB) at the cross-over frequency. For this example the desired cross-over frequency is 1/10 of the switching frequency, or 50 kHz. At 50 kHz the value of GPS is approximately -4dB, or 0.63V/V. This indicates a system where the fZ ≥ fSW. The value B should then be set to 1.58V/V and increased by 0.1V/V steps until the phase margin is at 45°. For this example, phase is 45° when B is 2.8V/V. Once R1 has been selected, C1 is calculated based on the value of R1 as shown in the following equation: 1 C1 = 2S x R1 x fP (32) R1 = 3.73 kΩ, and C1 = 15.7 nF. The closest 1% value should be used for R1 and the closest 10% value used for C1, which gives: R1 = 3.74 kΩ 1% C1 = 15 nF 10% The error amplifier of the LM3495 has a unity-gain bandwidth of 10 MHz. In order to model the effect of this limitation, the open-loop gain, OPG, can be calculated as: OPG = 2S x 10 MHz 2S x 10 MHz s+ gm x 72 M: (33) The new error amplifier transfer function taking into account unity-gain bandwidth is: GEA-ACTUAL = GEA x OPG 1 + GEA+ OPG (34) 50 0 40 -30 ERROR AMP PHASE (°) ERROR AMP GAIN (dB) The gain and phase of the error amplifier are shown in Figure 38. 30 20 10 -90 -120 -150 0 -10 100 -60 1k 10k 100k 1M -180 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 38. Error Amplifier Gain and Phase The total control loop transfer function, H, is equal to the power stage transfer function multiplied by the error amplifier transfer function. The bandwidth and phase margin can be read graphically from Bode plots of H, shown in Figure 39. H = GPS x GEA-ACTUAL (35) Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 25 LM3495 www.ti.com 60 -60 40 -80 OVERALL LOOP PHASE (°) OVERALL LOOP GAIN (dB) SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 20 0 -20 -40 -60 100 1k 10k 100k 1M -100 -120 -140 -160 -180 100 FREQUENCY (Hz) 1k 10k 100k 1M FREQUENCY (Hz) Figure 39. Overall Loop Gain and Phase The bandwidth of this example circuit is 49 kHz, with a phase margin of 46°. Efficiency Calculations A reasonable estimation for the efficiency, η, of a buck regulator controlled by the LM3495 can be obtained by adding together the loss in each current carrying element, PTOTAL-LOSS, and using the equation: PO K= PO + PTOTAL-LOSS (36) The following shows an efficiency calculation to complement the Typical Application Circuit. Output power for this circuit is PO = 1.2V x 10A = 12W. Input voltage is assumed to be 12V, and the calculations used assume that the converter runs in CCM. Chip Operating Loss This term accounts for the current drawn at the VIN pin. This current, IIN, drives the logic circuitry and the power FETs. The gate driving loss term from the power FET section of Design Considerations is included in the chip operating loss. For the LM3495, IIN is equal to the steady state operating current, IQ, plus the FET driving current, IGC. Power is lost as this IIN passes through the internal linear regulator of the LM3495. IGC = (QG-HI + QG-LO) x fOSC IGC = (11nC + 33nC) x 500 kHz = 22 mA (37) (38) IQ is typically 1.8 mA, taken from the Electrical Characteristics table. Chip Operating Loss is then: PQ = VIN x (IQ + IGC) PQ = 12V x (1.8mA + 22mA) = 0.29W (39) (40) High-Side FET Switching Loss PSW = 0.5 x VIN x IO x (tR + tF) x fSW PSW = 0.5 x 12V x 10A x (5 ns + 8 ns) x 500 kHz = 0.39W (41) (42) FET Conduction Loss PC = D (I2O x RDSON-HI x 1.3) PC-HI = 0.1 x (100 x 0.013) = 0.13W PC = (1 - D) (I2O x RDSON-LO x 1.3) PC-LO = 0.9 x (100 x 0.0044) = 0.40W (43) (44) (45) (46) RSNS Loss (if used) PSNS = (1 - D) ((IO)2 x RSNS) (47) Not used in this example. 26 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 Input Capacitor Loss This term represents the loss as input ripple current passes through the ESR of the input capacitor bank. In this equation ‘n’ is the number of capacitors in parallel. PIN = I2rms-IN x ESR n Irms-IN = IO x D(1 - D) Irms-IN = 10 x 0.1(0.9) = 3A (48) (49) PIN = (3A)2 x 2mΩ) = 0.018W Output Inductor Loss PLOUT =(IO)2 x RL PLOUT = (10A)2 x 3 mΩ = 0.3W (50) (51) Total Loss PLOSS = 1.53W (52) Efficiency n = 12W/(12W +1.50W) = 88% (53) Layout Considerations To produce an optimal power solution with the LM3495, good layout and design of the PCB are as important as the component selection. The following are several guidelines to aid in creating a good layout. KELVIN TRACES FOR SENSE LINES The pins of the low-side FET should be connected as close as possible to the SW/CSH and CSL pins. Each pin should use a separate trace, and the traces should be run parallel to each other to give common mode rejection. Although it can be difficult in a compact design, these traces should stay away from the output inductor if possible, to avoid coupling stray flux. The SNS pin should also be connected using a separate Kelvin trace, running from the positive pin/pad of the output cap to the pin itself. This trace should also be used to connect to the top of the feedback resistors. Keep this trace away from the switch node and from the output inductor. SEPARATE PGND AND SGND Good layout techniques include a dedicated ground plane, usually on an internal layer. Signal level components like the compensation and feedback resistors should be connected to a section of this internal plane, SGND. The SGND section of the plane should be connected to the power ground at only one point. The best place to connect the SGND and PGND is right at the SGND pin. MINIMIZE THE SWITCH NODE The plane that connects the power FETs and output inductor together radiates more EMI as it gets larger. Use just enough copper to give low impedance to the switching currents. LOW IMPEDANCE POWER PATH The power path includes the input capacitors, power FETs, output inductor, and output capacitors. Keep these components on the same side of the PCB and connect them with thick traces or copper planes (shapes) on the same layer. Vias add resistance and inductance to the power path, and have high impedance connections to internal planes than to the top of bottom layers of a PCB. If heavy switching currents must be routed through vias and/or internal planes, use multiple vias in parallel to reduce their resistance and inductance. The power components should be kept close together. The longer the paths that connect them, the more they act as antennas, radiating unwanted EMI. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 27 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Table 1. Bill of Materials for 6.0V to 18.0V Input, 1.0V Output, 7A, 500 kHz ID Part Number Type Size U1 LM3495 Synchronous Controller TSSOP-16 Q1 Si4894DY N-MOSFET SO-8 Q2 Si4442DY N-MOSFET SO-8 D1 MBR0530 Schottky Diode Parameters Qty Vendor 1 TI 30V, 15mΩ, 11.5nC 1 Vishay 30V, 4.1mΩ, 36nC 1 Vishay SMA 30V, 0.5A 1 Vishay 12.5x12.8 x 4.7mm 2.7µH 8.7A 4.5mΩ 1 TDK L1 RLF12545T-2R7N8R7 Inductor CIN1,CIN2 C3225X5R1E106M Capacitor 1210 22µF, 25V 2 TDK CO1 6TPD470M Capacitor 7.3x4.3 x3.8 470µF 6.3V 10mΩ 1 Sanyo TDK CF C2012X7R1E105M Capacitor 0805 1µF, 25V 1 CDD C2012X7R1C225M Capacitor 0805 2.2µF 16V 1 TDK CB, CINX VJ0805Y104KXXAT Capacitor 0805 100nF 10% 2 Vishay CC1 VJ0805Y822KXXAT Capacitor 0805 8.2nF 10% 1 Vishay CC2 VJ0805A1012KXXAT Capacitor 0805 100pF 10% 1 Vishay RC1 CRCW08055761F Resistor 0805 5.76kΩ 1% 1 Vishay RFB1 CRCW080510502F Resistor 0805 15kΩ 1% 1 Vishay RFB2 CRCW08051002F Resistor 0805 10kΩ 1% 1 Vishay RFRQ CRCW08055492F Resistor 0805 54.9kΩ 1% 1 Vishay RLIM CRCW08052671F Resistor 0805 2.67kΩ 1% 1 Vishay Qty Vendor Table 2. Bill of Materials for 3.0V to 6.0V Input, 2.2V Output, 7A, 500 kHz ID Part Number Type Size U1 LM3495 Synchronous Controller TSSOP-16 Q1 Si4866DY N-MOSFET SO-8 Q2 Si4838DY N-MOSFET SO-8 D1 MBR0530 Schottky Diode L1 MSS1260–102NX Inductor CIN1, CIN2 C3225X5R1A226M Capacitor CO1 6TPD470M CF C2012X7R1E105M Parameters 1 TI 12V, 6.5mΩ, 21nC 1 Vishay 12V, 3.1mΩ, 40nC 1 Vishay SMA 30V, 0.5A 1 Vishay 12.3x12.3 x 6mm 1µH 8A 10mΩ 1 Coilcraft 1210 22µF, 10V 2 TDK Capacitor 7.3x4.3 x3.8 470µF 6.3V 10mΩ 2 Sanyo Capacitor 0805 1µF, 25V 1 TDK CDD C2012X7R1C225M Capacitor 0805 2.2µF 16V 1 TDK CB, CINX VJ0805Y104KXXAT Capacitor 0805 100nF 10% 2 Vishay CC1 VJ0805Y472KXXAT Capacitor 0805 4.7nF 10% 1 Vishay RC1 CRCW08051742F Resistor 0805 17.4kΩ 1% 1 Vishay RFB1 CRCW08053741F Resistor 0805 3.74kΩ 1% 1 Vishay RFB2 CRCW08051002F Resistor 0805 10kΩ 1% 2 Vishay RFRQ CRCW08055492F Resistor 0805 54.9kΩ 1% 1 Vishay RLIM CRCW08052051F Resistor 0805 2.05kΩ 1% 1 Vishay 28 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 Table 3. Bill of Materials for Typical Application Circuit ID Part Number Type Size U1 LM3495 Synchronous Controller TSSOP-16 Q1 HAT2198R N-MOSFET SO-8 Q2 HAT2165H N-MOSFET LFPAK D1 MBR0530 Schottky Diode L1 RLF12560T-1R0N140 Parameters Qty Vendor 1 TI 30V, 9.6mΩ, 11nC 1 Renesas 30V, 3.4mΩ, 33nC 1 Renesas SMA 30V, 0.5A 1 Vishay Inductor 12.5x12.8 x 6mm 1µH 14A 3mΩ 1 TDK CIN C3225X5R1E226M Capacitor 1210 22µF, 25V 1 TDK CO1, CO2 C3225X5R0J107M Capacitor 1210 100µF 6.3V 1.5mΩ 2 TDK CF C2012X7R1E105M Capacitor 0805 1µF, 25V 1 TDK CDD C2012X7R1C225M Capacitor 0805 2.2µF 16V 1 TDK CB, CINX VJ0805Y104KXXAT Capacitor 0805 100nF 10% 2 Vishay CC1 VJ0805Y103KXXAT Capacitor 0805 10nF 10% 1 Vishay RC1 CRCW08051501F Resistor 0805 1.5kΩ 1% 1 Vishay RFB1, RFB2 CRCW08051002F Resistor 0805 10kΩ 1% 2 Vishay RFRQ CRCW08055492F Resistor 0805 54.9kΩ 1% 1 Vishay RLIM CRCW08053321F Resistor 0805 3.32kΩ 1% 1 Vishay Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 29 LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision E (April 2013) to Revision F • 30 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 29 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM3495 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM3495MTC/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3495 MTC LM3495MTCX NRND TSSOP PW 16 2500 TBD Call TI Call TI -40 to 125 LM3495 MTC LM3495MTCX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM3495 MTC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM3495MTCX TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 LM3495MTCX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3495MTCX TSSOP PW 16 2500 367.0 367.0 35.0 LM3495MTCX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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