HT45R15B 1.1 Features Operating voltage : fSYS =4M Hz:2.2V~5.5V fSYS =8M Hz:3.3V~5.5V 22 bidirectional I/O lines (max.) One external interrupt input pin shared with an I/O line Build-in de-bounce circuit for external interrupt De-bounce time is selected by software options Three 8-bit programmable timer/event counters Timer 0 can be configured to count synchronism pulse number or measure synchronism pulse high or low period Timer 1 can be configured to implement PPG non-retrigger function Watchdog Timer /Oscillator stop detection 4096 x 15 program memory ROM 208 x 8 data memory RAM HALT function and wake-up feature reduce power consumption Up to 0.5μs instruction cycle with 8MHz system clock at VDD =5V 8-level subroutine nesting 12 channels 12-bit resolution A/D converter 9-bit programmable pulse generator Support pulse width limit Two PPG preload registers Support non-retrigger control Support active high or low output (by configuration option) 4 comparators, 1 OPA (input voltage offset adjustable by software) Support peripheral clock output, PWM output I C Bus (Slave Mode) Bit manipulation instruction 63 powerful instructions All instructions in one or two machine cycles Low voltage reset /low voltage detector function Partial lock 2 24 -pin SKDIP/ 20-pin DIP/ 16-pin DIP, NSOP package Page 1 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 1.2 General Description The device are 8-bit high performance, RISC architecture microcontroller devices specifically designed for the A/D applications that interface directly to analog signals, such as those from sensors. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, multi-channel A/D converter, HALT and wake-up functions enhance the versatility of these devices to suit for a wide range of A/D application possibilities such as sensor signal processing. The device also provides three comparators, an operational amplifier and a programmable pulse generator (PPG); hence it is particularly for use in products such as induction cooker and home appliances. Page 2 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 1.3 Block Diagram TMR2C TMR2 fT2 Prescaler TMR0 M U X M U X TMR0C TMR0 fSYS INT0 (synchronism pulse number measure) fT0 Interrupt Circuit TMR1C TMR1 fT1 Stack Program ROM INTC Program Counter Instruction Register fSYS/4 M U X WDT WDT OSC fSYS Data Memory PPGC PPGTA PPGTB PPGTEX INT00 trigger mode &delay INT0 M U X debounce M U X MP M U X INT C0VO CP0N C0VO CP0P MUX Instruction Decoder ALU Timing Generator AN9 STATUS C1VO CP1N C2VO VR1 0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775*VDD CP2P VR2 0.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775*VDD CP2N VR3 0.075,0.1,0.125,0.15,0.175,0.2,0.225,0.25*VDD PPG Shifter CP3N C3VO ACC OSC2 OSC1 RES VDD VSS Internal RC OSC HALT VR40.6,0.625,0.65,0.675,0.7,0.725,0.75,0.775*VDD EN/DIS IOFF PPG LVR/LVD PC Port C PCC Ocillator stop detection PWM PB Port B PBC PA1/OPAO /OSC1/AN8 PA0/OPAN /OSC2 PB3/AN2 12-Channel A/D Converter PA Port A PAC VSS I2 C Bus Slave Mode PC0/AN10 PC1/PCK PC2~6 PC7/AN11 PB0/SCL/RES PB1/SDA/AN0 PB2/AN1/IOFF PB3/AN2 PB4/AN3/PWM PB5/AN4 PA0/OPAN/OSC2 PA1/OPAO/OSC1/AN8 PA2/CP0N/INT PA3/CP0P/TMR0 PA4/PPG PA5/CP1N/AN7 PA6/CP2N/AN6 PA7/CP2P/AN5 Note: External interrupt trigger source is INT0 falling edge (inverted or non-inverted de-bounce signal from INTB or comparator 0 output “C0VO” by software option) Page 3 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 1.4 Pin Assignment Page 4 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 1.5 Pin Description Pad Name I/O Configuration Options Wake-up Pull-high OSCCFG OPAEN PA0/OPAN/OSC2 PA1/OPAO/OSC1/AN8 I/O Software Options PA1 or AN8 OSC1+OSC2 or OSC1+PA0 or OSC1+OPAN or PA1/AN8+PA0 or PA1/AN8+OPAN or OPAO(AN8)+OPAN Wake-up Pull-high CMP0EN, CMP1EN, PPGEN, PLEV, PTSYN PA2/CP0N/INTB PA3/CP0P/TMR0 PA4/PPG I/O C1CTL PA2/INTB+PA3/TMR0 or CP0N+CP0P or CP0N+CP0P/CP1N or PA2/INTB +CP1N PA4 or PPG Wake-up Pull-high PA5 or AN7 C1CTL CMP1EN PA5/CP1N/AN7 I/O PA5/AN7 or CP1N(AN7) Wake-up Pull-high CMP2CFG PA6/CP2N/AN6 PA7/CP2P/AN5 I/O PB0/SCL/ RESB I/O PAx or ANx PA6/AN6+PA7/AN5 or PA6/AN6+CP2P(AN5) or CP2N(AN6)+ PA7/AN5 or CP2N(AN6)+CP2P(AN5) Pull-high (PB1) Description Bidirectional 2-bit input/output port. PA0, PA1 is pin-shared with OPAN/OSC2, OPAO/OSC1/AN8 respectively. When configured as bidirectional input/output port. It can be configured as wake-up input by configuration options. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high configuration option: bit option). Configuration options determine the I/O, OSC1, OSC2 or operational amplifier functions to be used. Once selected as operational amplifier input/output, oscillator input/output or A/D input, the I/O function and pull-high resistor are disabled automatically. Bidirectional 3-bit input/output port. PA2, PA3, PA4 is pin-shared with CP0N/INTB, CP0P/TMR0, PPG respectively. When configured as bidirectional input/output port. It can be configured as wake-up input by configuration options. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high configuration option: bit option). Once comparator 0 function is configured, the I/O function and pull-high resistor are disabled automatically. Note if comparator 1 is enabled and C1CTL software option selected PA3 as CP1N, the PA3 I/O function and pull-high resistor are disabled automatically. Once the PPG function is used, the internal registers related to PA4 can not be used. PPG pin is floating during PPG inactive period, power-on reset, RESB pin reset, LVR reset and oscillator stop condition (if enabled). The PPG output level (active low or active high) can be selected via configuration option. Bidirectional 1-bit input/output port. PA5 is pin-shared with CP1N/AN7. When configured as bidirectional input/output port. It can be configured as wake-up input by configuration options. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high configuration option: bit option). Once selected as an A/D input or comparator 1 input the I/O function and pull-high resistor are disabled automatically. Bidirectional 2-bit input/output port. PA6, PA7 is pin-shared with CP2N/AN6, CP2P/AN5 respectively. When configured as bidirectional input/output port. Each bit can be configured as wake-up input by configuration options. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high configuration option: bit option). Once selected as an A/D input or comparator 2 input, the I/O function and pull-high resistor are disabled automatically. Bidirectional 2-bit input/output port. PB0, PB1 is Page 5 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B PB1/SDA/AN0 RESBEN I2CEN PB1 or AN0 PB0+PB1/AN0 or RESB+PB1/AN0 or SCL+SDA Pull-high PB2CFG PB2/IOFF/AN1 PB2 or AN1 I/O PB2/AN1 or IOFF Pull-high OPAEN PB4CFG PB3/AN2 PB4/PWM/AN3 PB5/AN4 PBx or ANx I/O PB4/AN3 or PWM PC0/ AN10/CP3N PC1/PCK/CP3N PC2~6 PC7/AN11 VDD VSS I/O Pull-high PC1 or PCK PCx or ANx --- pin-shared with SCL/RESB, SDA/AN0 respectively. When PB0 is configured as bidirectional input/output. Software instructions determine the NMOS output, Schmitt trigger input without pull-high resistor. When PB1 is configured as bidirectional input/output. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high configuration option: bit option.) Once PB1 line is selected as an A/D input, the I/O function and pull-high resistor are disabled automatically. Once PB0 line is selected as a reset input, the I/O function is disabled automatically. Once I2C Bus function is used, the internal registers related to PB0 and PB1 can not be used. Bidirectional 1-bit input/output port. PB2 is pin-shared with AN1/IOFF. When configured as bidirectional input/output. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high configuration option: bit option). Once selected as an A/D input, or IOFF output, the I/O function and pull-high resistor are disabled automatically. Bidirectional 3-bit input/output port. PB3, PB4, PB5 are pin-shared with AN2, AN3/PWM, AN4 respectively. When configured as bidirectional input/output. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high configuration option: bit option). Once selected as an A/D input or PB4 as a PWM output or OPA enable with output connected to PB3/AN3 through a resistor, the I/O function and pull-high resistor are disabled automatically. Bidirectional 8-bit input/output port. PC0, PC1, PC7 are pin-shared with AN10/CP3N, PCK/CP3N, AN11 respectively. When configured as bidirectional input/output. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high configuration option: bit option). Once PC1 selected as PCK or CP3N output, PC0/7 selected as A/D input or CP3N, the I/O function and pull-high resistor are disabled automatically. Positive power supply Negative power supply, ground Page 6 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 2.0Absolute Maximum Ratings Supply Voltage ................VSS -0.3V to VSS +6.0V Storage Temperature ......................-50℃ to 125℃ Input Voltage..................VSS -0.3V to VDD +0.3V Operating Temperature.......................0℃ to 80℃ IOL Total……………………………………300mA IOH Total………….………………………-200mA Total power dissipation…………………500mW Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. 3.0D.C. Characteristics Ta=25℃ Symbol Test Conditions Parameter VDD VDD Operating Voltage IDD1 Operating Current (Crystal OSC) IDD2 IDD3 ISTB1 ISTB2 VIL1 VIH1 Standby Current (WDT disable) Unit fSYS=4MHz 2.2 - 5.5 V fSYS=8MHz 3.3 - 5.5 V 3V No load, fSYS=4MHz - 0.6 1.5 mA 5V ADC disable - 2.0 4.0 mA 3V No load, fSYS=4MHz - 0.8 1.5 mA 5V ADC disable - 2.5 4.0 mA - 4 8 mA - - 5 μA 5V - - 10 μA 3V - 1 μA - 2 μA 0 0.3VDD V 3V Standby Current (WDT enable) Max. - 5V (Crystal OSC, RC OSC) Typ. - Operating Current (RC OSC) Operating Current Min. Conditions No load, fSYS=8MHz ADC disable No load, system HALT No load, system HALT 5V Input Low Voltage for I/O Ports, TMR0 and INTB Input High Voltage for I/O Ports, TMR0 and INTB - 0.7VDD - VDD V VIL2 Input Low Voltage (RESB) - 0 - 0.4VDD V VIH2 Input High Voltage (RESB) - 0.9VDD - VDD V VLVR1 Low Voltage Reset (Note2) LVR 2.1V option 1.98 2.1 2.22 V VLVR2 Low Voltage Reset (Note2) LVR 3.0V option 2.83 3.0 3.17 V VLVD Low Voltage Detector Voltage (Note2) 4.12 4.4 4.7 V IOL1 I/O Port Sink Current (except PB0) 4 8 - mA 3V VOL=0.1VDD Page 7 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B IOL3 PB0 Sink Current IOH1 I/O Port (except PB0) Source Current RPH Pull-high Resistance VAD AD Input Voltage DNL ADC Differential Non-Linearity INL ADC Integral Non-Linearity IADC 5V VOL=0.1VDD 10 20 5V VOL=0.1VDD TBD 3 3V VOL=0.9VDD -2 -4 - mA 5V VOL=0.9VDD -5 -10 - mA 3V - 20 60 100 kΩ 5V - 10 30 50 kΩ - 0 - VDD V tAD=0.5us -2 +2 LSB tAD=0.5us -4 +4 LSB 2.7~ 5.5V 2.7~ 5.5V 2.7~ 5.5V - mA mA Additional Power Consumption if A/D 3V No load - 0.5 1 mA Converter is Used, tAD=0.5us 5V No load - 0.6 1.2 mA Page 8 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 4.0A.C Characteristics Ta=25℃ Symbol Parameter System Clock (Crystal OSC, RC OSC) fSYS1 fSYS2 Condition Typ. Max. Unit - 2.2V~5.5V 400 - 4000 KHz - 3.3V~5.5V 400 - 8000 KHz 7760 8000 8240 KHz +2 % 5V 8MHz, Ta=25℃ Temperature drift percentage relative to 25 ℃ 5V 0~55℃ -2 - 2.2V~5.5V 0 - 4000 KHz - 3.3V~5.5V 0 - 8000 KHz 45 90 180 32 65 130 1 - - us 3V tWDTOSC Min. System Clock (Internal RC OSC by calibration) Timer I/P Frequency (TMR0/TMR1/TMR2) fTIMER VDD Watchdog Oscillator Period - us 5V tRES External Reset Low Pulse Width - tSST System Start-up Timer Period - Power up or wake-up from HALT - 1024 - *tSYS tINT** Interrupt Pulse Width - No de-bounced 1 - - us tAD A/D Clock Period - - 0.5 - - us tADC A/D Conversion Time - - - 16 - tAD tLVR Low Voltage Width to Reset - - 0.25 1 2 ms tOSTP Oscillator Stop to Reset Time - - tIIC I C Bus Clock Period 2 - - 10 Connect to external pull high resister 2KΩ 64 us - - * tSYS Note: * tSYS= 1/fSYS1, 1/fSYS2 **Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized. 5.0Comparator/Operational Amplifier Characteristics Ta=25℃ Comparator Symbol Parameter Operating Voltage VDD Condition Min. - - 3.0 Typ. Max. Unit - 5.5 V Typ.+5% V Typ.+5% V 0.6~0.775VDD, VR1 Reference Voltage for Comparator 1 5V -40~85 ℃ (±5%) Typ.-5% VR2 Reference Voltage for Comparator 1 5V -40~85 ℃ (±5%) Typ.-5% 0.025VDD/step 0.6~0.775VDD, 0.025VDD/step Page 9 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 0.075 VDD VR3 Reference Voltage for Comparator 2 5V -40~85 ℃ (±5%) Typ.-5% ~0.25VDD, Typ.+5% V 0.025VDD/step By calibration VOS Analog Comparator Input Offset Voltage -2 - +2 mV -15 - +15 mV VDD-1.4 V Without calibration 5V CnCOF[4:0]=10000 B VCM Analog Comparator Common Mode tPD Analog Comparator Response Time - VHYS - - Voltage Range Analog Comparator Hysteresis Width 5V Analog Comparator Hysteresis Disable and With 10mV overdrive Analog Comparator Hysteresis Enable and With 60mV overdrive Analog Comparator Hysteresis Enable 0 - - 2 μS - - TBC* μS 20 40 60 mV Max. Unit 5.5 V 0.1 uA -15 +15 mV -2 +2 mV VSS VDD-1.4V V *TBC: To be confirmed Operational Amplifier Symbol Parameter VDD Condition Operating Voltage Min. Typ. 3 5V Power Down Current Without calibration, VOPOS1 Input Offset Voltage 5V VOPOS2 Input Offset Voltage 5V VCM Common Mode Voltage Range PSRR Power Supply Rejection Ratio 5V 60 80 dB CMRR Common Mode Rejection Ratio 5V VCM =0~ VDD -1.4V 60 80 dB SR Slew Rate+, Slew Rate- 5V No load 0.6 GBW Gain Band Width 5V RL=1M, CL=100P 0.6 Typical value 5V 25 ℃ 45 5V 0~50 ℃ -3 5V 25 ℃ 5V 0~50 ℃ 5V 25 ℃ OPAR1 Temperature drift percentage relative to 25 ℃ Typical value OPAOF[4:0]=10000B By calibration 0.75 1.8 V/us (TBC*) 2.2 MHz (TBC*) 60 1 75 kΩ +3 % 1.25 kΩ +3 % OPAR2 OPAR3 OPAR4 Temperature drift percentage relative to 25 ℃ Typical value -3 10 *TBC: To be confirmed Page 10 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. kΩ HT45R15B 6.0Power on Reset Characteristics Ta=25℃ Symbol RPOR Parameter VDD Rise Rate to Ensure Power-on Reset VDD Condition Without 0.1uF between VDD and VSS Ta=25℃ VPOR_MAX Maximum VDD Start Voltage to Ensure Power-on Reset Without 0.1uF Power-on Reset Low Pulse Width Typ. Max. 0.05 Ta= -40~85℃ VSS VSS With 0.1uF between VDD and VSS V/ms 0.9 1.5 V 0.6(#) 1.8(#) V 2 us TBD(#) us *TBD: To be defined Page 11 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. Unit between VDD and Without 0.1uF between VDD and tPOR Min. HT45R15B 7.0Application Circuit PPG active high option PPG active low option 15V High Voltage 15V Coil Panel Coil Panel IGBT IGBT VDD 0.01F* High Voltage VDD 100k 0.1F RES/PB0/SCL PA4/PPG PA4/PPG 10k 0.1F* VSS IRC VDD Voltage detect PA5/CP1N/AN7 PB2/AN1/IOFF PB5/AN4 Temperature 1 detect Temperature 2 detect Buzzer PB4/PWM/AN3 PB3/AN2 VDD PA1/OPAO/OSC1/AN8 PA0/OPAN/OSC2 _ + Current detect Motor OPANCFG=0 OPAPCFG=1 OPAOCFG=0 OPAFBCFG=0 + PC0/AN10 PC1/PCK PA2/CP0N/INT Synchronism detect PA7/CP2P/AN5 + C1CTL=0 VR1 PC3 + PA5/CP1N/AN7 Recoil voltage detect PC2 _ + PPG Module PA3/CP0P/TMR0 _ Display HT74164 PC4 & Key PC5 PC6 PC7/AN11 PB1/SDA/AN0 VR2 ++ AC Surge detect CMP2CFG[1:0]=11b _ PA6/CP2N/AN6 VR3 PC0/AN10/CP3N _ + PC1/PCK/CP3N VR4 + Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RESB to high. “*” Make the length of the wiring, which is connected to the RESB pin as short as possible, to avoid noise interference. Page 12 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.0Functional Description 8.1 Execution Flow The system clock is derived from a crystal, an external RC oscillator or an internal RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme allows each instruction to be effectively executed in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 System Clock PC PC PC+1 PC+2 Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) Execution Flow 8.2 Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by 1. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, subroutine call, initial reset, internal interrupt, external interrupt, or returning from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction. The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Page 13 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B Program Counter Mode *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 Initial Reset Comparator 2 interrupt or Timer/Event Counter 1 overflow (by configuration option) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Comparator 1 interrupt 0 0 0 0 0 0 0 1 0 0 0 Multi-function interrupt 0 0 0 0 0 0 0 1 1 0 0 I C-Bus Interrupt 0 0 0 0 0 0 1 0 0 0 0 Timer/Event Counter 0 overflow 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 2 Timer/Event Counter 2 overflow or A/D converter Interrupt (by configuration option) Skip Program Counter+2 Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return From Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program counter Note: *10~*0: Program counter bits S10~S0: Stack register bits #10~#0: Instruction code bits @7~@0: PCL bits Page 14 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.3 Program Memory The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 4096*15 bits, addressed by the PC and table pointer. 000H 004H 008H 00CH 010H Device Initialization Subroutine Multi-function interrupt Comparator 1 Interrupt Subroutine External Interrupt or LVD interrupt I2C Bus Interrupt Subroutine 014H Timer/Event Counter 0 Interrupt Subroutine 018H n00H nFFH Timer/Event Counter 2 Interrupt Subroutine or A/D Converter Interrupt Subroutine Program Memory Look-up Table (256 words) F00H FFFH Look-up Table (256 words) 15 bits Note: n ranges from 0 to F Certain locations in the ROM are reserved for special usage: ‧ Location 000H Location 000H is reserved for program initialization. After chip reset, the program always begins execution at this location. ‧ Location 004H Location 004H is reserved and the stack is not full, the program begins execution at location 004H. ‧ Location 008H Location 008H is reserved for the comparator 1 interrupt service program. If the comparator 1 output is activated (falling edge), and if the interrupt is enable and the stack is not full, the program begins execution at location 008H. ‧ Location 00CH Location 00CH is reserved for External Interrupt or LVD interrupt interrupt service program determined by configuration option. If the External Interrupt is activated or a LVD event occurs, and if the interrupt is enable and the stack is not full, the program Page 15 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B begins execution at location 00CH. ‧ Location 010H 2 2 Location 010H is reserved for the I C Bus interrupt service program. If the I C Bus interrupt results from a slave address is match or completed one 8-bit data transfer, and the interrupt is enable and the stack is not full, the program begins execution at location 010H ‧ Location 014H Location 014H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 014H. ‧ Location 018H Location 018H is reserved for either the A/D converter or Timer /Event Counter 2 interrupt service program determined by configuration option. If an A/D converter interrupt results from an end of A/D conversion or a timer interrupt results from a Timer/Event Counter 2 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 018H. ‧ Table location Any location in the ROM can be used as a look-up table. The instructions “TABRDC [m]” (the current page, 1 page=256 words) and “TABRDL [m]” (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH, and the remaining 1 bit read as “0”. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal program memory depending upon the user's requirements. Table location Instruction(s) *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Page 16 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B Table Location Note: *10~*0: Table location bits P10-P8: Current Program Counter bits @7~@0: Table pointer (TBLP) bits 8.4 Stack Register * STACK The stack register is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At a subroutine call or an interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of the subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack. If the stack is full and an interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. In a similar case, if the stack is full, and a “CALL” is subsequently executed, a stack overflow occurs and the first entry will be lost (only the most recent 8 return addresses are stored). 8.5 Data Memory - RAM The data memory (RAM) is divided into two functional groups, namely, special function registers and general purpose data memory (208*8 bits) most of which are readable/writeable, although some are read only. The remaining space before the 3FH is reserved for future expanded usage and reading these locations will get “00H”. The general purpose data memory, addressed from 40H to FFH is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by “SET [m].i” and “CLR [m].i”. They are also indirectly accessible through memory pointer registers (MP0:01H/MP1:03H). The data memory (RAM) is divided into two banks, bank0 and bank1. Selecting data memory (RAM) between bank0 and bank1 is achieved by bit 0 of BP register. BP Register Bit Name R/W POR 7 - Bank7~Bank1 Bit0 6 - 5 - 4 - 3 - 2 - 1 - 0 DMBP Undefined DMBP 0:Bank0 1:Bank1 Page 17 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B Bank1 Bank0 00H Indirect Addressing Register 0 01H MP0 02H Indirect Addressing Register 1 03H MP1 04H BP 05H ACC 06H PCL 07H TBLP 08H TBLH 09H 0AH STATUS 0BH INTC0 0CH 0DH TMR0 0EH TMR0C 0FH 10H TMR1 11H TMR1C 12H PA 13H PAC 14H PB 15H PBC 16H PC 17H PCC 18H Special Purpose Data Memory 19H 1AH CTRL0 1BH CMP0C 1CH CMP1C 1DH CMP2C 1EH INTC1 1FH 20H PPGC 21H PPGTA 22H PPGTB 23H PPGTEX 24H ADRL 25H ADRH 26H ADCR 27H ACSR 28H CTRL1 29H OPAC 2AH CTRL2 2BH PWLT 2CH CTRL3 2DH TMR2 2EH TMR2C 2FH CMPSC 30H HADR 31H HCR 32H HSR 33H HDR PCRL PCRH PWM PWMC CMP3C CTRL4 34H 35H 36H 37H 38H 39H 3AH MFI 3BH 3FH 40H 4FH General Purpose Gen eral Purpose D ara M e mo ry Data Memory (16 By tes) (192 Bytes) : Unused Read as "00" FFH Page 18 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.6 Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. 8.7 Accumulator - ACC The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. 8.8 Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions: ‧Arithmetic operations (ADD, ADC, SUB, SBC, DAA) ‧Logic operations (AND, OR, XOR, CPL) ‧Rotation (RL, RR, RLC, RRC) ‧Increment and Decrement (INC, DEC) ‧Branch decision (SZ, SNZ, SIZ, SDZ) The ALU not only saves the results of a data operation but also changes the status register. 8.9 Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the “CLR WDT” or “HALT” instruction. The PDF flag can be affected only by executing the “HALT” or “CLR WDT” instruction or a system power-up. The Z, OV, AC, and C flags reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the content of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. Bit No. Label Function Page 19 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B C is set if an operation results in a carry during an addition operation or if a borrow does not 0 C take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction 1 AC 2 Z 3 OV 4 PDF 5 TO 6,7 - AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vise versa; otherwise OV is cleared. PDF is cleared by system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. TO is cleared by system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. Undefined, read as “0”. Status Register Page 20 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.10 System Control Register The system control registers can control some configurations as following: System Control Register 0 (CTRL0) Bit No. 7 6 5 4 3 2 1 0 CTRL0 C2VOINV TMR0ECS PCKPSC2 PCKPSC1 PCKPSC0 OSTPC LVDO LVDC POR 0 0 0 0 0 0 0 0 Bit7: C2VOINV: Inverting control of the comparator 2 output signal. (0: non-inverted 1: inverted) Bit6: TMR0ECS: Select TMR0 external clock source (0: TMR0 pin, 1:INT0) Bit5~3: Peripheral clock prescaler stage PCKPSC2~0 000B 001B 010B 011B 100B 101 110 111 fPCK = fSYS /4/1= fSYS /4 = fSYS /4/2= fSYS /8 = fSYS /4/3= fSYS /12 = fSYS /4/4= fSYS /16 = fSYS /4/5= fSYS /20 = fSYS /4/6= fSYS /24 =fSYS/1024 =fSYS/2048 Bit2: Oscillator stop function control (1: enable, 0: disable) Bit1: Low voltage detector output 1: low voltage detected 0: normal voltage Bit0: Low voltage detector control (1: enable, 0: disable) System Control Register 1 (CTRL1) Bit No. CTRL1 POR 7 INTINV 0 6 INTS 0 5 DBC5 0 4 DBC4 0 3 DBC3 0 2 DBC2 0 1 DBC1 0 0 DBC0 0 Bit7: INTINV: Inverting control of the de-bounced external interrupt input signal. (0: non-inverted 1: inverted) Bit6: INTS: Select external interrupt source (0: INTB, 1: comparator 0 output “C0VO”) Bit5~0: DBC5~0: Select external interrupt input de-bounce time DBC5~DBC0 000000B 000001B 000010B : : 101111B 11xxxxB Digital de-bounce time for fSYS=8MHz bypass digital de-bounce circuit 0~1/fSYS , about 0.125us 1/fSYS~2/fSYS, about 0.25us : : 46/fSYS~47/fSYS, about 5.875us 47/fSYS~48/fSYS, about 6us System Control Register 2 (CTRL2) Bit No. CTRL2 POR 7 --0 6 --0 5 CVREF5 0 4 CVREF4 0 3 CVREF3 0 2 CVREF2 0 1 CVREF1 0 0 CVREF0 0 Bit7~6: Not implemented, read as “0” CTRL2 Bit5~3: CVREF5~3: Select internal reference voltage VR2 Page 21 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B CVREF5~3 000B 001B 010B 011B 100B 101B 110B 111B Internal reference voltage VR2 0.6VDD (0.6+0.025*1)VDD=0.625VDD (0.6+0.025*2)VDD=0.65VDD (0.6+0.025*3)VDD=0.675VDD (0.6+0.025*4)VDD=0.70VDD (0.6+0.025*5)VDD=0.725VDD (0.6+0.025*6)VDD=0.75VDD (0.6+0.025*7)VDD=0.775VDD CTRL2 Bit2~0: CVREF2~0: Select internal reference voltage VR1 CVREF2~0 000B 001B 010B 011B 100B 101B 110B 111B Internal reference voltage VR 1 0.6VDD (0.6+0.025*1)VDD=0.625VDD (0.6+0.025*2)VDD=0.65VDD (0.6+0.025*3)VDD=0.675VDD (0.6+0.025*4)VDD=0.70VDD (0.6+0.025*5)VDD=0.725VDD (0.6+0.025*6)VDD=0.75VDD (0.6+0.025*7)VDD=0.775VDD System Control Register 3 (CTRL3) Bit No. CTRL2 POR 7 --0 6 C3VOINV 0 5 CVREF11 0 4 CVREF10 0 3 CVREF9 0 2 CVREF8 0 1 CVREF7 0 0 CVREF6 0 Bit7: Not implemented, read as “0” Bit6: Inverting control of the comparator 3 output signal. (0: non-inverted 1: inverted) CTRL3 Bit5~3: CVREF11~9: Select internal reference voltage VR4 CVREF11~9 000B 001B 010B 011B 100B 101B 110B 111B Internal reference voltage VR 4 0.6VDD (0.6+0.025*1)VDD=0.625VDD (0.6+0.025*2)VDD=0.65VDD (0.6+0.025*3)VDD=0.675VDD (0.6+0.025*4)VDD=0.70VDD (0.6+0.025*5)VDD=0.725VDD (0.6+0.025*6)VDD=0.75VDD (0.6+0.025*7)VDD=0.775VDD CTRL3 Bit2~0: CVREF8~6: Select internal reference voltage VR3 CVREF8~6 000B 001B 010B 011B 100B 101B 110B 111B Internal reference voltage VR 3 0.075VDD (0.075+0.025*1)VDD=0.1VDD (0.075+0.025*2)VDD=0.125VDD (0.075+0.025*3)VDD=0.15VDD (0.075+0.025*4)VDD=0.175VDD (0.075+0.025*5)VDD=0.2VDD (0.075+0.025*6)VDD=0.225VDD (0.075+0.025*7)VDD=0.25VDD System Control Register 4 (CTRL4) Bit No. CTRL3 POR 7 - 6 - 5 PPGDL5 0 4 PPGDL4 0 3 PPGDL3 0 2 PPGDL2 0 1 PPGDL1 0 0 PPGDL0 0 Bit7~6: Not implemented, read as “0” Page 22 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B Bit5~0: PPGDL5~0: Select trigger delay for PPG PPGDL5~0 00000B 00001B 00010B : : 101111B 11xxxxB Trigger delay for PPG 0us 0.125us @ fSYS=8MHz 0.25us @ fSYS=8MHz : : 5.875us @ fSYS=8MHz 6us @ fSYS=8MHz Note: 1. Trigger delay means the time of the falling edge of INT0S to PPG trigger signal (INT00) being sent. 2. Falling edge of INT0S during trigger delay period will be ignored. INT0: inverted or non-inverted de-bounce signal from INTB or comparator 0 output “C0VO” by software option INT0S: signal represents single or double falling edge of INT0 INT00: PPG hardware trigger signal Page 23 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.11 Interrupts The device provides an external interrupt, three internal timer/event counter interrupts, three comparator interrupts, LVD 2 interrupt, an A/D converter interrupt and an I C bus interrupt. The interrupt control register 0 (INTC0; 0BH) and interrupt control register 1 (INTC1; 1EH) contain the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of INTC0 and INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full. All these interrupts have a wake-up capacity. As an interrupt is serviced, a control transfer occurs by pushing the contents of the program counter onto the stack followed by a branch to a subroutine at specified location in the program memory. Only the content of the PC is pushed onto the stack. If the content of the register or of the status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. The trigger source of interrupt vector 004H could be a multi-function interrupt which contain an Timer/Event Counter 1 interrupt , a comparator 2 output interrupt, and a comparator 3 output interrupt. The trigger source of interrupt vector 00CH could be an external interrupt or a LVD interrupt determined by configuration option. The trigger source of interrupt vector 018H could be either Timer/Event Counter 2 overflow or an end of A/D conversion determined by configuration option. The multi-function interrupt is triggered if the comparator 2 output interrupt, the comparator 3 output interrupt or the Timer/Event Counter 1 interrupt is triggered. When an event of Comparator 2 output interrupt, Comparator 3 output interrupt, or the Timer/Event Counter 1 interrupt occurs and its related enable status control bit is set, the program counter will be loaded with an address, 004H, to serve the related interrupt subroutine. Furthermore, the EMI bit and MTFF will be cleared automatically. However, ET1F, C2F, and C3F will not be cleared automatically and must be manually cleared by application program. The comparator 3 output interrupt is initialized by setting the comparator 3 output interrupt request flag (C3F) caused by a falling edge transition from the signal “C3VOB”. The comparator 1 output interrupt is initialized by setting the comparator 1 output interrupt request flag (C1F) caused by a falling edge transition from the comparator 1 output. When the interrupt is enabled, the stack is not full and the C1F bit is set, a subroutine call to location 008H will occur. The related interrupt request flag (C1F) will be reset, and the EMI bit cleared to disable further interrupts. Page 24 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B The external interrupt is triggered by falling edge transition of INT0 (inverted or non-inverted de-bounce signal from INTB or comparator 0 output “C0VO” by software option). The LVD interrupt is initialized by setting the LVD request flag (LVDF) caused by a low voltage detected. Trigger event of interrupt vector 00CH between LVD interrupt and external interrupt is determined by configuration option. when EMI bit and the related interrupt enable bit are enable, the stack is not full and the related interrupt flag is set, a subroutine call to 00CH will occur. The related interrupt request flag will be reset and the EMI bit is cleared to disable further interrupts. 2 2 The I C Bus interrupt is initialized by setting the I C Bus interrupt request flag (HIF) caused by a slave address match or one byte of data transfer is completed. When the interrupt is enabled, the stack is not full and the HIF bit is set, a subroutine call to location 010H will occur. The related interrupt request flag (HIF) will be reset and the EMI bit is cleared to disable further interrupts. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F) caused by a timer overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 014H will occur. The related interrupt request flag (T0F) will be reset, and the EMI bit cleared to disable further interrupts. The internal Timer/Event Counter 1/2 operate in the same manner, The Timer/Event Counter 1 interrupt related request flag is T1F and its subroutine call location is 004H. The Timer/Event Counter 2 interrupt related request flag is T2F and its subroutine call location is 018H. The A/D converter interrupt is initialized by setting the A/D converter request flag (ADF) caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF is set, a subroutine call to location 018H will occur. The related interrupt request flag (ADF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the “RETI” instruction is executed or the EMI bit and the related interrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine, “RET” or “RETI” may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests, the following table apply shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source Priority Vector Multi-function Interrupt 1 004H Comparator 1 Output Interrupt External Interrupt or LVD interrupt (by configuration option) 2 008H 3 00CH Page 25 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 2 I C-Bus Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 2 overflow or A/D converter Interrupt (by configuration option) 4 5 010H 014H 6 018H Interrupt Subroutine Vector Bit No. Label 0 EMI 1 MTFI Control the Multi-function interrupt (1:enable, 0: disable) 2 EC1I Control the comparator 1 interrupt (1:enable, 0: disable) 3 Function Control the master (global) interrupt (1=enable; 0=disable) EEI or ELVDI Control the external interrupt or the LVD interrupt (1= enable; 0= disable) 4 MTFF Multi-function interrupt request flag (1:active, 0: inactive) 5 C1F Comparator 1 interrupt request flag (1:active, 0: inactive) 6 7 EIF or LVDF External interrupt or LVD interrupt request flag(1=active; 0=inactive) - Unused bit, read as “0” INTC0 Register Bit No. Label Function 2 0 EHI Controls the I C Bus interrupt (1= enabled; 0= disabled) 1 ET0I Control the Timer/Event Counter 0 interrupt (1=enable; 0=disable) 2 3 ET2I or EADI Control the Timer/Event Counter 2 interrupt or the A/D converter interrupt (1=enable; 0=disable) HIF Unused bit, read as “0” 4 5 T0F Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) 6 2 I C Bus interrupt request flag (1= active; 0= inactive) T2F or ADF Internal Timer/Event Counter 2 request flag or A/D converter interrupt request flag (1=active; 0=inactive) 7 - Bit No. Label 0 EC3I Control Comparator 3 interrupt (1= enabled; 0= disabled) 1 EC2I Control Comparator 2 interrupt (1= enabled; 0= disabled) 2 ET1I Control the Timer/Event Counter 1 interrupt (1=enable; 0=disable) 3 C3F Unused bit, read as “0” 4 5 C2F Comparator 2 interrupt request flag (1= active; 0= inactive) 6 T1F Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) 7 - Unused bit, read as “0” INTC1 Register Function Comparator 3 interrupt request flag (1= active; 0= inactive) Unused bit, read as “0” MFI Register EMI, EEI/ELVDI, EC1I, MTFI, EHI, ET0I and ET2I/EADI and are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (C2F/T1F, C1F, MTFF, HIF T0F, EIF/LVDF and T2F/ADF) are set, they remain in the INTC0 or INTC1 respectively until the interrupts are serviced or cleared by a software instruction. In addition, “MFI” Register is a control register of Multi-function Interrupt which contain interrupt request flags and the enable status control bits of Timer/Event Counter 1 Interrupt, CMP2 Interrupt, and CMP3 interrupt. Page 26 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B It is recommended that a program does not use the “CALL subroutine” within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left, and enabling the interrupt is not well controlled, the original control sequence will be damaged once the “CALL” operates in the interrupt subroutine. Page 27 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.12 Oscillator Configuration The device provides three oscillator circuits for system clocks, i.e., external RC oscillator, crystal oscillator and internal RC oscillator, determined by configuration options. External crystal OSC: PA0/ PA1 are configured as OSC2/OSC1 to connect to a crystal External RC OSC + PA0: PA0 can configured as I/O when OPA is disabled or OPAN when OPA is enabled without OPAO pin-out, PA1 is configured as OSC1 to connect to a RC network Internal RC OSC: PA0 is configured as I/O and PA1 is configured as I/O or AN8 when OPA is disabled. PA0 is configured as OPAN and PA1 is configured as I/O or AN8 when OPA is enabled without OPAO pin-out. PA0 is configured as OPAN and PA1 is configured as OPAO, AN8 function can also be used when OPA is enabled with OPAO pin-out. No matter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator and ignores external signal in order to conserve power. If the external RC oscillator is configured, an external resistor between OSC1 and VDD is required, and the range of the resistance should be from 24k to 1M. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. If the crystal oscillator is configured, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required (if the oscillating frequency is less then 1MHz). If the internal RC oscillator is used, no external component is required. The frequency of this internal RC oscillator have a value 8 MHz. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 65μs at 5V. The WDT oscillator can be disabled by configuration option to conserve power. Page 28 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B VDD OSC1 OSC1 470pF PA0/OPAN OSC2 RC Oscillator PA1/OPAO /AN8 Internal RC Oscillator PA0/OPAN Crystal Oscillator Internal RC Oscillator System Oscillator Page 29 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.13 WDT The clock source of WDT is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4) determined by configuration option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by configuration option. If Watchdog Timer is disabled, all executions related to the WDT result in no operation. System Clock/4 8 fs/2 Mask option select fs Divider WDT Prescaler WDT OSC Time-out Reset fs/2 16 fs/2 15 fs/2 14 fs/2 13 Mask Option WDT Clear Watchdog Timer 13 14 15 Once an internal WDT oscillator is selected, it is divided by 2 , 2 , 2 16 or 2 (by configuration options) to get the WDT time-out period. This time-out period may vary with temperature, VDD and process variations. By selection the WDT configuration options, 16 longer time-out periods can be realized. If the WDT time-out is selected to fS/2 , the maximum time-out period is about 4.7s. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the halt state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The WDT overflow under normal operation will initialize a “chip reset” and sets the status bit “TO”. In the HALT mode, the overflow will initialize a “warm reset” wherein only the program counter and stack pointer are reset to “0”. To clear the WDT contents, three methods are adopted; external reset (a low level to RESB), software instruction, or a “HALT” instruction. The software instructions include “CLR WDT” and the other set – “CLR WDT1” and “CLR WDT2”. Of these two types of instruction, only one can be active depending on the configuration option – “CLR WDT times selection option”. If the “CLR WDT” is selected (i.e., CLRWDT times equal 1), any execution of the “CLR WDT” instruction will clear the WDT. In case “CLR WDT1” and “CLR WDT2” are chosen (i.e., CLRWDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out. Page 30 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.14 Power Down Operation - HALT The HALT mode is initialized by the “HALT” instruction and results in the following. ‧The system oscillator will be turned off but the WDT oscillator keeps running (if the WDT oscillator is selected). ‧The contents of the on-chip RAM and of the registers remain unchanged. ‧WDT will be cleared and recounted again (if the WDT clock source is from the WDT oscillator). ‧All I/O ports maintain their original status. ‧The PDF flag is set but the TO flag is cleared. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes device initialization, and the WDT overflow performs a “warm reset”. After examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared by system power-up or by executing the “CLR WDT” instruction, and is set by executing the “HALT” instruction. The TO flag is set if WDT time-out occurs, and causes a wake-up that only resets the program counter and SP, the others circuits keep their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by configuration options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to “1” before entering the “HALT” status, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the Wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Page 31 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.15 Reset (The RESB pin can be used by configuration option) There are five ways in which reset may occur. ‧Power-on reset ‧RESB reset during normal operation ‧RESB reset during HALT ‧WDT time-out reset during normal operation ‧WDT time-out reset during HALT The WDT time-out during HALT differs from other chip reset conditions, since it can perform a “warm reset” that resets only the program counter and SP and leaves the other circuits at their original state. Some registers remain unaffected during other reset conditions. Most registers are reset to the “initial condition” when the reset conditions are met. Examining the PD and TO flags, the program can distinguish between different “chip resets”. VDD VDD 0.01F* 100k 100k RES RES 10k 0.1F Basic Reset Circuit 0.1F* Hi-Nosie Reset Circuit Reset Circuit Note: “*” Make the length of the wiring, which is connected to the RESB pin as short as possible, to avoid noise interference. Note: Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the Hi-noise Reset Circuit. (With RESB pin by option) TO PDF RESET Conditions 0 0 RESB reset during power-up u u RESB reset or LVR during normal operation 0 1 RESB wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT wake-up HALT Note: “u” means unchanged (Without RESB pin by option) TO PDF RESET Conditions 0 0 Power-on reset u u LVR reset during normal operation 1 u WDT time-out during normal operation Page 32 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 1 1 WDT wake-up HALT Note: “u” means unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RESB reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from the HALT will enable the SST delay. An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RESB reset). The functional unit chip reset status is shown below. Program Counter 000H Interrupt Disable Prescaler, Divider Cleared WDT Clear. After master reset, WDT begins counting Timer/event Counter Off PPG Timer Off PPG, IOFF output Floating Input/output Ports Input mode Stack Pointer Points to the top of the stack VDD RES tRSTD VDD SST Time-out Power on reset Chip Reset SST Time-out (With RESB pin by option) tRSTD (Without RESB pin by option) Reset Timing Chart HALT Warm Reset WDT WDT * Time-out Reset HALT Warm Reset External WDT RES WDT SST 10-bit Ripple Counter OSC1 Cold Reset OSC1 Time-out Reset SST 10-bit Ripple Counter Cold Reset Power-on Detection *:This function is selected by ROM code option Power-on Detection (With RESB pin by option) (Without RESB pin by option) Reset Configuration The register states are summarized below: Page 33 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B WDT Time-out (Normal Operation) uuuu uuuu uuuu uuuu ---- ---0 uuuu uuuu 000H uuuu uuuu -uuu uuuu --1u uuuu RESB Reset (Normal Operation) uuuu uuuu uuuu uuuu ---- ---0 uuuu uuuu 000H uuuu uuuu -uuu uuuu --uu uuuu RESB Reset (HALT) uuuu uuuu uuuu uuuu ---- ---0 uuuu uuuu 000H uuuu uuuu -uuu uuuu --01 uuuu WDT Time-out (HALT)* uuuu uuuu uuuu uuuu ---- ---u uuuu uuuu 000H uuuu uuuu -uuu uuuu --11 uuuu -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC PC PCC CTRL0 CMP0C CMP1C CMP2C CMP3C INTC1 MFI PPGC PPGTA PPGTB PPGTEX ADRL ADRH xxxx 00-0 xxxx 00-0 1111 1111 --11 --11 1111 1111 0000 0001 0001 0001 0001 -000 -000 0000 xxxx xxxx ---x xxxx xxxx xxxx 1000 xxxx -000 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 -000 -000 --00 xxxx xxxx ---x ---xxxx xxxx 00-0 xxxx 00-0 1111 1111 --11 --11 1111 1111 0000 0001 0001 0001 0001 -000 -000 0000 xxxx xxxx ---x xxxx xxxx xxxx 1000 xxxx -000 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 -000 -000 --00 xxxx xxxx ---x ---xxxx xxxx 00-0 xxxx 00-0 1111 1111 --11 --11 1111 1111 0000 0001 0001 0001 0001 -000 -000 0000 xxxx xxxx ---x xxxx xxxx xxxx 1000 xxxx -000 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 -000 -000 --00 xxxx xxxx ---x ---xxxx xxxx 00-0 xxxx 00-0 1111 1111 --11 --11 1111 1111 0000 0001 0001 0001 0001 -000 -000 0000 xxxx xxxx ---x xxxx xxxx xxxx 1000 xxxx -000 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 -000 -000 --00 xxxx xxxx ---x ---xxxx uuuu uu-u uuuu uu-u uuuu uuuu --uu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu -uuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu -uuu --uu uuuu uuuu ---u ---uuuu ADCR ACSR CTRL1 CTRL2 CTRL3 OPAC PWLT CTRL4 TMR2 TMR2C CMPSC HADR HCR HSR HDR PCRL PCRH PWM PWMC 01----0000 --00 -000 0001 xxxx --00 xxxx ---0 0000 xxxx 0--0 100xxxx 0000 ---xxxx ---- 0000 --00 0000 0000 0000 0000 xxxx 0000 xxxx -000 --00 xxx0---0-1 xxxx 0000 0000 xxxx -000 01----0000 --00 -000 0001 xxxx --00 xxxx ---0 0000 xxxx 0--0 100xxxx 0000 ---xxxx ---- 0000 --00 0000 0000 0000 0000 xxxx 0000 xxxx -000 --00 xxx0---0-1 xxxx 0000 0000 xxxx -000 01----0000 --00 -000 0001 xxxx --00 xxxx ---0 0000 xxxx 0--0 100xxxx 0000 ---xxxx ---- 0000 --00 0000 0000 0000 0000 xxxx 0000 xxxx -000 --00 xxx0---0-1 xxxx 0000 0000 xxxx -000 01----0000 --00 -000 0001 xxxx --00 xxxx ---0 0000 xxxx 0--0 100xxxx 0000 ---xxxx ---- 0000 --00 0000 0000 0000 0000 xxxx 0000 xxxx -000 --00 xxx0---0-1 xxxx 0000 0000 xxxx -000 uu----uuuu --uu -uuu uuuu uuuu --uu uuuu ---u uuuu uuuu u--u uuuuuuu uuuu ---uuuu ---- uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu --uu uuuu---u-u uuuu uuuu uuuu uuuu -uuu Register Reset (Power On) MP0 MP1 BP ACC Program Counter TBLP TBLH STATUS xxxx xxxx ---xxxx 000H xxxx -xxx --00 INTC0 Note: xxxx xxxx ---0 xxxx xxxx xxxx xxxx “*” stands for “warm reset” “u” stands for “unchanged” “x” stands for “unknown” Page 34 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B “-” stands for “unimplemented” Page 35 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.16 Peripheral Clock Output The device provides peripheral output (PCK). PCK is pin-shared with PC1 selected by PC1 configuration option. Once the PC1 is selected as the PCK output and the output function of PC1 is enabled (PCC1 =”0”), writing “1” to PC1 data register will enable the PCK output function and writing “0” will force the PC1 to remain at “0”. The output frequency is selected by PCKPSC2~0 bits in system control register 0. 8.17 Timer/Event Counters •Prescaler 7-stage prescaler fSYS T0PSC2 T0PSC1 T0PSC0 8-1 MUX fT0 T1PSC2 T1PSC1 T1PSC0 8-1 MUX fT1 T2PSC2 T2PSC1 T2PSC0 8-1 MUX fT2 Prescaler • Timer/Event Counter Three timer/event counters (TMR0, TMR1 and TMR2) are implemented in the microcontroller. The Timer/Event Counter 0 contains an 8-bit programmable count-up counter and the clock may come from an external source or an internal clock source. The Timer/Event Counter 1/2 contains an 8-bit programmable count-up counter and the clock comes from an internal clock source only. An internal clock source comes from fSYS. The external clock input allows the user to count external events, measure time internals or pulse widths. While using the internal clock allows the user to generate an accurate time base. Data bus fT0 TMR0 T0M1 T0M0 MUX 8-bit Timer/Event Counter Preload Register Reload INT0 TMR0ECS T0M1 T0M0 T0ON T0E 8-bit Timer/Event Counter (TMR0) Pulse Width Measurement Mode Control Overflow To Interrupt NOTE: INT0 is inverted or non-inverted de-bounce signal from INTB pin or comparator 0 output “C0VO” by software option Timer/Event Counter 0 Page 36 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B Data bus 8-bit Timer/Event Counter Preload Register Reload INH SET_T1ON T1M1 T1M0 T1ON T1OV fT1 Timer 1 Control Circuit 8-bit Timer/Event Counter (TMR1) SET_T1ON T1OV Overflow to Interrupt T1M1 T1M0 R Q S Timer/Event Counter 1 Data bus 8-bit Timer/Event Counter Preload Register fT2 T2ON Reload 8-bit Timer/Event Counter (TMR2) Overflow To Interrupt Timer/Event Counter 2 There are six registers related to the Timer/Event Counter; TMR0 (0DH), TMR0C (0EH), TMR1 (10H), TMR1C (11H), TMR2 (2DH) and TMR2C (2EH). Writing TMR0/TMR1/TMR2 makes the written data be placed in the Timer/Event Counter 0/1/2 preload register and reading TMR0/TMR1/TMR2 retrieves the contents of the Timer/Event Counter 0/1/2. The TMR0C, TMR1C and TMR2C are timer/event counter control register 0/1/2, which defines the operation mode, counting enable or disable and an active edge. The T0M0/T1M0/T2M0 and T0M1/T1M1/T2M1 bits define the operation mode. The event count mode (for Timer/Event Counter 0 only) is used to count external events, which means that the clock source is from an external (TMR0) pin or INT0. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. The pulse width measurement mode (only for Timer/Event Counter 0) can be used to count the high or low level duration of the external (TMR0) pin or INT0, and the counting is based on the internal selected clock source. The Timer/Event Counter 1 has a mode 0 for PPG usage. In this mode, the timer starts counting when PPG is stopped and stops when overflow. That means the T1ON will be set once PPG stopped and cleared when overflow. This mode is used to implement the PPG non-retriggered function. In the event count or timer mode, the Timer/Event Counter starts counting at the current contents in the timer/event counter and ends at FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag. Page 37 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B In the pulse width measurement mode with the values of the T0ON and T0E bits equal to 1, after receiving a transient from low to high (or high to low if the T0E bit is “0”), it will start counting until returns to the original level and resets the T0ON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the T0ON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request. To enable the counting operation, the Timer ON bit (T0ON; bit 4 of TMR0C, T1ON; bit 4 of TMR1C, T2ON; bit 4 of TMR2C) should be set to “1”. In the pulse width measurement mode, the Timer ON bit is automatically cleared after the measurement cycle is completed. But in timer or event counter modes, the Timer ON bit can only be reset by instructions. In the mode 0 of Timer/Event Counter 1, T1ON is set once PPG stopped and cleared by overflow. No matter what the operation mode is, writing a 0 to ET0I/ET1I/ET2I disables the related interrupt service. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the timer/event counter (reading TMR0/TMR1/TMR2) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1/TMR2 register first, before turning on the related timer/event counter, for proper operation since the initial value of TMR0/TMR1/TMR2 is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. The bit0~bit2 of the TMR0C/TMR1C/TMR2C can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The definitions are as shown. Bit No. Label 0 1 2 T0PSC0 T0PSC1 T0PSC2 3 T0E Function Define the prescaler stages. T0PSC2, T0PSC1, T0PSC0= 000 : fT0 = fSYS 001 : fT0 = fSYS /2 010 : fT0 = fSYS /4 011 : fT0 = fSYS /8 100 : fT0 = fSYS /16 101 : fT0 = fSYS /32 110 : fT0 = fSYS /64 111 : fT0 = fSYS /128 Define the active edge of timer/event counter: In event counter mode: 1: count on falling edge 0: count on rising edge Page 38 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 4 T0ON 5 - 6 7 T0M0 T0M1 In pulse width measurement mode: 1: start counting on rising edge, stop on falling edge 0: start counting on falling edge, stop on rising edge Enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as “0” Define the operating mode.T0M1, T0M0 = 01: Event count mode 10: Timer mode 11: Pulse width measurement mode 00: Unused TMR0C register Bit No. Label 0 1 2 T1PSC0 T1PSC1 T1PSC2 3 - 4 T1ON 5 - 6 7 T1M0 T1M1 Function Define the prescaler stages. T1PSC2, T1PSC1, T1PSC0= 000 : fT1 = fSYS 001 : fT1 = fSYS /2 010 : fT1 = fSYS /4 011 : fT1 = fSYS /8 100 : fT1 = fSYS /16 101 : fT1 = fSYS /32 110 : fT1 = fSYS /64 111 : fT1 = fSYS /128 Unused bit, read as “0” Enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as “0” Defines the operating mode. T1M1, T1M0 = 01: Unused 10: Timer mode 11: Unused 00: Mode 0 (PPG non-retrigger functions) TMR1C register Bit No. Label 0 1 2 T2PSC0 T2PSC1 T2PSC2 3 - 4 T2ON 5 6 7 - Function Define the prescaler stages.T2PSC2, T2PSC1, T2PSC0= 000 : fT2 = fSYS 001 : fT2 = fSYS /2 010 : fT2 = fSYS /4 011 : fT2 = fSYS /8 100 : fT2 = fSYS /16 101 : fT2 = fSYS /32 110 : fT2 = fSYS /64 111 : fT2 = fSYS /128 Unused bit, read as “0” Enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as “0” Unused bits, both read as “0” TMR2C register Page 39 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.18 Programmable Pulse Generator The device provides one 9-bit PPG output channel. The PPG has a programmable period of 512xT, where T is 1/fSYS for an output pulse width. The PPG pulse width could be limited with using pulse width limiter timer. The PPG output is pin shared with PA4 selected by configuration option. Once the PPG output function is selected, the PA4 I/O function and pull-high resistor are disabled. The PPG detects a trigger input, and outputs a single pulse. The trigger source may come from INT00 falling edge or/and software trigger bit, which can be configured by software. The PPG can output an active low or active high pulse by setting the polarity control bit (PLEV) of configuration option. The PPG output is floating when VDD is between 0.6V and 1.2V, Reset occurs, and the PPG is inactive; an external pull-high or pull-low resistor (depended on polarity configuration option) is need. PRSEN PPGDL5~0 ..... M INT0 triger INT0S triger U mode delay X INT M U X de-bounce INTS DBC5~0 INT00 CP1N VR1 PWL VR4 fSYS reload control Overflow PPG Timer (9 bit) RLBF = 0, reload from A RLBF = 1, reload from B ( RLBF is set by C1VO falling edge if C1CTL=0, cleared by software ) one shot PWL CLR_PRSEN PPGOUT C1CTL Debounce RLBF C1VO CMP1 0.5us control CP1P + C1RLEN CMP1 Debounce ON PPG Mode (Configuration) + Control C2VO M Debounce CMP2 U 0.5us X CMP2 Debounce ON (Configuration) C2VOINV C3VO CP3N M CMP3 Debounce C3VOB U + 0.5us X CMP3 Debounce Enable C3VOINV (Configuration) fSYS Reload PPG Timer On/Off PPG stop PSPEN M U X PLEV one shot one shot PPG 1.Floating for reset, inactive, and a condition 0.6V<VDD<1.2V 2.Hi/Lo by PLEV for active PPG Output Logic IOFF Output Logic CMP2EN CMP1EN PC0/AN10/CP3N PC1/PCK/CP3N Preload Register A Preload Register B CMP0EN CP2P VR2 VR3 CP2N PPG_start fSYS CMP0 C0VO + AN9 CP0P Data bus PPG start PST C2VOB CP0N C2INT PPGOUT TRGMOD INTINV C1INT Note: PRSEN will be cleared by the falling edge of C2VOB or C3VOB CLR_PRSEN PRSEN control INH IOFF 1.Floating for reset 2.Hi/Lo when PPG inactive/active SET_T1ON S Q PWL R Reload Pulse Width Limit Timer Preload Register PWL fSYS/2 fPPG Pulse Width Limit Timer (PWLT) Reload Overflow rising or fallging selection trigger edge control PPG start PPG active (Sync mode) start SYNC option PPG Block Diagram Page 40 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B The PPG module consists of one PPG timer, one PPG Mode Control and four comparators. The PPG timer consists of one 9-bit up-counter timer, and two 9-bit preload data registers. The programmable pulse generator (PPG) starts counting at the current contents in the preload register and ends at “1FFH 000H”. A “000H” data write to the PPGTA/B register yields a pulse width 512xT output. Once an overflow occurs, the counter is reloaded from the PPG timer counter preload register, and generates a signal to stop the PPG timer. The software trigger bit (PST) will be cleared when the PPG timer overflow occurs. • Non-retrigger function The PPG unit has non-retrigger function to inhibit further PPG trigger. The PPG will be non-triggered by one of following condition: (1) PPG is active (2) During the non-retrigger period which starts counting once PPG stopped (Only available by using with mode 0 of Timer/Event Counter 1, the non-trigger period is decided by Timer/Event Counter 1) Timer1 mode0 on Timer1 mode0 overflow & off non-retrigger period PPGOUT PPG active PPG inactive PPG is always non-retrigger if PPG is active Debounce for C1VO/C2VO Note : The control bits ,C0CMPOP, C1CMPOP, C2CMPOP, and C3CMPOP, is used to set output status of C0VO, V1VO, C2VO, and C3VO, which have not been debounced. • Pulse width limit function The PPG unit has pulse width limit function to stop PPG output. The PPG output will be stopped once the pulse width reaching the limit. This function is implemented by a pulse width limit timer which starts counting once PPG is triggered and stops once overflow or PPG is stopped. The pulse width limit is (256-PWLT)/ (fSYS/2), where PWLT is pulse width limit timer register. To start the PPG operation: ‧ Enable PPG function by configuration option. Page 41 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B ‧ Set the PPG output active level (PLEV; by configuration option) ‧ Set the PPG timer start counting is synchronized with system clock (f SYS) or not (PTSYN; by configuration option) ‧ PPG input mode selection (PRSEN, PSPEN, INTS, INTINV, PPGDL5~0, DBC5~0, C2VOINV) ‧ Set the PPG output pulse width. Writing data to PPGTA/B and PPGTEX ‧ Decide using C1VO falling edge to enable the reload function from preload register B or not (C1RLEN, C1CTL) ‧ Decide using the non-retrigger period function or not (by using with mode 0 of Timer/Event Counter 1) ‧ Set pulse width limit timer for pulse width limit function. (PWLT) ‧ When PPG input is triggered by INT00 falling edge transition or triggered by a software bit (PST) being set to “1”, the PPG will start counting from the current content of preload register. When PPG input is trigged by a software bit (PST) being cleared to “0”, C2VOB falling edge, PPG timer overflow occurs, or a pulse width limit condition occurs, the PPG will stop counting. Page 42 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B • PPG Control Register Bit No. PPGC(20H) POR value 7 PST 0 6 PRSEN 0 5 PSPEN 0 4 RLBF 0 3 - 2 - 1 TRGMOD 0 0 C1RLEN 0 C1RLEN: Enable or disable C1VO falling edge to set RLBF for PPG timer reloads from preload register B (0: disable, 1: enable) Which is available when C1CTL=0 (CP1P and CP1N are connected to programmable internal reference voltage VR1 and PA3/CP0P/TMR pin respectively) TRGMOD: select single or double falling edge of INT0 as the input of trigger delay circuit which produce INT00. (0: single, 1: double), INT0: inverted or non-inverted de-bounce signal from INTB or comparator 0 output “C0VO” by software option. RLBF: PPG reload control bit. (0: PPG timer reloads from preload register A, 1: PPG timer reloads from preload register B) PSPEN: Enable or disable stopping the PPG timer using the trigger input of C2VOB or C3VOB (inverted or non-inverted signal from the output of comparator 2 or comparator 3 by software option) trigger input. (0: disable, 1: enable) PRSEN: Enable or disable restarting the PPG timer using INT00 trigger input (0: disable, 1: enable) PST: PPG software trigger bit. (0: Stop PPG, 1: Restart PPG) Normally, PPG timer is reloaded from preload register A if RLBF=0. If C1RLEN is set and C1CTL is cleared, the C1VO falling edge caused by comparator output will set RLBF and then PPG timer will be reload from preload register B until RLBF is cleared by software. The PRSEN is the PPG restarting enable or disable bit using INT00 trigger input. If this bit is enabled, the PPG timer restarting input can be trigger by INT00 falling edge. PRSEN 0 1 Description Disable restarting the PPG timer using INT00 trigger input. PPG module output can be restarted by software control (PST) only. Enable restarting the PPG timer using INT00 trigger input. PPG module output can be restarted by INT00 falling edge trigger or software control (PST is set to “1”). The PSPEN is the PPG stopping enable or disable bit using the trigger input of C2VOB or C3VOB. If this bit is enabled, the PPG timer stopping input can be triggered and an IOFF output will active high by the falling edge of C2VOB or C3VOB. The IOFF output is floating during reset, high when PPG is inactive, and low when PPG is active. The PRSEN bit will be cleared by the falling edge of C2VOB or C3VOB, no matter the PPG is in active period or not. This will prevent PPG module output be restarted by INT00 falling edge again, only restarted by software control is permitted until PRSEN is set again by software. PSPEN 0 Description Disable stopping the PPG timer using the trigger input of C2VOB or C3VOB. PPG module output can be stopped by software control (PST) only Page 43 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B Enable stopping the PPG timer using the trigger input of C2VOB or C3VOB. 1 PPG module output can be stopped by C2VOB falling edge trigger, C3VOB falling edge trigger, or software control (PST is set to “0”) The PST is a software trigger bit, if this bit is set to “1”, the PPG timer will start counting and this bit will be cleared when the PPG timer overflow occurs or PPG timer stop counting. If this bit is cleared to “0”, the PPG timer will stop counting. When the PPG timer is counting and if a falling edge generates from INT00 or a software control bit (PST) is set, the PPG timer counter is not affected, the trigger from INT00 or PST is not useful. The PST can also be used as a status bit of PPG timer output. The PPG module output pulse active level is decided by configuration option (PLEV), if clear this bit to “0”, the PPG output will be defined as an active high output, if the PLEV bit is set to “1”, the PPG output will be defined as an active low output. Another function is provided, that is the PPG timer start counting is synchronized with clock or not, decided by configuration option (PTSYN). • PPGTA, PPGTB (PPG timer preload register A/B) PPGTA PGTA7 PGTA6 PGTA5 PGTA4 PGTA3 PGTA2 PGTA1 PGTA0 PPGTB POR value PGTB7 x PGTB6 x PGTB5 x PGTB4 x PGTB3 x PGTB2 x PGTB1 x PGTB0 x PPGTEX - - - PGTB8 - - - PGTA8 POR value - - - x - - - x “-“stands for unimplemented, read as “0” To control PPG pulse starting delay ≦ 0.5*(1/ fSYS) when start synchronized with clock is selected, clock (fSYS) edge trigger type (raising or falling), which triggers PPG, varies with next coming clock transition once PPG starts. After PPG starts, the PPG output becomes active and begins to count as soon as first transition (falling or rising) of system clock comes. After first trigger done, the following clock edge trigger type is decided by the first one. For example, once PPG starts and next coming clock transition is falling edge, the PPG will be trigger by falling edge until PPG stops and vice versa. EX1: Since the first trigger type is falling edge after PPG starts, the PPG timer is triggered by falling edge until PPG stops. tSYS system clock start trigger PPG pulse < 0.5 tSYS PPG timer n n+1 n+2 Page 44 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B EX2: Since the first trigger type is raising edge after PPG starts, the PPG timer is triggered by raising edge until PPG stops. tSYS system clock start trigger PPG pulse < 0.5 tSYS PPG timer n n+1 n+2 Any action causing PPG stop – such as PPG timer overflow, C2VOB falling edge (if PSPEN=1), software stop (PST=10) or reaching pulse limit -- will cause actions as following: •PPG timer will be reloaded •PST is cleared •PPG is inactive PPGCFG Description 0 PA4 is GPIO. 1 PA4 is PPG output. PPG Configuration Option PB2CFG 0 1 Description PB2 is functioned as GPIO or AN1 by PCR1 bit PB2 is function as IOFF output. This is only available only when PPG output is enabled in PPG configuration option. PB2 Configuration Option Page 45 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.19 Comparator The device includes 4 integrated comparators in PPG module. Either inputs of comparator 0 can be connected to AN9 selected by C0N2AN9 bit in comparators control register. The non-inverting input of comparator 1 is connected to programmable internal reference voltage VR1; Moreover, the inverting input of comparator 1 can be selected between PA5/CP1N/AN7 and PA3/CP0P/TMR0 by C1CTL bit. The non-inverting input of comparator 2 can be selected between PA7/CP2P/AN5 and programmable internal reference voltage VR2 by comparator 2 configuration options; Moreover, the inverting input of comparator 2 can be selected between PA6/CP2N/AN6 and programmable internal reference voltage VR3 by comparator 2 configuration options. The inverting input of comparator 3 can be selected between PC0/AN10/CP3N and PC1/PCK/CP3N by comparator 3 configuration options; Moreover, the non-inverting input of comparator 3 is connected to programmable internal reference voltage VR4. The input offset is adjustable by using a common mode input to calibrate the offset value. Vr CPnN CPnP CnVO S1 CnVO S2 S3 The calibration steps as following: (1) Setting CnCOFM=1 to offset cancellation mode (S3 is closed) (2) Setting CnCRS to select which input pin as reference voltage (S1 or S2 is closed) (3) Adjusting CnCOF0~CnCOF4 until output status is changed (4) Setting CnCOFM=0 to normal comparator mode , where n=0, 1 or 2. CMP0C register (Comparator 0 control register): Bit 4~0 5 Name C0COF4~C0COF0 C0CRS 6 C0COFM 7 C0CMPOP Function Comparator input offset voltage cancellation control bits Comparator input offset voltage cancellation reference selection bit 1/0 : select CP0P/CP0N as the reference input Input offset voltage cancellation mode and comparator mode selection 1: input offset voltage cancellation mode 0: comparator mode Comparator output; positive logic POR 10000B 0 0 0 CMP1C register (Comparator 1 control register): Bit 4~0 5 Name C1COF4~C1COF0 C1CRS Function Comparator input offset voltage cancellation control bits Comparator input offset voltage cancellation reference selection bit 1/0 : select CP1P/CP1N as the reference input POR 10000B 0 Page 46 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 6 C1COFM 7 C1CMPOP Input offset voltage cancellation mode and comparator mode selection 1: input offset voltage cancellation mode 0: comparator mode Comparator output; positive logic 0 0 CMP2C register (Comparator 2 control register): Bit 4~0 5 Name C2COF4~C2COF0 C2CRS 6 C2COFM 7 C2CMPOP Function Comparator input offset voltage cancellation control bits Comparator input offset voltage cancellation reference selection bit 1/0 : select CP2P/CP2N as the reference input Input offset voltage cancellation mode and comparator mode selection 1: input offset voltage cancellation mode 0: comparator mode Comparator output; positive logic POR 10000B 0 0 0 CMP3C register (Comparator 3 control register): Bit 4~0 5 Name C3COF4~C3COF0 C3CRS 6 C3COFM 7 C3CMPOP Function Comparator input offset voltage cancellation control bits Comparator input offset voltage cancellation reference selection bit 1/0 : select CP3P/CP3N as the reference input Input offset voltage cancellation mode and comparator mode selection 1: input offset voltage cancellation mode 0: comparator mode Comparator output; positive logic POR 10000B 0 0 0 CMPSC (Comparators control register): Bit 0 Name C0N2AN9 1 C1CTL 2 3 4 5 6 7 C0HYSON C1HYSON C2HYSON C3HYSON Function Control comparator 0 inputs connection to AN9 (0: CP0P connected to AN9, 1:CP0N connected to AN9) Control comparator 1 inputs connection (0: The inverting input of comparator 1 is connected to PA3/CP0P/TMR0 1: The inverting input of comparator 1 is connected to PA5/CP1N/AN7) Not implemented, read as “0” Not implemented, read as “0” Enable or disable comparator 0 hysteresis. (0: disable, 1: Enable) Enable or disable comparator 1 hysteresis. (0: disable, 1: Enable) Enable or disable comparator 2 hysteresis. (0: disable, 1: Enable) Enable or disable comparator 3 hysteresis. (0: disable, 1: Enable) POR 0 0 0 0 0 0 Configuration options determine the comparators function to be used: CMP0EN Description Disable the comparator 0. 0 PA2/CP0N/INTB and PA3/CP0P/TMR0 are GPIO pins but in the case that comparator 1 is enabled with the non-inverting input of comparator 1 connected to PA3 (C1CTL=0), PA3 I/O function and pull-high are disabled. Enable the comparator 0. 1 PA2/CP0N/INTB and PA3/CP0P/TMR0 are comparator 0 inverting/ non-inverting input pins. PA2/3 I/O function and pull-high are disabled. CMP1EN Description Disable the comparator 1. 0 PA5/CP1N/AN7 is a GPIO pin or analog input. PA3/CP0P/TMR0 is GPIO pin if comparator 0 is also disabled (no matter what C1CTL bit is). Page 47 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B Enable the comparator 1. 1 PA5/CP1N/AN7 or PA3/CP0P/TMR0 is comparator 1 inverting input pin selected by C1CTL bit. If PA5/CP1N/AN7 is selected, AN7 function can also be used. No matter which pin is selected, its I/O function and pull-high are disabled. CMP2CFG[1:0] 00 Description Disable the comparator 2. PA6/CP2N/AN6 and PA7/CP2P/AN5 are GPIO pins or analog inputs. Enable the comparator 2. 01 The comparator 2 inverting input is connected to programmable internal reference voltage VR3. PA7/CP2P/AN5 is comparator 2 non-inverting input pin. AN5 function can also be used. PA7 I/O function and pull-high are disabled. PA6/CP2N/AN6 is a GPIO pin or analog input. Enable the comparator 2. 10 PA6/CP2N/AN6 is comparator 2 inverting input pin. AN6 function can also be used. The comparator 2 non-inverting input is connected to programmable internal reference voltage VR2. PA6 I/O function and pull-high are disabled. PA7/CP2P/AN5 is a GPIO pin or analog input. Enable the comparator 2. 11 PA6/CP2N/AN6 is comparator 2 inverting input pin. AN6 function can also be used. PA7/CP2P/AN5 is comparator 2 non-inverting input pin. AN5 function can also be used. PA6 and PA7 I/O function and pull-high are disabled. CMP3CFG[1:0] 00 Description Disable the comparator 3. PC0/CP3N/AN10 and PC1/CP3N/PCK are GPIO pins or analog inputs. Enable the comparator 3. 01 The comparator 3 non-inverting input is connected to programmable internal reference voltage VR4. PC0/CP3N/AN10 is comparator 3 inverting input pin. AN10 function can also be used. PC0 I/O function and pull-high are disabled. PC1/CP3N/PCK is a GPIO pin or PCK pin. Enable the comparator 3. 1x The comparator 3 non-inverting input is connected to programmable internal reference voltage VR4. PC1/CP3N/PCK is comparator 3 inverting input pin. PC1 I/O function, PCK function, and pull-high are disabled. PC0/CP3N/AN10 is a GPIO pin or analog input. Page 48 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.20 Operational Amplifier The device includes an integrated operational amplifier. It can be enabled by OPA enable configuration option, OPAEN [1:0] (only available when IRC or ERC is selected in Oscillator configuration). The non-inverting input can be connected to VSS directly or through a 1k ohm resistor determined by configuration option, OPAPCFG. The inverting input can be connected to OPAN pin directly or through a 1k ohm resistor determined by configuration option, OPANCFG. The output can be connected back to the inverting input through a 60k ohm resistor or not determined by configuration option, OPAOCFG. The output can be connected to PA1/OPAO/AN8/OSC1 pin or connected to PB3/AN2 pin through a 10k ohm resister by configuration, OPAEN [1:0]. The input offset is adjustable by using a common mode input to calibrate the offset value. Vr OPAO OPAOCFG OPANCFG 1 PA0/OPAN/OSC2 0 OPAR3 1k ohm 0 1 OPAR1 60k ohm OPAEN.0 S1 0 S2 PA1/OPAO/AN8/OSC1 1 OPAEN.1 OPAR4 AN8 0 10k ohm 1 0 OPAPCFG S3 1 OPAR2 1k ohm PB3/AN2 M U X ADC AN2 ACS3~0 VSS The calibration steps as following: (1) Setting OPAFM=1 to offset cancellation mode (S3 is closed) (2) Setting OPARS to select which input pin as reference voltage (S1 or S2 is closed) (3) Adjusting OPAOF0~OPAOF4 until output status is changed. (4) Setting OPAOFM=0 to normal operational amplifier mode OPAC register (Operational Amplifier Control Register): Bit 4~0 5 Name OPAOF4~OPAOF0 OPARS 6 OPAOFM Function Operational amplifier input offset voltage cancellation control bits Operational amplifier input offset voltage cancellation reference selection bit 1/0 : select OPAP/OPAN as the reference input Input offset voltage cancellation mode and operational amplifier mode selection 1: input offset voltage cancellation mode 0: operational amplifier mode POR 10000B 0 0 Page 49 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 7 OPAOP Operational amplifier output; positive logic 0 OPA enable configuration options determine the operational amplifier function to be used: OPAEN[1:0] Description Disable the operational amplifier. Then PA0 and PA1 function are decided by oscillator configuration option and PCR8 bit in PCRH register. 00 1. PA0 as OSC2, PA1 as OSC1 (OSC configuration =XTAL) 2. PA0 as GPIO, PA1 as OSC1 (OSC configuration =ERC) 3. PA0 as GPIO, PA1 as GPIO or AN8 (OSC configuration =IRC) Enable the operational amplifier with OPAO pin-out. 01 Only available when OSC configuration is IRC. PA0 as amplifier inverting input pin: OPAN; OPA output connected to PA1/OPAO/AN8/OSC1 pin (OSC configuration =IRC). PA1 I/O function and pull-high are disabled. AN8 function can be used. Enable the operational amplifier with OPA output connected to PB3/AN2 pin through a resister (OPAR4). PB3 I/O function and pull-high are disabled. AN2 function can be used. 10 Only available when OSC configuration is ERC or IRC. 1. PA0 as amplifier inverting input pin: OPAN; PA1 as OSC1 (OSC configuration =ERC) 2. PA0 as amplifier inverting input pin: OPAN; PA1 as GPIO or AN8 (OSC configuration =IRC) Reserved. 11 Three additional configuration options determine the operational amplifier structure to be used if operation amplifier function is allowed to be enabled: OPANCFG Description 0 OPAN connected to inverting input directly. 1 OPAN connected to inverting input through a resistor (OPAR3) OPAPCFG Description 0 Non-inverting input connected to VSS through a resistor (OPAR2). 1 Non-inverting input connected to VSS directly. OPAOCFG Description 0 OPA output is not connected back to inverting input. 1 OPA output connected back to inverting input through a resistor. Page 50 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.21 I/O Port There are 22 bidirectional input/output lines in the microcontroller, labeled as PA, PB, and PC, which are mapped to the data memory of [12H], [14H], and [16H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction “MOV A,[m]” (m=12H, 14H, or 16H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, and PCC) to control the input/output configuration. With this control register, CMOS (except for PB0)/ NMOS (only for PB0) output or Schmitt trigger input with or without pull-high resistor (PB0 has no pull-high resistor) structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write “1”. The input source also depends on the control register. If the control register bit is “1”, the input will read the pad state. If the control register bit is “0”, the contents of the latches will move to the internal bus. The latter is possible in the “read-modify-write” instruction. For output function, except for PB0 CMOS is the only configuration, PB0 is NMOS. These control registers are mapped to locations 13H, 15H, and 17H. After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high configuration options). Each bit of these input/output latches can be set or cleared by “SET [m].i” and “CLR [m].i” (m=12H, 14H, or 16H) instructions. Some instructions first input data and then follow the output operations. For example, “SET [m].i”, “CLR [m].i”, “CPL [m]”, “CPLA [m]” read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O port except PB0 has a pull-high configuration option. Once the pull-high configuration option is selected, the I/O port has a pull-high resistor, otherwise, there’s none. Take note that a non-pull-high I/O port operating in input mode will cause a floating state. It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. Page 51 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B VDD Control Bit Data Bus D Write Control Register Q CK Q S Chip Reset Read Control Register Pull-high option Data Bit D Q Write Data Register CK PCRx (ANx only) Q S M U X PCK, PWM Read Data Register PA0/OPAN/OSC2 PA1/OPAO/OSC1/AN8 PA2/CP0N/INT PA3/CP0P/TMR0 PA5/CP1N/AN7 PA6/CP2N/AN6 PA7/CP2P/AN5 PB1/SDA/AN0 PB2/IOFF/AN1 PB3/AN2 PB4/PWM/AN3 PB5/AN4 PC0/AN10/CP3N PC1/PCK/CP3N PC2~6 PC7/AN11 PCK, PWM option M U X System Wake-up (PA only) Wake-up option INT for PA2 Only TMR0 for PA3 Only To A/D Converter (ANx only) ACS3~0 Data Bus Write Control Register Control Bit Pull-highOption PPG Option D Q CK Chip Reset Q S PA4/PPG Read Control Register Write Data Register Data Bit D Q CK Q S M U X From PPG/PPG Read Data Register M U X System Wake-up (PA only) Wake-up option reset signal From PPG PPG Option Input/Output Ports (except PB0) Page 52 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B Control Bit Data Bus Write Control Register D Q CK Q S Chip Reset PB0/SCL/RES Read Control Register Write Data Register Data Bit D Q CK Q S Read Data Register M U X RES for PB0 only Input/Output Port (PB0) Page 53 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.22 PWM The microcontroller provides one channel (6+2) bits PWM output shared with PB4. The PWM channel has it data register denoted as PWM. The frequency source of the PWM counter comes from fPWM which is derived from fSYS and selected by PWMPS2~0 bits of PWMC register. The PWM register is an 8-bit register. The waveforms of PWM outputs are as shown. Once the PB4 is selected as the PWM output and the output function of PB4 is enabled (PBC4=”0”), writing 1 to PB4 data register will enable the PWM output function and writing “0” will force the PB4 to stay at “0”. A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. The group 2 is denoted by AC which is the value of PWM.1~PWM.0. In a (6+2) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter Modulation cycle i (i=0~3) AC (0~3) i<AC i≧AC Duty Cycle (DC+1)/64 DC/64 The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. PWM Modulation Frequency PWM Cycle Frequency PWM Cycle Duty fPWM /64 fPWM /256 [PWM]/256 fPWM/2 [PWM] =100 PWM 25/64 25/64 25/64 25/64 25/64 26/64 25/64 25/64 25/64 26/64 26/64 26/64 25/64 25/64 26/64 26/64 26/64 26/64 25/64 26/64 [PWM] =101 PWM [PWM] =102 PWM [PWM] =103 PWM PWM modulation period : 64/fPWM Modulation cycle 0 Modulation cycle 1 Modulation cycle 2 Modulation cycle 3 Modulation cycle 0 PWM cycle : 256/fPWM (6+2)PWM Mode Page 54 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B Bit No. Label Function 2~0 PWMPSC2~0 7~3 - Define the prescaler stages. PWMPSC2, PWMPSC1, PWMPSC0= 000 : fPWM = fSYS 001 : fPWM = fSYS/2 010 : fPWM = fSYS/4 011 : fPWM = fSYS/8 100 : fPWM = fSYS/16 101 : fPWM = fSYS/32 110 : fPWM = fSYS/64 111 : fPWM = fSYS/128 Unused bit, read as “0” PWMC register PB4CFG Description 0 PB4 is functioned as GPIO or AN3 by PCR3 bit 1 PB4 is functioned as PWM output PB4 Configuration Option Page 55 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.23 ADC The 12 channels and 12-bit resolution A/D converter are implemented in this microcontroller. The reference voltage is VDD. The A/D converter contains 6 special registers which are; ADRL, ADRH, ADCR, ACSR, PCRL and PCRH. The ADRH and ADRL are A/D result register higher-order byte and lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be read to get the conversion result data. Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADRL D3 D1 D0 - - - - ADRH D11 D10 D9 D2 D8 D7 D6 D5 D4 Note: *: D0~11 is A/D conversion result data bit LSB~MSB ADRL and ADRH register The ADCR is an A/D converter control register, which defines the analog channel select, start A/D conversion control bit and the end of A/D conversion flag. The bit3~bit0 of the ADCR are used to select an analog input channel. There are a total of 12 channels to select. The EOCB bit (bit6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure the A/D conversion is completed, the START should remain at “0” until the EOCB is cleared to “0” (end of A/D conversion). Bit No. 3~0 Label Function ACS3~0 Defines the analog channel select. 5~4 - 6 EOCB Unused bits, read as “0” Indicates end of A/D conversion. (0 = end of A/D conversion) Each time PCR0~11 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. 7 START Starts the A/D conversion. (0->1->0= start; 0->1= Reset A/D converter and set EOCB to “1”) ADCR register Page 56 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B ACS3 ACS2 ACS1 0 0 0 0 AN0 0 0 0 1 AN1 0 0 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 1 0 0 0 AN8 1 0 0 1 AN9 1 0 1 0 AN10 0 1 1 AN11 1 ACS0 Analog Channel 1100~1111 Undefined, cannot be used Analog input channel selection The ACSR is A/D clock setting register, which is used to select the A/D clock source. Bit1 and bit0 of the ACSR are used to select A/D clock sources. Bit No. Label Function Selects the A/D converter clock source ADCS1, ADSC0: 1~0 ADCS1~0 00= system clock/2 01= system clock/8 10= system clock/32 11= undefined 6~2 - Unused bit, read as “0” 7 - Unused bit, read as “0” ACSR register The PCRH and PCRL registers defines the analog input configuration. If PCR11~0 are all zero, the ADC circuit is power off to reduce power consumption. Once an I/O line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D converter circuit is power on. Bit No. Label Function 2 0: PB1 is I/O if PB1 is not configured as SDA function by I C configuration option 0 PCR0 1: PB1 is analog input channel: AN0 if PB1 is not configured as SDA function by I C configuration 2 option 0: PB2 is I/O if PB2 is not configured as IOFF function by PB2 configuration 1 PCR1 2 PCR2 3 PCR3 1: PB2 is analog input channel: AN1 if PB2 is not configured as IOFF function by PB2 configuration 0: PB3 is I/O 1: PB3 is analog input channel: AN2 0: PB4 is I/O if PB4 is not configured as PWM function by PB4 configuration 1: PB4 is analog input channel: AN3 if PB4 is not configured as PWM function by PB4 configuration Page 57 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 0: PB5 is I/O 4 PCR4 5 PCR5 1: PB5 is analog input channel: AN4 0: PA7 is I/O if PA7 is not configured as CP2P function by comparator 2 configuration option 1: PA7 is analog input channel: AN5 with or without CP2P function by comparator 2 configuration option 0: PA6 is I/O if PA6 is not configured as CP2N function by comparator 2 configuration option 6 PCR6 1: PA6 is analog input channel: AN6 with or without CP2N function by comparator 2 configuration option 0: PA5 is I/O if PA5 is not configured as CP1N function by comparator 1 configuration option and comparator 1 input pin software option: C1CTL bit in comparators control register. 7 PCR7 1: PA5 is analog input channel: AN7 with or without CP1N function by comparator 1 configuration option and comparator 1 input pin software option: C1CTL bit in comparators control register. PCRL register Bit No. Label Function 0: PA1 is I/O if PA1 is not configured as OPAO or OSC1 function by OPA and Oscillator configuration 0 PCR8 option. 1: PA1 is analog input channel: AN8 with or without OPAO function by OPA configuration option if IRC is used by Oscillator configuration option. 0: Internal analog input channel AN9 disabled 1 PCR9 2 PCR10 3 PCR11 7~4 - 1: Internal analog input channel AN9 enabled 0: PC0 is I/O 1: PC0 is analog input channel: AN10 0: PC7 is I/O 1: PC7 is analog input channel: AN11 Unused bit, read as “0” PCRH register If users want to start an A/D conversion, define analog input configuration, select A/D clock source, select the converted analog channel, and give START bit a raising edge and falling edge (0→1→0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter interrupt occurs if the A/D interrupt is enabled. The EOCB bit is set to “1” when the START bit is set from “0” to “1”. Minimum one instruction cycle needed, Maximum ten instruction cycles allowed START EOCB A/D sampling time tADCS PCR11~ 000000000000B PCR0 ACS3~ ACS0 000000001111B 0000B A/D sampling time tADCS 000000001111B Start of A/D conversion Reset A/D converter 1: Define PB configuration 2: Select analog channel 000000000111B 0000B 0010B Power-on Reset A/D sampling time tADCS Reset A/D converter End of A/D conversion tADC A/D conversion time 1. PA1,5~7,PB1~5, PC0,7 setup as I/Os or pin-shared function 2. A/D converter is powered off to reduce power consumption don't care 0001B Start of A/D conversion 000000000000B Start of A/D conversion Reset A/D converter End of A/D conversion tADC A/D conversion time End of A/D conversion tADC A/D conversion time Note: A/D clock must be fSYS/2, fSYS/8 or fSYS/32 tADCS=4tAD tADC=16tAD Page 58 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B A/D Conversion Timing Page 59 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B 8.24 Low Voltage Reset/Detector – LVR/LVD The micro-controller provides a low voltage reset circuit in order to monitor the supply voltage of the device. This function can be enabled or disabled by configuration option. If the supply voltage of the device is within the range 0.9V~VLVR, the LVR will automatically reset the device internally. The LVR includes the following specifications: ‧ The low voltage (0.9V~VLVR) has to be maintained for more than tLVR. If the low voltage state does not exceed tLVR, the LVR will ignore it and do not perform a reset function. ‧ The LVR uses the “OR” functions with the external RESB signal to perform chip reset. The relationship between VDD and VLVR is shown below. VDD 5.5V VOPR 5.5V 2.2V VDD 5.5V VOPR 5.5V VLVR VLVR 2.1V 3.0V 2.2V 0.9V 0.9V Note: VOPR is the voltage range for proper chip operation at 4MHz system clock. V DD 5.5V LVR Detect Voltage VLVR 0.9V 0V Reset Signal Reset Normal Operation *1 Reset *2 Low voltage reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over tLVR, therefore after tLVR delay, the device enters the reset mode. Page 60 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B The micro-controller also provides a low voltage detect function. This internal function provides a means for the user to monitor when the power supply voltage falls below a certain fixed level as specified in the D.C. characteristics. LVD function can be enabled or disabled by configuration option. If the LVD configuration option is enabled, the user can use LVDC bit in system control register 0 to enable/disable the LVD circuit and read the LVD detector status from LVDO bit in system control register 0. The device also provides an interrupt for low voltage detection; please see the section of interrupt for detail. During HALT, both LVR and LVD are disabled. 8.25 Oscillator stop detection An oscillator stop detection function which monitor the oscillator and force the micro-controller into the reset state if the oscillator fails. The reset state is maintained until the oscillator is working again. The oscillator stop detection function can be enabled by setting the OSTPC bit in system control register 0. During HALT, oscillator stop detection function is disabled. 8.26 I2C Bus Serial Interface 2 2 I C Bus is implemented in the device. The I C Bus is bi-directional two-wire lines. The data line and clock line are implement in SDA pin and SCL pin. The SDA and SCL are NMOS open drain output pins. They must connect a pull-high resistor respectively. 2 Using the I C Bus, the device has two ways to transfer data. One is in slave transmit mode, the other is in slave receive mode. 2 There are four registers related to I C Bus: HADR, HCR, HSR, and HDR. The HADR register is the slave address setting of the 2 device, if the master sends the calling address which match, it means that this device is selected. The HCR is I C Bus control 2 2 register which defines the device enable or disable the I C Bus as a transmitter or as a receiver. The HSR is I C Bus status 2 register, it responds with the I C Bus status. The HDR is input/output data register; data to transmit or receive must be via the HDR register. 2 2 The I C Bus control register contains three bits. The HEN bit defines whether to enable or disable the I C Bus. If the data wants 2 2 transfer via I C Bus, this bit must be set. The HTX bit defines whether the I C Bus is in transmit or receive mode. If the device is as a transmitter, this bit must be set to “1”. The TXAK defines the transmission of acknowledge signal, when the device received 2 8-bit data, the device sends this bit to I C Bus at the 9th clock. If the receiver wants to continue to receive the next data, this bit must be reset to “0” before receiving data. 2 The I C Bus status register contains five bits. The HCF bit is reset to “0” when one data byte is being transferred. If one data 2 transfer is completed, this bit is set to “1”. The HASS bit is set “1” when the address is match, and the I C Bus interrupt request 2 flag is set to “1”. If the interrupt is enabled and the stack is not full, a subroutine call will occur. Writing data to the I C Bus control 2 register clears HAAS bit. If the address is not match, this bit is reset to “0”. The HBB bit is set to respond the I C Bus is busy. It 2 means that a START signal is detected. This bit is reset to “0” when the I C Bus is not busy. It means that a STOP signal is 2 detected and the I C Bus is free. The SRW bit defines the read/write command bit, if the calling address is match. When HAAS Page 61 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B is set to “1”, the device check SRW bit to determine whether the device is working in transmit or receive mode. When SRW bit is 2 2 set “1”, it means that the master wants to read data from I C Bus, the slave device must write data to I C Bus, so the slave 2 device is working in transmit mode. When SRW is reset to “0”, it means that the master wants to write data to I C Bus, the slave device must read data from the bus, so the slave device is working in receive mode. The RXAK bit is reset “0” indicates an acknowledge signal has been received. In the transmit mode, the transmitter checks RXAK bit to know the receiver which wants 2 to receive the next data byte, so the transmitter continue to write data to the I C Bus until the RXAK bit is set to “1” and the transmitter releases the SDA line, so that the master can send the STOP signal to release the bus. The HADR bit7 to bit1 define the device slave address. At the beginning of transfer, the master must select a device by sending 2 the address of the slave device. The bit 0 is unused and is not defined. If the I C Bus receives a start signal, all slave device notice the continuity of the 8-bit data. The front of 7 bits is slave address and the first bit is MSB. If the address is match, the 2 2 HAAS status bit is set and generates an I C Bus interrupt. In the ISR, the slave device must check the HAAS bit to know the I C Bus interrupt comes from the slave address that has match or completed one 8-bit data transfer. The last bit of the 8-bit data is read/write command bit, it responds in SRW bit. The slave will check the SRW bit to know if the master wants to transmit or receive data. The device check SRW bit to know it is as a transmitter or receiver. Bit7~Bit1 Slave Address Bit0 HADR Register Note: “-“means undefined 2 The HDR register is the I C Bus input/output data register. Before transmitting data, the HDR must be loaded with the data to be transmitted. Before receiving data, the device must dummy read data from HDR first. 2 2 At the beginning of the transfer of the I C Bus, the device must initial the bus. The following are the notes for initialing the I C Bus: 2 1: Write the I C Bus address register (HADR) to define its own slave address. 2 2 2: Set HEN bit of I C Bus control register (HCR) to enable the I C Bus. 2 3: Set EHI bit of the interrupt control register 1 (INTC1) to enable the I C Bus interrupt. Page 62 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B Label TXAK HTX HEN Bit No. Function 2~0 Unused bit, read as “0” Enable/disable transmit acknowledge 3 (0= acknowledge; 1= don’t acknowledge) Define the transmit/receive mode 4 (0= receive mode; 1= transmit) 6~5 Unused bit, read as “0” 2 Enable/disable I C Bus function 7 (0= disable; 1= enable) HCR Register Label Bit No. RXAK 0 HTO 1 SRW 2 HBB 4~3 5 HAAS 6 HCF 7 Function RXAK is cleared to “0” when the master receives an 8-bit data and acknowledge at the 9th clock. RXAK is set to “1” means not acknowledged. I2C time-out flag. (set by time-out and clear by software) 0: not occured. 1: occurred. 2 SRW is set to “1” when the master wants to read data from the I C Bus, so the slave must transmit 2 data to the master. SRW is cleared to “0” when the master wants to write data to the I C Bus, so the slave must receive data from the master. Unused bit, read as “0” 2 2 HBB is set to “1” when I C Bus is busy and HBB is cleared to “0” means that the I C Bus is not busy. 2 HAAS is set to “1” when the calling addressed is matched, and I C Bus interrupt will occur and HCF is set. HCF is clear to “0” when one data byte is being transferred. HCF is set to “1” indicating 8-bit data 2 communication has been finished, and I C Bus interrupt will occur. HSR register Start signal The START signal is generated only by the master device. The other device in the bus must detect the START signal to set the 2 I C Bus busy bit (HBB). The START signal is SDA line from high to low, when SCL is high. SCL SDA Start Bit Slave address The master must select a device for transferring the data by sending the slave device address after the START signal. All 2 2 devices in the I C Bus will receive the I C Bus slave address (7 bits) to compare with its own slave address (7 bits). If the slave address is matched, the slave device will generate an interrupt and save the following bit (8th bit) to SRW bit and sends an acknowledge bit (low level) to the 9th bit. The slave device also sets the status flag (HAAS), when the slave address is matched. 2 In interrupt subroutine, check HAAS bit to know whether the I C Bus interrupt comes from a slave address that is matched or a data byte transfer is completed. When the slave address is matched, the device must be in transmit mode or receive mode and write data to HDR or dummy read from HDR to release the SCL line. SRW bit 2 The SRW bit means that the master device wants to read from or write to the I C Bus. The slave device check this bit to Page 63 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B understand itself if it is a transmitter or a receiver. The SRW bit is set to “1” means that the master wants to read data from the 2 I C Bus, so the slave device must write data to a bus as a transmitter. The SRW is cleared to “0” means that the master wants to 2 2 write data to the I C Bus, so the slave device must read data from the I C Bus as a receiver. SCL SRW Start 1 SDA 0 1 1 0 1 0 ACK 1 0 Data ACK Stop SCL 1 0 0 1 0 1 0 0 SDA S = Start (1 bit) S A= S lave A ddress (7 bits) S R = S R W bit (1 bit) M = S lave device send aclcnow ledge bit (1 bit) D =D ata (8 bits) A = AC K (R X AK bit for transm itter; TX A K bit for receiver 1 bit) P = Stop (1bit) S SA SR M D A D A S SA SR M D A D A P 2 I C Communication Timing Diagram Acknowledge bit One of the slave device generates an acknowledge signal, when the slave address is matched. The master device can check this acknowledge bit to know if the slave device accepts the calling address. If no acknowledge bit, the master must send a 2 STOP bit and end the communication. When the bit 6 (HAAS) of I C Bus status register is high, it means the address is matched, so the slave must check SRW as a transmitter (set HTX) to “1” or as a receiver (clear HTX) to “0”. Data byte The data is 8 bits and is sent after the slave device has acknowledges the slave address. The first bit is MSB and the 8th bit is LSB. The receiver sends the acknowledge signal (“0”) and continues to receive the next one byte data. If the transmitter checks 2 and there’s no acknowledge signal, then it release the SDA line, and the master sends a STOP signal to release the I C Bus. The data is stored in the HDR register. The transmitter must write data to the HDR before transmit data and the receiver must read data from the HDR after receiving data. Page 64 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B SCL SDA Start bit Stop bit Data stable Data allow change Data Timing Diagram Receive acknowledge bit When the receiver wants to continue to receive the next data byte, it generates an acknowledge bit (TXAK) at the 9th clock. The 2 transmitter checks the acknowledge bit (RXAK) to continue to write data to the I C Bus or change to receive mode and dummy read the HDR register to release the SDA line and the master sends the STOP signal. SCL SDA Stop Bit Start Write Slave Address to HADR SET HEN Disable I2C Bus Interrupt=? Enable CLR EHI Poll HIF to decide when to go to I2C Bus ISR SET EHI Wait for Interrupt Goto Main Program Goto Main Program 2 I C Bus Initial Flow Chart Page 65 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK. HT45R15B Start No No HTX=1 ? Yes HAAS=1 ? Yes Yes No SRW=1 ? Read from HDR SET HTX CLR HTX CLR TXAK RETI Write to HDR Dummy Read From HDR RETI RETI Yes RXAK=1 ? No CLR HTX CLR TXAK Write to HDR Dummy Read from HDR RETI RETI 2 I C Bus Interrupt Service Program Flow Chart I2C time-out control The time-out is implemented as following illustration: Time-out counter starts counting on I2C bus “START” & “address match”, and clears & stops on I2C bus “STOP”. Once time-out counter overflow : (1) counter stops and the HTO ( I2C time-out flag ) is set for indication. (2) the overflow also causes an interrupt which use the I2C interrrupt vector. (3) I2C module is reset and registers (HADR, HCR, HSR, and HDR) becomes reset state, except for HTO=1. It has to be re-initialized. HTO flag can be cleared by software. There are 4 time-out periods for selection by configuration option: 128, 256, 512, 1024 (unit : WDT OSC clock ). Page 66 of 66 本資料為盛群半導體股份有限公司專有之財產，非經書面准許不可透露或使用本資料，亦不准複印、複製或轉變成任何其它形式使用。 The information contained herein is the exclusive property of HOLTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of HOLTEK.