Hynix HY5DU281622ETP-33 128m(8mx16) gddr sdram Datasheet

HY5DU281622ETP
128M(8Mx16) gDDR SDRAM
HY5DU281622ETP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Oct. 2005
1
1HY5DU281622ETP
Revision History
Revision No.
History
Draft Date
0.1
Defined target spec.
July 2003
0.2
Supports Lead free parts for each speed grade
Oct. 2003
0.3
166Mhz speed bin delete, AC parameter change (tRC_APCG at 200Mhz)
Jan. 2005
1.0
Added Sentence to relate Power Up Sequence
Oct. 2005
Rev. 1.0 / Oct. 2005
Remark
2
1HY5DU281622ETP
DESCRIPTION
The Hynix HY5DU281622ETP is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for
the point-to-point applications which require high densities and high bandwidth.
The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
rising and falling edges of the data strobe
•
2.8V +/- 0.1V VDD and VDDQ power supply
supports 400/375/350/333/300MHz
•
2.5V +/- 5% VDD and VDDQ power supply
supports 275/250/200/166MHz
•
All inputs and outputs are compatible with SSTL_2
interface
•
JEDEC Standard 400 mil x 875 mil 66 Pin TSOP II,
with 0.65mm pin pitch
•
Fully differential clock inputs (CK, /CK) operation
•
•
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
•
Write mask byte controls by DM (UDM,LDM)
•
Programmable /CAS Latency 5, 4 and 3 are supported
•
Programmable Burst Length 2, 4 and 8 with both
sequential and interleave mode
Double data rate interface
•
Internal 4 bank operation with single pulsed /RAS
•
Source synchronous - data transaction aligned to
bidirectional data strobe (UDQS,LDQS)
•
tRAS Lock-Out function are supported
•
Auto refresh and self refresh are supported
•
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
•
4096 refresh cycles / 32ms
•
Full strength, Half strength and Weak Impedance
driver options controlled by EMRS
•
Data(DQ) and Write masks(DM) latched on the both
ORDERING INFORMATION
Part No.
HY5DU281622ETP-25
HY5DU281622ETP-26
HY5DU281622ETP-28
HY5DU281622ETP-30
HY5DU281622ETP-33
HY5DU281622ETP-36
HY5DU281622ETP-4
HY5DU281622ETP-5
Power
Supply
VDD/VDDQ=2.8V
VDD/VDDQ=2.5V
Clock
Frequency
Max Data Rate
interface
400MHz
375MHz
350MHz
333MHz
300MHz
275MHz
250MHz
200MHz
800Mbps/pin
750Mbps/pin
700Mbps/pin
666Mbps/pin
600Mbps/pin
550Mbps/pin
500Mbps/pin
400Mbps/pin
SSTL_2
Package
400 x 875mil 2
66 Pin TSOP II
Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free material.
We'll add "P" character after "T" for Pb free product. For example, the part number of 300MHz Lead free
Product is HY5DU281622ETP-33.
Rev. 1.0 / Oct. 2005
3
1HY5DU281622ETP
PIN CONFIGURATION (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
400mil X 875mil
66pin TSOP -II
0.65mm pin pitch
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
ROW AND COLUMN ADDRESS TABLE
Rev. 1.0 / Oct. 2005
ITEMS
8Mx16
Organization
2M x 16 x 4banks
Row Address
A0 - A11
Column Address
A0-A8
Bank Address
BA0, BA1
Auto Precharge Flag
A10
Refresh
4K
4
1HY5DU281622ETP
PIN DESCRIPTION
PIN
TYPE
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry and exit. CKE is asynchronous for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and
CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during
SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd
is applied.
/CS
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied.
A0 ~ A11
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
UDM, LDM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ
and DQS loading. LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data
on DQ8-Q15
UDQS, LDQS
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. LDQS corresponds to the data on
DQ0-Q7; UDQS corresponds to the data on DQ8-Q15
DQ0 ~ DQ15
I/O
Data input / output pin : Data Bus
VDD/VSS
Supply
Power supply for internal circuits and input buffers.
VDDQ/VSSQ
Supply
Power supply for output buffers for noise immunity.
VREF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
Rev. 1.0 / Oct. 2005
DESCRIPTION
No connection.
5
1HY5DU281622ETP
FUNCTIONAL BLOCK DIAGRAM
4Banks x 2Mbit x 16 I/O Double Data Rate Synchronous DRAM
16
Input Buffer
Write Data Register
2-bit Prefetch Unit
32
CLK
Bank
Control
2Mx16/Bank0
2Mx16/Bank1
/CS
/RAS
Command
Decoder
2Mx16/Bank2
32
/CAS
16
Output Buffer
Sense AMP
CKE
2-bit Prefetch Unit
/CLK
DS
DQ[0:15]
2Mx16/Bank3
/WE
LDM
UDM
Mode
Register
Row
Decoder
Column Decoder
LDQS, UDQS
A0~A11
CLK_DLL
Address
Buffer
BA0, BA1
Column Address
Counter
LDQS
UDQS
CLK
/CLK
Data Strobe
Transmitter
Data Strobe
Receiver
DLL
Block
Mode
Register
Rev. 1.0 / Oct. 2005
6
1HY5DU281622ETP
SIMPLIFIED COMMAND TRUTH TABLE
A10/
AP
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
X
L
L
L
L
OP code
1,2
H
X
H
X
X
X
L
H
H
H
X
1
H
X
L
L
H
H
H
X
L
H
L
H
CA
H
X
L
H
L
L
CA
H
X
L
L
H
L
X
Read Burst Stop
H
X
L
H
H
L
X
1
Auto Refresh
H
H
L
L
L
H
X
1
Entry
H
L
L
L
L
H
Exit
L
H
H
X
X
X
L
H
H
H
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
1
H
X
X
X
1
L
V
V
V
Device Deselect
No Operation
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Self Refresh
Precharge Power
Down Mode
Active Power
Down Mode
Exit
L
H
Entry
H
L
Exit
L
H
X
ADDR
RA
BA
V
L
H
L
H
V
V
Note
1
1
1,3
1
1,4
H
X
1,5
L
V
1
1
X
1
1
X
X
1
1
1
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. UDM, LDM states are Don’t Care. Refer to below Write Mask Truth Table.(note 6)
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before
entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from
Prechagre command.
3. If a Read with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented
to activate bank until CK(n+BL/2+tRP).
4. If a Write with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented
to activate bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery
Time(tWR) is needed to guarantee that the last data have been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
6. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of
VIHmin ~ VILmax
Rev. 1.0 / Oct. 2005
7
1HY5DU281622ETP
WRITE MASK TRUTH TABLE
CKEn-1
CKEn
/CS, /RAS,
/CAS, /WE
DM
Data Write
H
X
X
L
X
1,2,3
Data-In Mask
H
X
X
H
X
1,2,3
Function
ADDR
A8/
AP
BA
Note
Note :
1. Write Mask command masks burst write data with reference to UDQS/LDQS and it is not related with read data.
2. LDM corresponds to the data on DQ0-Q7 and UDM corresponds to the data on DQ8-Q15
3. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of
VIHmin ~ VILmax
Rev. 1.0 / Oct. 2005
8
1HY5DU281622ETP
OPERATION COMMAND TRUTH TABLE - I
Current
State
IDLE
ROW
ACTIVE
READ
WRITE
/CS
/RAS
/CAS
/WE
Address
Command
Action
H
X
X
X
X
DSEL
NOP or power down3
L
H
H
H
X
NOP
NOP or power down3
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4
L
L
H
H
BA, RA
ACT
Row Activation
L
L
H
L
BA, AP
PRE/PALL
NOP
L
L
L
H
X
AREF/SREF
Auto Refresh or Self Refresh5
L
L
L
L
OPCODE
MRS
Mode Register Set
H
X
X
X
X
DSEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
Begin read : optional AP6
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
Begin write : optional AP6
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Precharge7
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
Terminate burst
L
H
L
H
BA, CA, AP
READ/READAP
Term burst, new read:optional AP8
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Term burst, precharge
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
Term burst, new read:optional AP8
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
Term burst, new write:optional AP
Rev. 1.0 / Oct. 2005
9
1HY5DU281622ETP
OPERATION COMMAND TRUTH TABLE - II
Current
State
WRITE
READ
WITH
AUTOPRECHARGE
WRITE
AUTOPRECHARGE
PRECHARGE
/CS
/RAS
/CAS
/WE
Address
Command
Action
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Term burst, precharge
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP-Enter IDLE after tRP
L
H
H
H
X
NOP
NOP-Enter IDLE after tRP
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
NOP-Enter IDLE after tRP
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
Rev. 1.0 / Oct. 2005
10
1HY5DU281622ETP
OPERATION COMMAND TRUTH TABLE - III
Current
State
/CS
/RAS
/CAS
/WE
Address
Command
Action
H
X
X
X
X
DSEL
NOP - Enter ROW ACT after tRCD
L
H
H
H
X
NOP
NOP - Enter ROW ACT after tRCD
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,9,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter ROW ACT after tWR
L
H
H
H
X
NOP
NOP - Enter ROW ACT after tWR
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter precharge after tDPL
L
H
H
H
X
NOP
NOP - Enter precharge after tDPL
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,8,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter IDLE after tRC
L
H
H
H
X
NOP
NOP - Enter IDLE after tRC
L
H
H
L
X
BST
ILLEGAL11
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL11
ROW
ACTIVATING
WRITE
RECOVERING
WRITE
RECOVERING
WITH
AUTOPRECHARGE
REFRESHING
Rev. 1.0 / Oct. 2005
11
1HY5DU281622ETP
OPERATION COMMAND TRUTH TABLE - IV
Current
State
WRITE
MODE
REGISTER
ACCESSING
/CS
/RAS
/CAS
/WE
Address
Command
Action
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL11
L
L
H
H
BA, RA
ACT
ILLEGAL11
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter IDLE after tMRD
L
H
H
H
X
NOP
NOP - Enter IDLE after tMRD
L
H
H
L
X
BST
ILLEGAL11
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL11
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL11
L
L
H
H
BA, RA
ACT
ILLEGAL11
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
Note :
1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input, BA - Bank Address, AP - AutoPrecharge Address,
CA - Column Address, RA - Row Address, NOP - NO Operation.(see note 12)
2. All entries assume that CKE was active(high level) during the preceding clock cycle.
3. If both banks are idle and CKE is inactive(low level), then in power down mode.
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of that
bank.
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.
6. Illegal if tRCD is not met.
7. Illegal if tRAS is not met.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Illegal if tRRD is not met.
10. Illegal for single bank, but legal for other banks in multi-bank devices.
11. Illegal for all banks.
12. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of
VIHmin ~ VILmax
Rev. 1.0 / Oct. 2005
12
1HY5DU281622ETP
CKE FUNCTION TRUTH TABLE
Current
State
SELF
REFRESH1
POWER
DOWN2
ALL BANKS
IDLE4
ANY STATE
OTHER
THAN
ABOVE
CKEn1
CKEn
/CS
/RAS
/CAS
/WE
/ADD
Action
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit self refresh, enter idle after tSREX
L
H
L
H
H
H
X
Exit self refresh, enter idle after tSREX
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue self refresh
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit power down, enter idle
L
H
L
H
H
H
X
Exit power down, enter idle
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue power down mode
H
H
X
X
X
X
X
See operation command truth table
H
L
L
L
L
H
X
Enter self refresh
H
L
H
X
X
X
X
Exit power down
H
L
L
H
H
H
X
Exit power down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
H
X
X
ILLEGAL
H
L
L
L
L
L
X
ILLEGAL
L
L
X
X
X
X
X
NOP
H
H
X
X
X
X
X
See operation command truth table
H
L
X
X
X
X
X
ILLEGAL5
L
H
X
X
X
X
X
INVALID
L
L
X
X
X
X
X
INVALID
Note :
When CKE=L, all DQ and UDQS/LDQS should be in Hi-Z state.
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All commands can be stored after 2 clocks from low to high transition of CKE.
3. Illegal, if CK is suspended or stopped during the power down mode.
4. Self refresh can be asserted only from the all banks idle state.
5. Disabling CK may cause malfunction of any banks which are in active state.
Rev. 1.0 / Oct. 2005
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1HY5DU281622ETP
SIMPLIFIED STATE DIAGRAM
MRS
MODE
REGISTER
SET
SREF
SELF
REFRESH
IDLE
SREX
PDEN
PDEX
AREF
ACT
POWER
DOWN
POWER
DOWN
AUTO
REFRESH
PDEN
BST
PDEX
BANK
ACTIVE
READ
WRITE
READ
WRITE
WRITEAP
WRITE
WITH
AUTOPRECHARGE
PRE(PALL)
READAP
READ
READAP
WITH
AUTOPRECHARGE WRITEAP
READ
WRITE
PRE(PALL)
PRE(PALL)
PRECHARGE
POWER-UP
Command Input
Automatic Sequence
POWER APPLIED
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1HY5DU281622ETP
POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those
specified may result in undefined operation. Power must first be applied to VDD and VDDQ simultaneously, and then to
VREF (and to the system VTT).
VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device.
VREF can be applied any time after VDDQ but is expected to be nominally coincident with VTT. Except for CKE, inputs
are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level
after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ
and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read
access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a
200µs delay prior to applying an executable command.
Once the 200µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED
MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE
REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Register set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command
for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting
the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
1.
Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVCMOS low state. (All the other input pins may be undefined.)
No power sequencing is specified during power up or power down given the following cirteria :
• VDD and VDDQ are driven from a single power converter output.
• VTT is limited to 1.35V.
• VREF tracks VDDQ/2.
• If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must be adhered to during power up :
Voltage description
Sequencing
Voltage relationship to avoid latch-up
VDDQ
After or with VDD
< VDD + 0.3V
VTT
After or with VDDQ
< VDDQ + 0.3V
VREF
After or with VDDQ
< VDDQ + 0.3V
2.
Start clock and maintain stable clock for a minimum of 200µsec.
3.
After stable power and clock, apply NOP or DESELECT conditionS and take CKE high.
4.
Following the NOP command, a PRECHARGE ALL command should be applied
5.
Issue Extended Mode Register Set (EMRS) to enable DLL.
6.
Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200
cycles(tXSRD) of clock are required for locking DLL)
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1HY5DU281622ETP
7.
Issue Precharge commands for all banks of the device.
8.
Issue 2 or more Auto Refresh commands.
9.
Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
Power-Up Sequence
VDD
VDDQ
tVTD
VTT
VREF
/CLK
CLK
tIS tIH
CKE
LVCMOS Low Level
CMD
NOP
PRE
EMRS
MRS
ADDR
CODE
A10
BA0, BA1
NOP
PRE
MRS
ACT
RD
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
Non-Read
Command
READ
AREF
DM
DQS
DQ'S
T=200usec
tRP
tMRD
tMRD
tRP
tRFC
tMRD
tXSRD*
Power UP
VDD and CK stable
Precharge All
EMRS Set
MRS Set
Reset DLL
(with A8=H)
Precharge All
2 or more
Auto Refresh
MRS Set
(with A8=L)
* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command
Note)
1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device
latch-up. VDDQ, VTT and VREF must be equal to or less than VDD+0.3V. Alternatively, VTT may be 1.35V
maximum during power up, even if VDD/VDDQ are 0V. Once initialized, including self refresh mode, VREF must
always be powered within specified range.
2. The Power Voltage ramp time between initial VDD and VDDmin must be no less than 3ms.
3. The Initial VDD must be maintained under 100mV.
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1HY5DU281622ETP
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low
signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE
must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write
the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.
BA1
BA0
0
0
A11
A10
RFU*
A9
A8
A7
DR
TM
A6
A5
A4
CAS Latency
BA0
MRS Type
A7
Test Mode
0
MRS
0
Normal
1
EMRS
1
Vendor
test mode
A3
A2
BT
A1
A0
Burst Length
Burst Length
A2
A1
A8
DLL Reset
0
No
0
0
1
Yes
0
A0
Sequential
Interleave
0
Reserved
Reserved
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
5
A3
Burst Type
1
1
0
Reserved
0
Sequential
1
1
1
Reserved
1
Interleave
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.
And, if MRS/EMRS are programmed with ‘Reserved’ code, it could be the cause of mal-function.
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1HY5DU281622ETP
BURST DEFINITION
Burst Length
Starting Address (A2,A1,A0)
Sequential
Interleave
XX0
0, 1
0, 1
XX1
1, 0
1, 0
X00
0, 1, 2, 3
0, 1, 2, 3
X01
1, 2, 3, 0
1, 0, 3, 2
X10
2, 3, 0, 1
2, 3, 0, 1
X11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
0, 1, 2, 3, 4, 5, 6, 7
7, 6, 5, 4, 3, 2, 1, 0
2
4
8
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst
length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is
set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a
given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to both Read and Write bursts.
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Burst Definitionon Table
CAS LATENCY
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the
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1HY5DU281622ETP
availability of the first burst of output data. The latency can be programmed 3 or 4 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident
with clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any
time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally
applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
This device supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-topoint environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2,
Class II, and Matched impedance driver, about 30% of Full drive strength.
Rev. 1.0 / Oct. 2005
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1HY5DU281622ETP
EXTENDED MODE REGISTER SET (EMRS)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits
shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0)
and will retain the stored information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subsequent operation. Violating either of these requirements will
result in unspecified operation.
BA1
BA0
0
1
A11
A10
A9
RFU*
BA0
MRS Type
0
MRS
1
EMRS
A8
A7
A6
A5
A4
DS
A3
RFU*
A2
A1
A0
DS
DLL
A0
DLL enable
0
Enable
1
Diable
A6
A1
Output Driver Impedance Control
0
0
Full
0
1
Half (60%)
1
0
Reserved
1
1
Weak (33%)
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.
Rev. 1.0 / Oct. 2005
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1HY5DU281622ETP
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
oC
Storage Temperature
TSTG
-55 ~ 125
o
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
C
VDD
-0.5 ~ 3.6
V
VDDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
IOS
50
mA
Power Dissipation
PD
2
W
TSOLDER
260 ⋅ 10
Voltage on VDDQ relative to VSS
Soldering Temperature ⋅ Time
oC
⋅ sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
Parameter
Power Supply Voltage
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Symbol
Min
Typ
Max
Unit
Note
VDD
2.375
2.5
2.625
V
1,4
VDDQ
2.375
2.5
2.625
V
1,4
VDD
2.7
2.8
2.9
V
1,5
1,5
VDDQ
2.7
2.8
2.9
V
Input High Voltage
VIH
VREF + 0.15
-
VDDQ + 0.3
V
Input Low Voltage
VIL
-0.3
-
VREF - 0.15
V
Termination Voltage
VTT
VREF - 0.04
VREF
VREF + 0.04
V
3
Reference Voltage
VREF
0.49*VDDQ
0.5*VDDQ
0.51*VDDQ
V
2
Note : 1. VDDQ must not exceed the level of VDD.
2. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak to peak noise on VREF may not exceed ± 2% of the DC value.
3. VTT is expected to be set equal to VREF, and Vtt of the transmitting device must track VREF of the receiving device.
4. Supports 275/ 250/ 200/166Mhz
5. Supports 400/375/350/333/300Mhz
DC CHARACTERISTICS I
Parameter
Input Leakage Current
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Symbol
Min
Max
Unit
Note
ILI
-5
5
uA
1
Output Leakage Current
ILO
-5
5
uA
2
Output High Voltage
VOH
VTT + 0.76
-
V
IOH = -15.2mA,2
Output Low Voltage
VOL
-
VTT - 0.76
V
IOL = +15.2mA,2
Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V.
2. DOUT is disabled, VOUT=0 to 2.625V, It means, output logic high voltage and low voltage is depend on output channel conditions.
Rev. 1.0 / Oct. 2005
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1HY5DU281622ETP
DC CHARACTERISTICS II
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Speed
Parameter
Symbol
Test Condition
Unit
Note
190
mA
1
1
25
26
28
30
33
230
220
210
200
Operating Current
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min);
DQ,DM and DQS inputs changing
twice per clock cycle; address and
control inputs changing once per
clock cycle
Operating Current
IDD1
Burst length=4, One bank active
tRC ≥ tRC(min), IOL=0mA
230
220
210
200
190
mA
Precharge Standby
Current in Power Down
Mode
IDD2P
CKE ≤ VIL(max), tCK=min
40
40
40
40
40
mA
Precharge Standby
Current in Non Power
Down Mode
IDD2N
CKE ≥ VIH(min), /CS ≥ VIH(min),
tCK = min, Input signals are
changed one time during 2clks
150
140
130
120
110
mA
Active Standby Current in Power Down
Mode
IDD3P
CKE ≤ VIL(max), tCK=min
40
40
40
40
40
mA
Active Standby Current in Non Power
Down Mode
IDD3N
CKE ≥ VIH(min), /CS ≥ VIH(min),
tCK=min, Input signals are
changed one time during 2clks
190
180
170
160
150
mA
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
380
360
340
320
300
mA
1
Auto Refresh Current
IDD5
tRC ≥ tRFC(min),
All banks active
380
360
340
320
300
mA
1,2
Self Refresh Current
IDD6
CKE ≤ 0.2V
4
4
4
4
4
mA
Operating Current Four Bank Operation
IDD7
Four bank interleaving with BL=4,
Refer to the following page for
detailed test condition
530
510
490
470
450
mA
Note :
1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
Rev. 1.0 / Oct. 2005
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1HY5DU281622ETP
DC CHARACTERISTICS II
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Speed
Parameter
Symbol
Test Condition
Unit
Note
160
mA
1
1
36
4
5
180
170
Operating Current
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM
and DQS inputs changing twice per clock
cycle; address and control inputs changing once per clock cycle
Operating Current
IDD1
Burst length=2, One bank active
tRC ≥ tRC(min), IOL=0mA
180
170
160
mA
Precharge Standby Current in Power Down
Mode
IDD2P
CKE ≤ VIL(max), tCK=min
40
40
40
mA
Precharge Standby Current in Non Power Down
Mode
IDD2N
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK =
min, Input signals are changed one time
during 2clks
100
90
80
mA
Active Standby Current
in Power Down Mode
IDD3P
CKE ≤ VIL(max), tCK=min
40
40
40
mA
Active Standby Current
in Non Power Down
Mode
IDD3N
CKE ≥ VIH(min), /CS ≥ VIH(min),
tCK=min, Input signals are changed one
time during 2clks
140
130
120
mA
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
280
260
240
mA
1
Auto Refresh Current
IDD5
tRC ≥ tRFC(min),
All banks active
280
260
240
mA
1,2
Self Refresh Current
IDD6
CKE ≤ 0.2V
4
4
4
mA
Operating Current - Four
Bank Operation
IDD7
Four bank interleaving with BL=4, Refer
to the following page for detailed test
condition
430
410
390
mA
Note :
1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
Rev. 1.0 / Oct. 2005
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1HY5DU281622ETP
AC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.45
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
Input Differential Voltage, CK and /CK inputs
VID(AC)
Input Crossing Point Voltage, CK and /CK inputs
VIX(AC)
Unit
Note
V
VREF - 0.45
V
0.7
VDDQ + 0.6
V
1
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
VDDQ x 0.5
V
Termination Voltage
VDDQ x 0.5
V
AC Input High Level Voltage (VIH, min)
VREF + 0.45
V
AC Input Low Level Voltage (VIL, max)
VREF - 0.45
V
Input Timing Measurement Reference Level Voltage
VREF
V
Output Timing Measurement Reference Level Voltage
VTT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (RT)
50
Ω
Series Resistor (RS)
25
Ω
Output Load Capacitance for Access Time Measurement (CL)
30
pF
Rev. 1.0 / Oct. 2005
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1HY5DU281622ETP
AC Overshoot/Undershoot specifications for Address and Command pins
Parameter
200MHz Specifications
Maximum peak amplitude allowwed for overshoot
1.5 V
Maximum peak amplitude allowwed for undershoot
1.5 V
The area between the overshoot signal and VDD must be less than or equal to(See below Fig)
4.5 V-nS
The area between the overshoot signal and GND must be less than or equal to(See below Fig)
4.5 V-nS
Max. amplitude=1.5V
+5
+4
+3
VDD
Volts +2
(V) +1
Ground
0
-1
-2
Max. area=4.5V-ns
-3
0
1
2
3
4
5
6
AC Overshoot/Undershoot
specifications
for
Data,
Strobe
and
Mask Pins
Time(ns)
Parameter
200MHz Specifications
Maximum peak amplitude allowwed for overshoot
1.2 V
Maximum peak amplitude allowwed for undershoot
1.2 V
The area between the overshoot signal and VDD must be less than or equal to(See below Fig)
2.4 V-nS
The area between the overshoot signal and GND must be less than or equal to(See below Fig)
2.4 V-nS
Max. amplitude=1.2V
+5
+4
+3
VDD
Volts +2
(V) +1
Ground
0
-1
-2
Max. area=2.4V-ns
-3
0
1
2
3
4
5
6
Time(ns)
Rev. 1.0 / Oct. 2005
25
1HY5DU281622ETP
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
Symbol
25
26
28
Unit
Min
Max
Min
Max
Min
Max
tRC
22
-
21
-
20
-
tRC_APCG
24
-
23
-
22
-
Auto Refresh Row Cycle Time
tRFC
26
-
25
-
24
-
CK
Row Active Time
tRAS
16
100K
15
100K
14
100K
CK
Row Address to Column Address Delay for Read
tRCDRD
6
-
6
-
6
-
CK
Row Address to Column Address Delay for Write
tRCDWR
4
-
4
-
4
-
CK
Row Active to Row Active Delay
tRRD
4
-
4
-
4
-
CK
Column Address to Column Address Delay
tCCD
2
-
2
-
2
-
CK
Row Precharge Time
tRP
6
-
6
-
6
-
CK
Write Recovery Time
tWR
4
-
4
-
4
-
CK
Last Data-In to Read Command
tDRL
2
-
2
-
2
-
CK
Auto Precharge Write Recovery + Precharge Time
tDAL
10
-
10
-
10
-
CK
2.5
6
2.6
6
-
-
-
-
-
-
2.8
6
Row Cycle Time(Manual Precharge)
Row Cycle Time(Auto Precharge)
System Clock Cycle Time
CL=5
CL=4
tCK
Note
CK
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.55
0.55
-0.6
0.6
-0.6
0.6
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.55
0.55
-0.6
0.6
-0.6
0.6
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.35
-
0.35
-
0.35
ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns
1,6
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns
1,5
tQHS
-
0.35
-
0.35
-
0.35
ns
6
Input Setup Time
tIS
0.75
-
0.75
-
0.75
-
ns
2
Input Hold Time
tIH
0.75
-
0.75
-
0.75
-
ns
2
Write DQS High Level Width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Low Level Width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
CK
Clock to First Rising edge of DQS-In
tDQSS
0.85
1.15
0.85
1.15
0.85
1.15
CK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.35
-
0.35
-
0.35
-
ns
3
Data-In Hold Time to DQS-In (DQ & DM)
tDH
0.35
-
0.35
-
0.35
-
ns
3
Data Hold Skew Factor
Rev. 1.0 / Oct. 2005
26
1HY5DU281622ETP
Parameter
Symbol
25
26
28
Unit
Min
Max
Min
Max
Min
Max
DQS falling edge to CK setup time
tDSS
3.0
-
3.0
-
3.0
-
CK
DQS falling edge hold time from CK
tDSH
3.0
-
3.0
-
3.0
-
CK
Write DQS Preamble Setup Time
tWPRES
0
-
0
-
0
-
ns
Write DQS Preamble Hold Time
tWPREH
0.35
-
0.35
-
0.35
-
CK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
10
-
10
-
10
-
ns
Exit Self Refresh to Any Execute Command
tXSC
200
-
200
-
200
-
CK
Power Down Exit Time
tPDEX
2tCK
+ tIS
-
2tCK
+ tIS
-
2tCK
+ tIS
-
CK
Average Periodic Refresh Interval
tREFI
-
7.8
-
7.8
-
7.8
us
Note
4
Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
Data latched at both rising and falling edges of Data Strobes(UDQS,LDQS) : DQ, LDM,UDM.
4.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
5.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
6.
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).
tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and
output pattern effects, and p-channel to n-channel variation of the output drivers.
7.
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
Rev. 1.0 / Oct. 2005
27
1HY5DU281622ETP
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
Symbol
30
33
36
Unit
Note
Min
Max
Min
Max
Min
Max
tRC
19
-
18
-
16
-
tRC_APCG
21
-
20
-
18
-
Auto Refresh Row Cycle Time
tRFC
23
-
22
-
20
-
CK
Row Active Time
tRAS
13
100K
12
100K
11
100K
CK
Row Address to Column Address Delay for Read
tRCDRD
6
-
6
-
5
-
CK
Row Address to Column Address Delay for Write
tRCDWR
4
-
4
-
3
-
CK
Row Active to Row Active Delay
tRRD
4
-
4
-
3
-
CK
Column Address to Column Address Delay
tCCD
2
-
1
-
1
-
CK
Row Precharge Time
tRP
6
-
6
-
5
-
CK
Write Recovery Time
tWR
4
-
4
-
3
-
CK
Last Data-In to Read Command
tDRL
2
-
2
-
2
-
CK
Auto Precharge Write Recovery + Precharge Time
tDAL
10
-
10
-
8
-
CK
System Clock Cycle Time
tCK
3
6
3.3
6
3.6
10
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.6
0.6
-0.6
0.6
-0.6
0.6
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.6
0.6
-0.6
0.6
-0.6
0.6
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.35
-
0.35
-
0.35
ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns
1,6
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns
1,5
tQHS
-
0.35
-
0.35
-
0.4
ns
6
Input Setup Time
tIS
0.75
-
0.75
-
0.75
-
ns
2
Input Hold Time
tIH
0.75
-
0.75
-
0.75
-
ns
2
Write DQS High Level Width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Low Level Width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
CK
Clock to First Rising edge of DQS-In
tDQSS
0.85
1.15
0.85
1.15
0.85
1.15
CK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.35
-
0.35
-
0.4
-
ns
3
Data-In Hold Time to DQS-In (DQ & DM)
tDH
0.35
-
0.35
-
0.4
-
ns
3
DQS falling edge to CK setup time
tDSS
0.3
-
0.3
-
0.3
-
CK
DQS falling edge hold time from CK
tDSH
0.3
-
0.3
-
0.3
-
CK
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
CK
Row Cycle Time(Manual Precharge)
Row Cycle Time(Auto Precharge)
CL=4
Data Hold Skew Factor
Rev. 1.0 / Oct. 2005
CK
28
1HY5DU281622ETP
Parameter
Symbol
30
33
36
Unit
Min
Max
Min
Max
Min
Max
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
tWPRES
0
-
0
-
0
-
ns
Write DQS Preamble Hold Time
tWPREH
0.35
-
0.35
-
0.35
-
CK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
10
-
10
-
10
-
ns
Exit Self Refresh to Any Execute Command
tXSC
200
-
200
-
200
-
CK
Power Down Exit Time
tPDEX
2tCK
+ tIS
-
2tCK
+ tIS
-
1tCK
+ tIS
-
CK
Average Periodic Refresh Interval
tREFI
-
7.8
-
7.8
-
7.8
us
Read DQS Postamble Time
Note
4
Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
Data latched at both rising and falling edges of Data Strobes(UDQS,LDQS) : DQ, LDM,UDM.
4.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
5.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
6.
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).
tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and
output pattern effects, and p-channel to n-channel variation of the output drivers.
7.
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
Rev. 1.0 / Oct. 2005
29
1HY5DU281622ETP
AC CHARACTERISTICS - I
(Continued)
Parameter
Symbol
4
5
Unit
Min
Max
Min
Max
tRC
15
-
12
-
tRC_APCG
17
-
13
-
Auto Refresh Row Cycle Time
tRFC
18
-
14
-
CK
Row Active Time
tRAS
10
100K
8
100K
CK
Row Address to Column Address Delay for Read
tRCDRD
5
-
4
-
CK
Row Address to Column Address Delay
for Write
tRCDWR
3
-
2
-
CK
Row Active to Row Active Delay
tRRD
3
-
2
-
CK
Column Address to Column Address Delay
tCCD
1
-
1
-
CK
Row Precharge Time
tRP
5
-
4
-
CK
Write Recovery Time
tWR
3
-
3
-
CK
Last Data-In to Read Command
tDRL
2
-
2
-
CK
Auto Precharge Write Recovery +
Precharge Time
tDAL
8
-
7
-
CK
4
10
-
-
-
-
5
10
Row Cycle Time(Manual Precharge)
Row Cycle Time(Auto Precharge)
System Clock Cycle Time
CL=4
CL=3
tCK
Note
CK
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.6
0.6
-0.65
0.65
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.6
0.6
-0.55
0.55
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.4
-
0.4
ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns
1,6
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
ns
1,5
tQHS
-
0.4
-
0.45
ns
6
Input Setup Time
tIS
0.75
-
0.6
-
ns
2
Input Hold Time
tIH
0.75
-
0.6
-
ns
2
Write DQS High Level Width
tDQSH
0.4
0.6
0.4
0.6
CK
Write DQS Low Level Width
tDQSL
0.4
0.6
0.4
0.6
CK
Clock to First Rising edge of DQS-In
tDQSS
0.85
1.15
0.72
1.28
CK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.4
-
0.4
-
ns
3
Data-In Hold Time to DQS-In (DQ & DM)
tDH
0.4
-
0.4
-
ns
3
DQS falling edge to CK setup time
tDSS
0.3
-
0.3
-
CK
Data Hold Skew Factor
Rev. 1.0 / Oct. 2005
30
1HY5DU281622ETP
Parameter
Symbol
4
5
Unit
Min
Max
Min
Max
DQS falling edge hold time from CK
tDSH
0.3
-
0.3
-
CK
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
CK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
tWPRES
0
-
0
-
ns
Write DQS Preamble Hold Time
tWPREH
0.35
-
0.25
-
CK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
10
-
10
-
ns
Exit Self Refresh to Any Execute Command
tXSC
200
-
200
-
CK
Power Down Exit Time
tPDEX
1tCK
+ tIS
-
1tCK
+ tIS
-
CK
Average Periodic Refresh Interval
tREFI
-
7.8
-
7.8
us
Note
4
Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
Data latched at both rising and falling edges of Data Strobes(UDQS,LDQS) : DQ, UDM,LDM.
4.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
5.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
6.
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).
tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and
output pattern effects, and p-channel to n-channel variation of the output drivers.
7.
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
Rev. 1.0 / Oct. 2005
31
1HY5DU281622ETP
AC CHARACTERISTICS - II
Frequency
CL
tRC
tRC_APCG
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tDAL
Unit
400MHz (2.5ns)
5
22
24
26
16
6
4
6
10
tCK
375MHz (2.6ns)
5
21
23
25
15
6
4
6
10
tCK
350MHz (2.8ns)
4
20
22
24
14
6
4
6
10
tCK
333MHz (3.0ns)
4
19
21
23
13
6
4
6
10
tCK
300MHz (3.3ns)
4
18
20
22
12
6
4
6
10
tCK
275MHz (3.6ns)
4
16
18
20
11
5
3
5
8
tCK
250MHz (4.0ns)
4
15
17
18
10
5
3
5
8
tCK
200MHz (5.0ns)
3
12
13
14
8
4
2
4
7
tCK
Rev. 1.0 / Oct. 2005
32
1HY5DU281622ETP
CAPACITANCE (TA=25oC, f=1MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Clock Capacitance
CK, /CK
CCK
2
3
pF
Input Capacitance
All other input-only pins
CIN
2
3
pF
Input / Output Capacitance
DQ, DQS, DM
CIO
4
5
pF
Note :
1. VDD = min. to max., VDDQ = 2.375V to 2.625V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
V TT
R T =50Ω
Output
Zo=50Ω
V REF
C L=30pF
Rev. 1.0 / Oct. 2005
33
1HY5DU281622ETP
PACKAGE INFORMATION
400mil 66pin Thin Small Outline Package
Unit : mm(Inch)
11.94 (0.470)
11.79 (0.462)
10.26 (0.404)
10.05 (0.396)
BASE PLANE
22.33 (0.879)
22.12 (0.871)
0.65 (0.0256) BSC
1.194 (0.0470)
0.991 (0.0390)
Rev. 1.0 / Oct. 2005
0.35 (0.0138)
0.25 (0.0098)
0 ~ 5 Deg.
SEATING PLANE
0.15 (0.0059)
0.05 (0.0020)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
34
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