18-Bit, 1 MSPS PulSAR 7 mW ADC in MSOP/LFCSP AD7982 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS 2.5V TO 5V 2.5V IN+ REF VDD VIO SDI AD7982 ±10V, ±5V, .. IN– ADA4940-1/ ADA4941-1 SCK SDO GND CNV 1.8V TO 5V 3- OR 4-WIRE INTERFACE (SPI, CS DAISY CHAIN) 06513-001 18-bit resolution with no missing codes Throughput: 1 MSPS Low power dissipation 4 mW at 1 MSPS (VDD only) 7 mW at 1 MSPS (total) 70 μW at 10 kSPS INL: ±1 LSB typical, ±2 LSB maximum Dynamic range: 99 dB typical True differential analog input range: ±VREF 0 V to VREF with VREF between 2.5 V to 5.0 V Allows use of any input range Easy to drive with the ADA4941-1 or ADA4940-1 No pipeline delay Single-supply 2.5 V operation with 1.8 V, 2.5 V, 3 V, and 5 V logic interface Proprietary serial interface SPI-/QSPI™/ MICROWIRE™-/ DSP-compatible1 Ability to daisy-chain multiple ADCs and busy indicator 10-Lead MSOP and 3 mm × 3 mm 10-Lead LFCSP Figure 1. GENERAL DESCRIPTION The AD7982 is an 18-bit, successive approximation, analog-todigital converter (ADC) that operates from a single power supply, VDD. The AD7982 contains a low power, high speed, 18-bit sampling ADC and a versatile serial interface port. On the CNV rising edge, the AD7982 samples the voltage difference between the IN+ and IN− pins. The voltages on these pins usually swing in opposite phases between 0 V and VREF. The reference voltage, VREF, is applied externally and can be set independent of the supply voltage, VDD. Its power scales linearly with throughput. The serial peripheral interface (SPI)-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provides an optional busy indicator. The AD7982 is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. Battery-powered equipment Data acquisition systems Medical instruments Seismic data acquisition systems The AD7982 is available in a 10-lead MSOP or a 10-lead LFCSP with operation specified from −40°C to +85°C. Table 1. MSOP and LFCSP 14-/16-/18-Bit PulSAR® ADCs Bits 181 100 kSPS AD7989-1 250 kSPS AD7691 161 AD7684 AD7687 162 AD7680 AD7683 AD7988-1 AD7940 AD7685 AD7694 400 kSPS to 500 kSPS AD7690 AD7989-5 AD7688 AD7693 AD7916 AD7686 AD7988-5 AD7942 AD7946 142 1 2 1 ≥1000 kSPS AD7982 AD7984 AD7915 AD7980 AD7983 True differential. Pseudo differential. Protected by U.S. Patent 6,703,961. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2007–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7982* PRODUCT PAGE QUICK LINKS Last Content Update: 04/14/2017 COMPARABLE PARTS REFERENCE MATERIALS View a parametric search of comparable parts. Product Selection Guide EVALUATION KITS Technical Articles • AD7982 Evaluation kit • Exploring Different SAR ADC Analog Input Architectures • Precision ADC PMOD Compatible Boards • Low Power Precision Data Acquisition Signal Chain for Space Constrained Applications DOCUMENTATION • MS-1779: Nine Often Overlooked ADC Specifications Application Notes • MS-2210: Designing Power Supplies for High Speed ADC • AN-742: Frequency Domain Response of SwitchedCapacitor ADCs Tutorials • SAR ADC & Driver Quick-Match Guide • AN-931: Understanding PulSAR ADC Support Circuitry • AN-932: Power Supply Sequencing Data Sheet • MT-001: Taking the Mystery out of the Infamous Formula, "SNR=6.02N + 1.76dB", and Why You Should Care • MT-031: Grounding Data Converters and Solving the Mystery of "AGND" and "DGND" • AD7982: 18-Bit, 1 MSPS PulSAR 7 mW ADC in MSOP/LFCSP Data Sheet • MT-074: Differential Drivers for Precision ADCs Technical Books DESIGN RESOURCES • The Data Conversion Handbook, 2005 • AD7982 Material Declaration User Guides • PCN-PDN Information • UG-340: Evaluation Board for the 10-Lead Family 14-/16-/ 18-Bit PulSAR ADCs • Quality And Reliability • UG-682: 6-Lead SOT-23 ADC Driver for the 8-/10-Lead Family of 14-/16-/18-Bit PulSAR ADC Evaluation Boards SOFTWARE AND SYSTEMS REQUIREMENTS • AD7982 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design • BeMicro FPGA Project for AD7982 with Nios driver TOOLS AND SIMULATIONS • Symbols and Footprints DISCUSSIONS View all AD7982 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT • AD7982 IBIS Models Submit a technical question or find your regional support number. REFERENCE DESIGNS DOCUMENT FEEDBACK • CN0032 Submit feedback for this data sheet. • CN0180 • CN0237 • CN0345 This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified. AD7982 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 15 Applications ....................................................................................... 1 Single-Ended to Differential Driver......................................... 16 Functional Block Diagram .............................................................. 1 Voltage Reference Input ............................................................ 16 General Description ......................................................................... 1 Power Supply............................................................................... 16 Revision History ............................................................................... 2 Digital Interface .......................................................................... 17 Specifications..................................................................................... 3 CS Mode, 3-Wire Without Busy Indicator ............................. 18 Timing Specifications .................................................................. 5 CS Mode, 3-Wire with Busy Indicator .................................... 19 Absolute Maximum Ratings............................................................ 7 CS Mode, 4-Wire Without Busy Indicator ............................. 20 ESD Caution .................................................................................. 7 CS Mode, 4-Wire with Busy Indicator .................................... 21 Pin Configurations and Function Descriptions ........................... 8 Chain Mode Without Busy Indicator ...................................... 22 Typical Performance Characteristics ............................................. 9 Chain Mode with Busy Indicator ............................................. 23 Terminology .................................................................................... 12 Applications Information .............................................................. 24 Theory of Operation ...................................................................... 13 Layout .......................................................................................... 24 Circuit Information .................................................................... 13 Evaluating the Performance of the AD7982............................ 24 Converter Operation .................................................................. 13 Outline Dimensions ....................................................................... 25 Typical Connection Diagram ................................................... 14 Ordering Guide .......................................................................... 25 Analog Inputs .............................................................................. 15 REVISION HISTORY 1/2017—Rev. C to Rev. D Deleted QFN .................................................................. Throughout Changes to Features Section, Figure 1, and Table 1 ..................... 1 Changed to VIO = 2.3 V to 5.5 V to VIO = 1.71 V to 5.5 V ....... 3 Changes to Table 2 ............................................................................ 3 Deleted VIO Range Parameter, Table 3 ......................................... 4 Changed to VIO = 2.3 V to 5.5 V to VIO = 1.71 V to 5.5 V ....... 4 Changes to VIO Parameter, Table 3 ............................................... 4 Changes to Table 4 ............................................................................ 5 Added Table 5; Renumbered Sequentially .................................... 6 Changes to Figure 5 and Table 7 ..................................................... 8 Moved Typical Performance Characteristics Section .................. 9 Changes to Figure 9 .......................................................................... 9 Changes to Figure 23 ...................................................................... 14 Changes to Analog Inputs Section and Table 9 .......................... 15 Change to Single-Ended to Differential Driver Section Title ... 16 Changes to Power Supply Section ................................................ 16 Changes to Figure 30 ...................................................................... 18 Changes to Figure 32 ...................................................................... 19 Changes to Figure 34 ...................................................................... 20 Changes to Figure 36 ...................................................................... 21 Changes to Chain Mode with Busy Indicator ............................. 23 Changes to Applications Information Section............................ 24 Changes to Ordering Guide .......................................................... 25 Added Patent Footnote .....................................................................1 7/2013—Rev. A to Rev. B Added Low Power Dissipation of 4 mW at 1 MSPS (VDD only) to Features Section ............................................................................1 Changes to Power Dissipation; Table 3...........................................4 Added EPAD Notation to Figure 5 and Table 6 ............................7 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 10/2007—Rev. 0 to Rev. A Changes to Table 1 and Layout ........................................................1 Changes to Table 2.............................................................................3 Changes to Layout .............................................................................5 Changes to Layout .............................................................................6 Changes to Figure 5 ...........................................................................7 Changes to Figure 18 and Figure 20............................................. 11 Changes to Figure 23...................................................................... 13 Changers to Figure 26 .................................................................... 15 Changes to Digital Interface Section ........................................... 16 Changes to Figure 38...................................................................... 21 Changes to Figure 40...................................................................... 22 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 3/2007—Revision 0: Initial Version 6/2014—Rev. B to Rev. C Rev. D | Page 2 of 25 Data Sheet AD7982 SPECIFICATIONS VDD = 2.5 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, TA = −40°C to +85°C, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Common-Mode Input Range Analog Input Common Mode Rejection Ratio (CMRR) Leakage Current at 25°C Input Impedance ACCURACY No Missing Codes Differential Linearity Error (DNL) Integral Linearity Error (INL) Transition Noise Gain Error, TMIN to TMAX2 Gain Error Temperature Drift Zero Error, TMIN to TMAX2 Zero Temperature Drift Power Supply Rejection Ratio (PSRR) THROUGHPUT Conversion Rate Transient Response AC ACCURACY Dynamic Range Oversampled Dynamic Range4 Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion5 (THD) Signal-to-Noise-and-Distortion (SINAD) Test Conditions/Comments Min 18 IN+ − IN− IN+ and IN− IN+ and IN− fIN = 450 kHz −VREF −0.1 VREF × 0.475 Acquisition phase VREF × 0.5 67 Max Unit Bits +VREF VREF + 0.1 VREF × 0.525 V V V dB 200 See the Analog Inputs section 18 −0.85 −2 VREF = 5 V −0.023 VDD = 2.5 V ± 5% VIO ≥ 2.3 V VIO ≥ 1.71 V Full-scale step 0 0 VREF = 5 V VREF = 2.5 V FO = 1 kSPS fIN = 1 kHz, VREF = 5 V fIN = 1 kHz, VREF = 2.5 V fIN = 10 kHz fIN = 10 kHz fIN = 1 kHz, VREF = 5 V 97 1 Typ 95.5 ±0.5 ±1 1.05 +0.004 ±1 ±100 0.5 90 +1.5 +2 +0.023 +700 1 800 290 99 93 129 98 92.5 −115 −120 97 nA Bits LSB1 LSB1 LSB1 % of FS ppm/°C μV ppm/°C dB MSPS kSPS ns dB3 dB3 dB3 dB3 dB3 dB3 dB3 dB3 LSB means least significant bit. With the ±5 V input range, 1 LSB is 38.15 μV. See Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. All specifications expressed in decibels are referred to a full-scale input range (FSR )and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 Dynamic range is obtained by oversampling the ADC running at a throughput FS of 1 MSPS followed by postdigital filtering with an output word rate of FO. 5 Tested fully in production at fIN = 1 kHz. 2 3 Rev. D | Page 3 of 25 AD7982 Data Sheet VDD = 2.5 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, TA = −40°C to +85°C, unless otherwise noted. Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDD VIO Standby Current1, 2 Power Dissipation Total VDD Only REF Only VIO Only Energy per Conversion TEMPERATURE RANGE3 Specified Performance Test Conditions/Comments Min Typ 2.4 Max Unit 5.1 1 MSPS, VREF = 5 V 350 V μA VDD = 2.5 V 10 2 MHz ns VIO > 3 V VIO > 3 V VIO ≤ 3 V VIO ≤ 3 V –0.3 0.7 × VIO –0.3 0.9 × VIO −1 −1 Serial 18 bits, twos complement Conversion results available immediately after completed conversion 0.4 VIO − 0.3 ISINK = +500 μA ISOURCE = −500 μA 2.375 1.71 VDD and VIO = 2.5 V, 25°C VDD = 2.625 V, VREF = 5 V, VIO = 3 V 10 kSPS throughput 1 MSPS throughput TMIN to TMAX +0.3 × VIO VIO + 0.3 +0.1 × VIO VIO + 0.3 +1 +1 2.5 −40 1 With all digital inputs forced to VIO or GND as required. During acquisition phase. 3 Contact an Analog Devices, Inc., sales representative for the extended temperature range. 2 Rev. D | Page 4 of 25 V V 2.625 5.5 V V μA 86 8.6 μW mW mW mW mW nJ/sample +85 °C 0.35 70 7 4 1.7 1.3 7.0 V V V V μA μA Data Sheet AD7982 TIMING SPECIFICATIONS VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted.1 Table 4. Parameter CONVERSION AND ACQUISTION TIMES Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV PULSE WIDTH (CS MODE) SCK SCK Period (CS Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CS MODE CNV or SDI Low to SDO D17 MSB Valid VIO Above 3 V VIO Above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance SDI Valid Setup Time from CNV Rising Edge SDI Valid Hold Time from CNV Rising Edge CHAIN MODE SDI Valid Hold Time from CNV Rising Edge SCK Valid Setup Time from CNV Rising Edge SCK Valid Hold Time from CNV Rising Edge SDI Valid Setup Time from SCK Falling Edge SDI Valid Hold Time from SCK Falling Edge SDI High to SDO High (Chain Mode with Busy Indicator) 1 See Figure 2 and Figure 3 for load conditions. Rev. D | Page 5 of 25 Symbol Min tCONV tACQ tCYC tCNVH 500 290 1000 10 Typ Max Unit 710 ns ns ns ns tSCK 10.5 12 13 15 ns ns ns ns 11.5 13 14 16 4.5 4.5 3 ns ns ns ns ns ns ns tSCK tSCKL tSCKH tHSDO tDSDO 9.5 11 12 14 ns ns ns ns 10 15 20 ns ns ns ns ns tEN tDIS tSSDICNV tHSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 5 2 0 5 5 2 3 15 ns ns ns ns ns ns AD7982 Data Sheet VDD = 2.37 V to 2.63 V, VIO = 1.71 V to 2.3 V, −40°C to +85°C, unless otherwise stated.1 Table 5. Parameter THROUGHPUT RATE CONVERSION AND AQUISITION TIMES Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV PULSE WIDTH (CS MODE) SCK SCK Period (CS Mode) SCK Period (Chain Mode) SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay CS MODE CNV or SDI Low to SDO D17 MSB Valid CNV or SDI High or Last SCK Falling Edge to SDO High Impedance SDI Valid Setup Time from CNV Rising Edge SDI Valid Hold Time from CNV Rising Edge CHAIN MODE SDI Valid Hold Time from CNV Rising Edge SCK Valid Setup Time from CNV Rising Edge SCK Valid Hold Time from CNV Rising Edge SDI Valid Setup Time from SCK Falling Edge SDI Valid Hold Time from SCK Falling Edge SDI High to SDO High (Chain Mode with Busy Indicator) Min tCONV tACQ tCYC tCNVH 500 290 1.25 10 tSCK tSCK tSCKL tSCKH tHSDO tDSDO 22 23 6 6 3 tEN tDIS tSSDICNV tHSDICNV Typ Max 800 Unit kSPS 800 ns ns μs ns 14 21 18 40 20 ns ns ns ns ns ns ns ns ns ns 5 10 tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 0 5 5 2 3 ns ns ns ns ns ns 22 See Figure 2 and Figure 3 for load conditions. IOL Y% VIO1 X% VIO1 tDELAY 1.4V TO SDO CL 20pF 500µA IOH tDELAY VIH2 VIL2 VIH2 VIL2 1FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30. 2MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS IH IL SPECIFICATIONS IN TABLE 3. Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. D | Page 6 of 25 06513-003 500µA 06513-002 1 Symbol Data Sheet AD7982 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Analog Inputs IN+, IN− to GND1 Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance 10-Lead MSOP 10-Lead LFCSP θJC Thermal Impedance 10-Lead MSOP 10-Lead LFCSP Lead Temperatures Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to VREF + 0.3 V or ±130 mA −0.3 V to +6.0 V −0.3 V to +3.0 V +3 V to −6 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 200°C/W 48.7°C/W 44°C/W 2.96°C/W 215°C 220°C See the Analog Inputs section for an explanation of IN+ and IN−. Rev. D | Page 7 of 25 AD7982 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 VDD 2 IN+ 3 IN– 4 GND 5 IN– 4 TOP VIEW (Not to Scale) 9 SDI 8 SCK 7 SDO 6 CNV AD7982 9 SDI TOP VIEW (Not to Scale) 8 SCK 7 SDO 6 CNV GND 5 NOTES 1. EXPOSED PAD. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED PAD MUST BE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. Figure 4. 10-Lead MSOP Pin Configuration 06513-005 VDD 2 IN+ 3 AD7982 10 VIO 06513-004 REF 1 10 VIO Figure 5. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 Mnemonic REF Type1 AI 2 3 4 5 6 VDD IN+ IN− GND CNV P AI AI P DI 7 8 9 SDO SCK SDI DO DI DI 10 VIO EPAD P Description Reference Input Voltage. The REF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be decoupled closely to the GND pin with a 10 μF capacitor. Power Supply. Differential Positive Analog Input. Differential Negative Analog Input. Power Supply Ground. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the device: chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data must be read when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is a data input that daisy-chains the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is the output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Exposed Pad. For the lead frame chip scale package (LFCSP), the exposed pad must be connected to GND. This connection is not required to meet the electrical performances. 1 AI means analog input, DI means digital input, DO means digital output, and P means power. Rev. D | Page 8 of 25 Data Sheet AD7982 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V. 2.0 2.0 POSITIVE INL: +0.79 LSB NEGATIVE INL: –0.68 LSB 1.5 1.5 1.0 1.0 DNL (LSB) 0 –0.5 –1.0 0 –0.5 –1.5 –1.0 0 65536 131072 CODE 196608 262144 06513-006 –2.0 0.5 –1.5 –2.0 0 65536 131072 CODE 196608 262144 Figure 9. DNL vs. Code Figure 6. INL vs. Code 50000 60000 44806 43239 45000 50975 50000 40000 35000 COUNTS 32476 29064 30000 20000 30000 25000 20013 20000 16682 15000 7795 10000 0 3FFF0 0 29 3FFF2 745 881 3FFF4 3FFF6 3FFF8 43 0 3FFFA 0 3FFFC CODE IN HEX 06513-007 5000 0 0 7 145 0 1 2 3 4 5 6 7 8 9 222 7 0 0 A B C D CODE IN HEX 100 0 SNR (dB REFERRED TO FULL SCALE) fS = 1MSPS fIN = 2kHz –20 SNR = 97.3dB THD = –121.8dB SFDR = 120.2dB SINAD = 97.3dB –40 –60 –80 –100 –120 –140 –160 –180 100 200 300 FREQUENCY (kHz) 400 500 99 98 97 96 95 94 93 92 91 90 –10 06513-008 AMPLITUDE (dB OF FULL SCALE) 0 Figure 10. Histogram of a DC Input at the Code Transition Figure 7. Histogram of a DC Input at the Code Center 0 3158 2793 0 06513-010 10000 9064 –9 –8 –7 –6 –5 –4 –3 INPUT LEVEL (dB) Figure 11. SNR vs. Input Level Figure 8. Fast Fourier Transform (FFT) Plot Rev. D | Page 9 of 25 –2 –1 0 06513-032 COUNTS 40000 06513-009 INL (LSB) 0.5 AD7982 Data Sheet 18 100 –100 130 –105 125 SNR, SINAD 17 THD (dB) 115 –115 110 –120 THD 15 85 105 –125 2.75 3.25 3.75 4.25 REFERENCE VOLTAGE (V) 4.75 14 5.25 –130 2.25 06513-034 80 2.25 98 –117 96 –119 THD (dB) –115 94 –121 92 –123 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 –125 –55 06513-042 SNR (dB) 100 –35 3.25 3.75 4.25 REFERENCE VOLTAGE (V) 100 5.25 4.75 Figure 15. THD and SFDR vs. Reference Voltage Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage 90 –55 2.75 06513-033 ENOB ENOB (Bits) 16 90 SFDR (dB) 120 SFDR –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 06513-041 SNR, SINAD (dB) –110 1000 06513-030 95 Figure 16. THD vs. Temperature Figure 13. SNR vs. Temperature –80 100 –85 –90 95 THD (dB) 90 –105 –110 85 –115 –120 80 0.1 1 10 FREQUENCY (kHz) 100 1000 –125 0.1 06513-031 SINAD (dB) –95 –100 1 10 FREQUENCY (kHz) 100 Figure 17. THD vs. Frequency Figure 14. SINAD vs. Frequency Rev. D | Page 10 of 25 Data Sheet AD7982 1.4 1.4 IVDD IVDD 1.2 OPERATING CURRENTS (mA) 1.0 0.8 0.6 IREF 0.4 IVIO 0.2 2.475 2.525 SUPPLY VOLTAGE (V) 2.575 2.625 06513-036 2.425 0.6 IREF 0.4 IVIO 0 –55 Figure 18. Operating Currents vs. Supply Voltage 7 6 5 4 3 IVDD + IVIO 2 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 06513-038 1 –35 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 Figure 20. Operating Currents vs. Temperature 8 POWER-DOWN CURRENTS (µA) 0.8 0.2 0 2.375 0 –55 1.0 Figure 19. Power-Down Currents vs. Temperature Rev. D | Page 11 of 25 125 06513-035 OPERATING CURRENTS (mA) 1.2 AD7982 Data Sheet TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, that is, 0 V, from the actual voltage producing the midscale output code, that is, 0 LSB. Gain Error The first code transition (from 100 … 00 to 100 … 01) must occur at a level ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) must occur for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: Effective Resolution Effective resolution is calculated as Effective Resolution = log2(2N/RMS Input Noise) and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dB so it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. ENOB = (SINADdB − 1.76)/6.02 and is expressed in bits. Noise Free Code Resolution Noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as Noise Free Code Resolution = log2(2N/Peak-to-Peak Noise) and is expressed in bits. Rev. D | Page 12 of 25 Data Sheet AD7982 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB REF 131,072C 65,536C LSB 4C 2C C SW+ C BUSY COMP GND 131,072C 65,536C 4C 2C C CONTROL LOGIC C MSB OUTPUT CODE LSB SW– 06513-011 CNV IN– Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7982 is a fast, low power, single-supply, precise 18-bit ADC using a successive approximation architecture. The AD7982 is capable of converting 1,000,000 samples per second (1 MSPS) and powers down between conversions. When operating at 10 kSPS, for example, it typically consumes 70 µW, making it ideal for battery-powered applications. The AD7982 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7982 can interface to any 1.8 V to 5 V digital logic family. It is available in a 10-lead MSOP or a tiny 10-lead LFCSP that allows space savings and flexible configurations. It is pin for pin compatible with the 16-bit AD7980. CONVERTER OPERATION The AD7982 is a successive approximation ADC based on a charge redistribution DAC. Figure 21 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 18 binary weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the input of the comparator are connected to GND via Switch SW+ and Switch SW−. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ input and the IN− input. When the acquisition phase completes and the CNV input goes high, a conversion phase initiates. When the conversion phase begins, SW+ and SW− open first. The two capacitor arrays then disconnect from the inputs and connect to the GND input. Therefore, the differential voltage between the IN+ and IN− inputs captured at the end of the acquisition phase applies to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 … VREF/262,144). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of the conversion phase process, the device returns to the acquisition phase and the control logic generates the ADC output code and a busy signal indicator. Because the AD7982 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev. D | Page 13 of 25 AD7982 Data Sheet Transfer Functions Table 8. Output Codes and Ideal Input Voltages 011...111 011...110 011...101 1 2 100...010 –FSR + 1 LSB –FSR + 0.5 LSB +FSR – 1 LSB +FSR – 1.5 LSB ANALOG INPUT This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). This is also the code for an underranged analog input (VIN+ − VIN− below VGND). TYPICAL CONNECTION DIAGRAM Figure 23 shows an example of the recommended connection diagram for the AD7982 when multiple supplies are available. Figure 22. ADC Ideal Transfer Function Characteristic V+ Digital Output Code (Hex) 0x1FFFF1 0x00001 0x00000 0x3FFFF 0x20001 0x200002 REF1 2.5V 10µF2 100nF V+ 1.8V TO 5V 100nF 20Ω 0 TO VREF REF 2.7nF VDD V– AD7982 4 V+ 20Ω ADA4807-12, 3 SCK SDO IN– VREF TO 0 VIO SDI IN+ GND 3-WIRE INTERFACE CNV 2.7nF V– 4 NOTES 1 SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2C REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). SEE RECOMMENDED LAYOUT FIGURE 41 AND FIGURE 42. 3 SEE DRIVER AMPLIFIER CHOICE SECTION. 4 OPTIONAL FILTER. SEE ANALOG INPUT SECTION. Figure 23. Typical Application Diagram with Multiple Supplies Rev. D | Page 14 of 25 06513-013 100...001 100...000 –FSR Analog Input VREF = 5 V +4.999962 V +38.15 μV 0V −38.15 μV −4.999962 V −5 V Description FSR – 1 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 06513-012 ADC CODE (TWOS COMPLEMENT) The ideal transfer characteristic for the AD7982 is shown in Figure 22 and Table 8. Data Sheet AD7982 ANALOG INPUTS Figure 24 shows an equivalent circuit of the input structure of the AD7982. The two diodes, D1 and D2, provide electrostatic discharge (ESD) protection for the IN+ analog input and the IN− analog input. Take care to ensure the analog input signal does not exceed the reference input voltage (REF) by more than 0.3 V. If the analog input signal exceeds the 0.3 V level, the diodes become forward-biased and begin conducting current. These diodes can handle a forward-biased current of 130 mA maximum. However, if the supplies of the input buffer (for example, the supplies of the ADA4807-1 in Figure 23) are different from those of the REF, the analog input signal can eventually exceed the supply rails by more than 0.3 V. In such a case (for example, an input buffer with a short-circuit), the current limitation can protect the device. When the source impedance of the driving circuit is low, the AD7982 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. DRIVER AMPLIFIER CHOICE Although the AD7982 is easy to drive, the driver amplifier must meet the following requirements: REF D1 RIN CIN The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7982. The noise from the driver is filtered by the analog input circuit of the AD7982 1-pole, low-pass filter made by RIN and CIN, or by the external filter, if one is used. Because the typical noise of the AD7982 is 40 μV rms, the SNR degradation due to the amplifier is IN+ OR IN– D2 06513-014 CPIN GND SNRLOSS Figure 24. Equivalent Analog Input Circuit The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. 85 75 70 65 10 100 FREQUENCY (kHz) 1000 10000 06513-040 CMRR (dB) 80 1 Figure 25. Analog Input CMRR vs. Frequency During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the sampling phase where the switches are closed, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits noise. where: f–3dB is the input bandwidth, in megahertz, of the AD7982 (10 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp in nV/√Hz. 90 60 40 20 log π 2 2 40 f 3dB (NeN ) 2 For ac applications, the driver must have a THD performance commensurate with the AD7982. For multichannel, multiplexed applications, the driver amplifier and the AD7982 analog input circuit must settle for a full-scale step onto the capacitor array at an 18-bit level (0.0004%, 4 ppm). In the data sheet of the amplifier, settling at 0.1% to 0.01% is more typically specified. Settling time can differ significantly from the settling time at an 18-bit level and must be verified prior to driver selection. Table 9. Recommended Driver Amplifiers Amplifier ADA4941-1 ADA4940-1 ADA4807-2 ADA4627-1 ADA4522-2 ADA4500-2 Rev. D | Page 15 of 25 Typical Application Very low noise, low power, single to differential Very low noise, low power, single to differential Very low noise and low power Precision, low noise and low input bias Precision, zero drift, and electromagnetic interference (EMI) enhanced Precision, rail-to-rail input and output (RRIO), and zero input crossover distortion AD7982 Data Sheet SINGLE-ENDED TO DIFFERENTIAL DRIVER POWER SUPPLY For applications using a single-ended analog signal, either bipolar or unipolar, the ADA4941-1 single-ended to differential driver allows a differential input to the device. The circuit diagram is shown in Figure 26. The AD7982 uses two power supply pins: a core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 5.5 V. To reduce the number of supplies needed, tie VIO and VDD together. The AD7982 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 27. R1 and R2 set the attenuation ratio between the input range and the ADC voltage range (VREF). R1, R2, and CF are chosen depending on the desired input resistance, signal bandwidth, antialiasing, and noise contribution. For example, for the ±10 V range with a 4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ. 95 90 R3 and R4 set the common mode on the IN− input, and R5 and R6 set the common mode on the IN+ input of the ADC. Ensure the common mode is close to VREF/2. For example, for the ±10 V range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ. R5 R6 R3 R4 PSRR (dB) 85 80 75 70 10µF +5.2V 100nF REF OUTN 2.7nF OUTP 20Ω IN 1 10 100 FREQUENCY (kHz) 1000 Figure 27. PSRR vs. Frequency 20Ω 2.7nF 100nF 60 +2.5V 06513-039 65 +5V REF IN+ REF VDD The AD7982 powers down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. The power scaling linearly with throughput makes the device ideal for low sampling rates (even of a few hertz) and low battery-powered applications. AD7982 IN– GND FB ADA4941-1 10.000 R2 Figure 26. Single-Ended to Differential Driver Circuit VOLTAGE REFERENCE INPUT The AD7982 voltage reference input, REF, has a dynamic input impedance and must be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. When REF is driven by a very low impedance source (for example, a reference buffer using the AD8031 or the ADA4807-1), a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If using an unbuffered reference voltage, the decoupling value depends on the reference used. For instance, a 22 μF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR435 reference. If desired, use a reference decoupling capacitor with values as small as 2.2 μF with a minimal impact on performance, especially DNL. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins. Rev. D | Page 16 of 25 1.000 IVDD IREF 0.100 IVIO 0.010 0.001 10000 100000 SAMPLING RATE (SPS) 1000000 Figure 28. Operating Currents vs. Sampling Rate 06513-037 CF OPERATING CURRENTS (mA) R1 06513-015 ±10V, ±5V, .. –0.2V Data Sheet AD7982 DIGITAL INTERFACE Although the AD7982 has a reduced number of pins, it offers flexibility in its serial interface modes. When in CS mode, the AD7982 is compatible with SPI, QSPI, digital hosts, and digital signal processors (DSPs). In CS mode, the AD7982 can use either a 3-wire or 4-wire interface. A 3wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). The 4-wire interface is useful in low jitter sampling or simultaneous sampling applications. When in chain mode, the AD7982 provides a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. The mode in which the device operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high, and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. In either mode, the AD7982 offers the option of forcing a start bit in front of the data bits. The start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must timeout the maximum conversion time prior to readback. The busy indicator feature is enabled • • Rev. D | Page 17 of 25 In the CS mode if CNV or SDI is low when the ADC conversion ends (see Figure 32 and Figure 36). In the chain mode if SCK is high during the CNV rising edge (see Figure 40). AD7982 Data Sheet When the conversion completes, the AD7982 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 18th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. CS MODE, 3-WIRE WITHOUT BUSY INDICATOR CS mode, 3-wire without busy indicator is usually used when a single AD7982 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 29, and the corresponding timing is given in Figure 30. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. After a conversion is initiated, it continues until completion irrespective of the state of CNV. This feature can be useful, for instance, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. CONVERT DIGITAL HOST CNV VIO SDI AD7982 SDO DATA IN 06513-016 SCK CLK Figure 29. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 16 tHSDO 18 tSCKH tDSDO tEN SDO 17 D17 D16 D15 tDIS D1 D0 Figure 30. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High) Rev. D | Page 18 of 25 06513-017 SCK Data Sheet AD7982 When the conversion completes, SDO goes from high impedance to low impedance. With a pull-up resistor on the SDO line, the high impedance to low impedance transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7982 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 19th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. CS MODE, 3-WIRE WITH BUSY INDICATOR CS mode, 3-wire with busy indicator is usually used when a single AD7982 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 31, and the corresponding timing is given in Figure 32. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. If multiple AD7982 devices are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. CONVERT VIO DIGITAL HOST CNV VIO 47kΩ AD7982 DATA IN SDO IRQ SCK 06513-018 SDI CLK Figure 31. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 17 tHSDO 18 19 tSCKH tDSDO SDO D17 D16 tDIS D1 D0 Figure 32. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High) Rev. D | Page 19 of 25 06513-019 SCK AD7982 Data Sheet When the conversion completes, the AD7982 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 18th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance and another AD7982 can be read. CS MODE, 4-WIRE WITHOUT BUSY INDICATOR CS mode, 4-wire without busy indicator is usually used when multiple AD7982 devices are connected to an SPI-compatible digital host. A connection diagram example using two AD7982 devices is shown in Figure 33, and the corresponding timing is given in Figure 34. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. If SDI and CNV are low, SDO is driven low. Prior to the minimum conversion time, SDI can select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. CS2 CS1 CONVERT CNV AD7982 SDO SDI AD7982 SCK SDO DIGITAL HOST SCK 06513-020 SDI CNV DATA IN CLK Figure 33. CS Mode, 4-Wire Without Busy Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI(CS1) tHSDICNV SDI(CS2) tSCK tSCKL 1 2 16 3 tHSDO 18 19 20 D1 D0 D17 D16 34 35 36 D1 D0 tDSDO tEN SDO 17 tSCKH D17 D16 D15 tDIS Figure 34. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Rev. D | Page 20 of 25 06513-021 SCK Data Sheet AD7982 Prior to the minimum conversion time, SDI can select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. CS MODE, 4-WIRE WITH BUSY INDICATOR CS mode, 4-wire with busy indictor is usually used when a single AD7982 is connected to an SPI-compatible digital host with an interrupt input and when it is desired to keep CNV, which samples the analog input, independent of the signal used to select the data reading. This independence is particularly important in applications where low jitter on CNV is desired. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, the high impedance to low impedance transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7982 then enters the acquisition phase and powers down. The data bits then clock out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 19th SCK falling edge or SDI going high (whichever occurs first), SDO returns to high impedance. The connection diagram is shown in Figure 35, and the corresponding timing is given in Figure 36. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. If SDI and CNV are low, SDO is driven low. CS1 CONVERT VIO DIGITAL HOST CNV 47kΩ AD7982 DATA IN SDO IRQ SCK 06513-022 SDI CLK Figure 35. CS Mode, 4-Wire with Busy Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI tSCK tHSDICNV tSCKL 1 2 3 tHSDO 17 18 19 tSCKH tDSDO tDIS tEN SDO D17 D16 D1 Figure 36. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Rev. D | Page 21 of 25 D0 06513-023 SCK AD7982 Data Sheet When the conversion completes, the MSB is output onto SDO and the AD7982 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 18 × N clocks are required to read back the N ADCs. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7982 devices in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate can be reduced due to the total readback time. CHAIN MODE WITHOUT BUSY INDICATOR Chain mode without busy indicator can be used to daisy-chain multiple AD7982 devices on a 3-wire serial interface. The chain mode without busy indicator feature reduces component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. Figure 37 shows a connection diagram example using two AD7982 devices, and Figure 38 shows the corresponding timing. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. CONVERT SDI CNV AD7982 SDO SDI DIGITAL HOST AD7982 A B SCK SCK SDO DATA IN 06513-024 CNV CLK Figure 37. Chain Mode Without Busy Indicator Connection Diagram SDIA = 0 tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL tSSCKCNV SCK 1 tHSCKCNV 2 3 16 17 tSSDISCK 18 19 20 DA17 DA16 34 35 36 DA1 DA0 tSCKH tHSDISCK tEN SDOA = SDIB DA17 DA16 DA15 DA1 DA0 DB17 DB16 DB15 DB1 DB0 SDOB Figure 38. Chain Mode Without Busy Indicator Serial Interface Timing Rev. D | Page 22 of 25 06513-025 tHSDO tDSDO Data Sheet AD7982 In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7982 ADC labeled C in Figure 39) is driven high. The transition of driving the SDO pin of the ADC to high can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7982 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 18 × N + 1 clocks are required to read back the N ADCs. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7982 devices in the chain, provided the digital host has an acceptable hold time. CHAIN MODE WITH BUSY INDICATOR Chain mode with busy indicator can also daisy-chain multiple AD7982 devices on a 3-wire serial interface while providing a busy indicator. This chain mode with busy indicator feature reduces component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. Figure 39 shows a connection diagram example using three AD7982 devices, and Figure 40 shows the corresponding timing. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the busy indicator feature. CONVERT SDI CNV AD7982 SDO SDI CNV AD7982 SDO AD7982 SDI B SCK A SCK DIGITAL HOST SDO DATA IN C SCK IRQ 06513-026 CNV CLK Figure 39. Chain Mode with Busy Indicator Connection Diagram tCYC ACQUISITION tCONV tACQ ACQUISITION CONVERSION tSSCKCNV SCK tHSCKCNV 1 tEN 2 tSSDISCK SDOA = SDIB SDOB = SDIC 3 4 17 18 19 20 21 35 36 37 38 39 tSCKL tHSDISCK DA17 DA16 DA15 tDSDOSDI tSCK tSCKH DA1 54 55 tDSDOSDI DA0 tHSDO tDSDO tDSDOSDI DB17 DB16 DB15 DB1 DB0 DA17 DA16 DA1 DA0 DC17 DC16 DC15 DC1 DC0 DB17 DB16 DB1 DB0 DA17 DA16 tDSDOSDI SDOC 53 tDSDOSDI Figure 40. Chain Mode with Busy Indicator Serial Interface Timing Rev. D | Page 23 of 25 DA1 DA0 06513-027 CNV = SDIA AD7982 Data Sheet APPLICATIONS INFORMATION LAYOUT The printed circuit board (PCB) that houses the AD7982 must be designed so the analog and digital sections are separated and confined to certain areas of the PCB. The pin configuration of the AD7982, with its analog signals on the left side and its digital signals on the right side, eases the task of separating the analog and digital circuitry on a PCB. AD7982 It is recommended to use at least one ground plane. It can be common or split between the digital and analog sections. In the latter case, the planes must be joined underneath the AD7982 devices. 06513-028 Avoid running digital lines under the device; these couple noise onto the die, unless a ground plane under the AD7982 is used as a shield. Fast switching signals, such as CNV or clocks, must not run near analog signal paths. Crossover of digital and analog signals must be avoided. Figure 41. Example Layout of the AD7982 (Top Layer) Finally, decouple the power supplies of the AD7982, VDD and VIO, with ceramic capacitors, typically 100 nF, placed close to the AD7982 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. An example of layout following these rules is shown in Figure 41 and Figure 42. EVALUATING THE PERFORMANCE OF THE AD7982 Other recommended layouts for the AD7982 are outlined in the UG-340 user guide for the EVAL-AD7982SDZ. The evaluation board package includes a fully assembled and tested evaluation board, the user guide, and software for controlling the evaluation board from a PC via the EVAL-SDP-CB1Z. Rev. D | Page 24 of 25 06513-029 The AD7982 voltage reference input REF has a dynamic input impedance and must be decoupled with minimal parasitic inductances. Decoupling is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Figure 42. Example Layout of the AD7982 (Bottom Layer) Data Sheet AD7982 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 43. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 0.80 0.75 0.70 SEATING PLANE 0.30 0.25 0.20 0.20 MIN 1 5 BOTTOM VIEW TOP VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF 02-05-2013-C PIN 1 INDEX AREA Figure 44. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Model1, 2, 3 AD7982BRMZ AD7982BRMZRL7 AD7982BCPZ-RL7 AD7982BCPZ-RL EVAL-AD7982SDZ EVAL-SDP-CB1Z Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 10-Lead MSOP, Tube 10-Lead MSOP, 7” Reel 10-Lead LFCSP, 7” Reel 10-Lead LFCSP, 13” Reel Evaluation Board Controller Board 1 Package Option RM-10 RM-10 CP-10-9 CP-10-9 Branding C5F C5F C5F C5F Ordering Quantity 50 1,000 1,500 5,000 Z = RoHS compliant part. The EVAL-AD7982SDZ board can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes. 3 The EVAL-SDP-CB1Z board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SDZ designator. 2 ©2007–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06513-0-1/17(D) Rev. D | Page 25 of 25