SN74LS132 Quad 2-Input Schmitt Trigger NAND Gate The SN74LS132 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have greater noise margin than conventional NAND Gates. Each circuit contains a 2-input Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input thresholds (typically 800 mV) is determined internally by resistor ratios and is essentially insensitive to temperature and supply voltage variations. As long as one input remains at a more positive voltage than VT+ (MAX), the gate will respond to the transitions of the other input as shown in Figure 1. http://onsemi.com LOW POWER SCHOTTKY 14 1 PLASTIC N SUFFIX CASE 646 LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 13 12 11 10 9 8 14 1 1 2 3 4 5 6 SOIC D SUFFIX CASE 751A 7 GND GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current – High – 0.4 IOL Output Current – Low 8.0 Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 ORDERING INFORMATION Device Package Shipping mA SN74LS132N 14 Pin DIP 2000 Units/Box mA SN74LS132D 14 Pin 2500/Tape & Reel Publication Order Number: SN74LS132/D SN74LS132 VO, OUTPUT VOLTAGE (VOLTS) 5 VCC = 5 V TA = 25°C 4 3 2 1 0 0 0.4 0.95 1.2 VIN, INPUT VOLTAGE (VOLTS) 1.8 2 Figure 1. VIN versus VOUT Transfer Function DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Parameter Min Max Unit VT+ Positive-Going Threshold Voltage 1.5 2.0 V VCC = 5.0 V VT– Negative-Going Threshold Voltage 0.6 1.1 V VCC = 5.0 V VT + – VT– Hysteresis 0.4 V VCC = 5.0 V VIK Input Clamp Diode Voltage V VCC = MIN, IIN = – 18 mA VOH Output HIGH Voltage V VCC = MIN, IOH = – 400 µA, VIN = VIL VOL O Output LOW Voltage IT+ Input Current at Positive-Going Threshold – 0.14 mA VCC = 5.0 V, VIN = VT+ IT– Input Current at Negative-Going Threshold – 0.18 mA VCC = 5.0 V, VIN = VT– IIH Input HIGH Current IIL Input LOW Current Symbol IOS ICC Output Short Circuit Current Typ 0.8 – 0.65 2.7 (1) – 1.5 3.4 Test Conditions 0.25 0.4 V VCC = MIN, IOL = 4.0 mA, VIN = 2.0 V 0.35 0.5 V VCC = MIN, IOL = 8.0 mA, VIN = 2.0 V – 20 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V –100 mA VCC = MAX, VOUT = 0 V Power Supply Current Total, Output HIGH 5.9 11 mA VCC = MAX, VIN = 0 V Total, Output LOW 8.2 14 mA VCC = MAX, VIN = 4.5 V Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions VCC = 5.0 V CL = 15 pF tPLH Turn-Off Delay, Input to Output 22 ns tPHL Turn-On Delay, Input to Output 22 ns http://onsemi.com 2 SN74LS132 3V 1.6 V VIN 0.8 V 0V tPHL tPLH 1.3 V VOUT 1.3 V V T, THRESHOLD VOLTAGE (VOLTS) ∆ V T, HYSTERESIS (VOLTS) Figure 2. AC Waveforms 2 TA = 25°C VT+ 1.6 1.2 VT– 0.8 ∆ VT 0.4 0 4.5 4.75 5 5.25 VCC, POWER SUPPLY VOLTAGE (VOLTS) 5.5 V T, THRESHOLD VOLTAGE (VOLTS) ∆ V T, HYSTERESIS (VOLTS) Figure 3. Threshold Voltage and Hysteresis versus Power Supply Voltage 1.9 VT+ 1.7 1.5 1.3 1.1 VT– 0.9 0.7 – 55° ∆ VT 0° 25° 75° TA, AMBIENT TEMPERATURE (°C) Figure 4. Threshold Voltage and Hysteresis versus Temperature http://onsemi.com 3 125° SN74LS132 PACKAGE DIMENSIONS 14 8 B 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. N SUFFIX PLASTIC PACKAGE CASE 646–06 ISSUE M 7 A F DIM A B C D F G H J K L M N L N C –T– SEATING PLANE J K H D 14 PL G M 0.13 (0.005) 14 1 P 7 PL 0.25 (0.010) 7 G M B M R X 45 _ C F –T– SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 –B– D 14 PL 0.25 (0.010) T B J M K M S A MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 ––– 10_ 0.38 1.01 M D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F –A– INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 ––– 10_ 0.015 0.039 S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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