SN74LS273 Octal D Flip-Flop with Clear The SN74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing. • • • • http://onsemi.com 8-Bit High Speed Register Parallel Register Common Clock and Master Reset Input Clamp Diodes Limit High-Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA Parameter Supply Voltage Operating Ambient Temperature Range Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C 20 IOH Output Current – High – 0.4 mA IOL Output Current – Low 8.0 mA 1 PLASTIC N SUFFIX CASE 738 20 1 SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device SN74LS273N SN74LS273DW Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Package Shipping 16 Pin DIP 1440 Units/Box 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS273/D SN74LS273 CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP 20 19 18 17 16 15 14 13 12 11 1 MR 2 Q0 3 D0 4 D1 5 Q1 6 Q2 7 D2 8 D3 9 Q3 10 GND LOADING (Note a) PIN NAMES CP D0 – D7 MR Q0 – Q7 Clock (Active HIGH Going Edge) Input Data Inputs Master Reset (Active LOW) Input Register Outputs HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. TRUTH TABLE MR CP Dx Qx L H H X X H L L H L H = HIGH Logic Level L = LOW Logic Level X = Immaterial LOGIC DIAGRAM 11 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 CP 1 MR VCC = PIN 20 GND = PIN 10 = PIN NUMBERS http://onsemi.com 2 SN74LS273 FUNCTIONAL DESCRIPTION setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH transition of the clock input. The SN74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset. When the MR input is LOW, the Q outputs are LOW, independent of the other inputs. Information meeting the DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Min Typ Max 2.0 0.8 – 0.65 2.7 – 1.5 3.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA – 20 VCC = VCC MIN, VIN = VIL or VIH per Truth Table 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 27 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ 30 40 Max Unit Test Conditions MHz Figure 1 fMAX Maximum Input Clock Frequency tPHL Propagation Delay, MR to Q Output 18 27 ns Figure 2 Propagation Delay, Clock to Output 17 18 27 27 ns Figure 1 Max Unit Test Conditions 20 ns Figure 1 tPLH tPHL AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ tw Pulse Width, Clock or Clear ts Data Setup Time 20 ns Figure 1 th Hold Time 5.0 ns Figure 1 trec Recovery Time 25 ns Figure 2 http://onsemi.com 3 SN74LS273 AC WAVEFORMS 1/f max tW CP 1.3 V 1.3 V ts(H) D * Qn ts(L) trec tPHL 1.3 V tPLH tPHL 1.3 V 1.3 V tPHL tPLH 1.3 V CP th(L) 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V th(H) tW MR Qn 1.3 V 1.3 V 1.3 V 1.3 V tPLH Qn *The shaded areas indicate when the input is permitted to *change for predictable output performance. Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs. http://onsemi.com 4 SN74LS273 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE E –A– 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C –T– K SEATING PLANE M N E G F J D 0.25 (0.010) 20 PL 0.25 (0.010) 20 PL M T A M http://onsemi.com 5 M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 SN74LS273 D SUFFIX PLASTIC SOIC PACKAGE CASE 751D–05 ISSUE F q A 20 X 45 _ h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE DIM A A1 B C D E e H h L q C T http://onsemi.com 6 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ SN74LS273 Notes http://onsemi.com 7 SN74LS273 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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