Gennum GS9032-CTME3 Genlinx-tm ii gs9032 digital video serializer Datasheet

GENLINX ™II GS9032
Digital Video Serializer
DATA SHEET
DESCRIPTION
• SMPTE 259M and 540Mb/s compliant
The GS9032 encodes and serializes SMPTE 125M and
244M bit parallel digital video signals, and other 8-bit or
10-bit parallel formats. This device performs sync
detection, parallel to serial conversion, data scrambling
9
4
(using the X + X + 1 algorithm), 10x parallel clock
multiplication and conversion of NRZ to NRZI serial data.
The GS9032 features auto standard and adjustment free
operation for data rates to 540Mb/s with a single VCO
resistor. Other features include a lock detect output, NRZI
encoding, SMPTE scrambler bypass, a sync detect disable,
and an isolated quad output cable driver suitable for driving
75Ω loads. The complementary cable driving output swings
can be adjusted independently or the secondary differential
cable driver can be powered down.
• serializes 8-bit or 10-bit data
• autostandard, adjustment free operation
• minimal external components (no loop filter
components required)
• isolated, quad output, adjustable cable driver
• power saving secondary cable driver disable
• 3.3V and 5.0V CMOS/TTL compatible inputs
• lock detect indication
• SMPTE scramble and NRZI coding bypass option
• EDH support with GS9001, GS9021
• Pb-free and RoHS Comliant
The GS9032 requires a single +5 volt or -5 volt supply and
typically consumes 675mW of power while driving four 75Ω
loads.
APPLICATION
SMPTE 259M and 540Mb/s parallel to serial interfaces for
video cameras, VTRs, and signal generators; generic
parallel to serial conversion.
ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE
Pb-FREE AND RoHS COMPLIANT
GS9032 - CVM
44 pin TQFP
0°C to 70°C
No
GS9032 - CTM
44 pin TQFP Tape
0°C to 70°C
No
GS9032 - CVME3
44 pin TQFP
0°C to 70°C
Yes
GS9032 - CTME3
44 pin TQFP Tape
0°C to 70°C
Yes
SYNC DETECT DISABLE (SYNC DIS)
10
RESET
SYNC
DETECT
BYPASS
SDO0
2
10
DATA
IN
(PD0-PD9)
10
INPUT
LATCH
8
SMPTE
SCRAMBLER
RESET
BYPASS
PARALLEL
to SERIAL
CONVERTER
&
NRZ to NRZI
SDO0
SERIAL
DIGITAL
OUTPUTS
SDO1
SDO1
SCLK/10
SCLK
PLOAD
PARALLEL CLOCK
INPUT (PCLKIN)
SDO1
ENABLE
AUTO/MANUAL SELECT
(AUTO/MAN)
LOOP BANDWIDTH
CONTROL (LBWC)
PLL
MUTE
LOCK
DETECT
(LOCK DET)
3
DATA RATE SELECT
SS[2:0]
RVCO+
RVCO-
BLOCK DIAGRAM
Revision Date: May 2005
Document No. 521 - 96 - 09
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
GS9032
FEATURES
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
Supply Voltage (VS = VCC-VEE)
5.5V
Input Voltage Range (any input)
VEE<VIN<VCC
5mA
Power Dissipation (VCC = 5.25V)
1200mW
θj-a
42.5°C/W
θj-c
6.4°C/W
Maximum Die Temperature
GS90032
DC Input Current (any one input)
125°C
0°C ≤ TA ≤ 70°C
Operating Temperature Range
-65°C ≤ TS ≤ 150°C
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
260°C
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA = 0° – 70°C unless otherwise specified.
PARAMETER
SYMBOL
Positive Supply Voltage
VCC
Power (System Power)
P
Supply Current
Data & Clock Inputs
(PD[9:0] PCLKIN)
SYNC DIS
Logic Input Levels
(Auto/Man, SS[2:0]
Bypass, RESET)
Lock Detect Output
ΙCC
CONDITIONS
TYP
MAX
UNITS
4.75
5.00
5.25
V
3
VCC = 5.0V, T = 25°C (4 outputs)
-
675
-
mW
5
VCC = 5.25V (4 outputs)
-
-
180
mA
1
VCC = 5.0V, T = 25°C (4 outputs)
-
135
-
3
VCC = 5.25V (2 outputs)
-
-
160
1
VCC = 5.0V, T = 25°C (2 outputs)
-
110
-
7
Operating Range
VIH
Logic Input High (wrt VEE)
2.4
-
-
V
VIL
Logic Input Low (wrt VEE)
-
-
0.8
V
ΙL
Input Current
-
-
8.0
µA
VIH
Logic Input High (wrt to VEE)
2.4
-
-
V
VIL
Logic Input Low (wrt to VEE)
-
-
0.8
V
ΙL
Input Current
-
-
5.0
µA
VOL
Sinking 500µA
-
-
0.4
V
NOTES
TEST
LEVEL
MIN
3
3
1
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
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AC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA = 0° – 70°C unless otherwise specified.
PARAMETER
TYP
MAX
UNITS
NOTES
RVCO = 374Ω
143
-
540
Mb/s
SMPTE
259M
VSDO
RLOAD = 37.5Ω, RSET = 54.9Ω
740
800
860
mVp-p
1
Min. Swing (adjusted)
VSDOMIN
RLOAD = 37.5Ω, RSET = 73.2Ω
-
600
-
mVp-p
7
Max. Swing (adjusted)
VSDOMAX
RLOAD = 37.5Ω, RSET = 43.2Ω
-
1000
-
mVp-p
1
400
-
700
ps
7
-
-
7
%
1
7
1
7
SD Rise/Fall Times
tr, tf
20% - 80%
SD Overshoot/Undershoot
3
Output Return Loss
ORL
at 540MHz
15
-
-
dB
Lock Time
tLOCK
Worst case
-
-
5
ms
6
270Mb/s
-
220
-
kHz
7
-
500
-
kHz
7
-
1.7
-
MHz
7
UI
3
Min. Loop Bandwidth
BWMIN
LBWC = Grounded : BWMIN
Typical Loop Bandwidth
BWTYP
270Mb/s
LBWC = Floating :
Max. Loop Bandwidth
BWMAX
10 BWMIN
270Mb/s
LBWC = VCC : 10 BWMIN
Intrinsic Jitter (6σ)
Data & Clock Inputs
(PD[9:0] PCLKIN)
143Mb/s
LBWC = floating
-
0.07
-
177Mb/s
LBWC = VCC
-
0.07
-
270Mb/s
-
0.08
-
360Mb/s
-
0.09
-
540Mb/s
-
0.11
-
tSU
Setup Time at 25°C
2.5
-
-
ns
3
tH
Hold Time at 25°C
2.0
-
-
ns
3
TEST LEVELS
NOTES
1. Production test at room temperature and nominal supply voltage with guardbands for
supply and temperature ranges.
1. Depends on PCB layout.
2. Production test at room temperature and nominal supply voltage with guardbands for
supply and temperature ranges using correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
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521 - 96 - 09
GS90032
Serial Data Outputs Signal
Swing
BRSDO
CONDITIONS
TEST
LEVEL
MIN
Serial Data Bit Rate
SYMBOL
44 43 42 41 40 39 38 37 36 35
VCC1
VEE1
RVCO+
RVCO-
NC
VEE
LF+
LBWC
VEE
LF-
SYNC DIS
PIN CONNECTIONS
34
1
33
PD8
2
32
AUTO/MAN
PD7
3
31
BYPASS
PD6
4
30
RSET1
PD5
5
29
VEE
PD4
6
PD3
GS9032
TOP VIEW
28
SDO1
7
27
SDO1
PD2
8
26
VEE
PD1
9
25
SDO0
PD0
10
24
SDO0
PCLKIN
11
23
VEE
GS90032
RESET
PD9
RSET0
SSO
LOCK DET
VEE2
SDO1 ENABLE
VCC2
SS1
SS2
COSC
VEE3
VCC3
12 13 14 15 16 17 18 19 20 21 22
PIN DESCRIPTIONS
NUMBER
SYMBOL
TYPE
DESCRIPTION
1-10
PD9 - PD0
I
CMOS or TTL compatible parallel data inputs. PD0 is the LSB and PD9 is the MSB.
11
PCLKIN
I
CMOS or TTL compatible parallel clock input.
12
VEE3
-
Most negative power supply connection for parallel data and clock inputs.
13
VCC3
-
Most positive power supply connection for parallel data and clock inputs.
14
COSC
I
Master Timer Capacitor. A capacitor should be added to decrease the system clock
frequency when an external capacitor is used across LF+ and LF- (NC if not used).
15, 16, 21
SS2, SS1, SS0
I
Data rate selection when in manual mode. These pins are not used in auto mode.
17
VCC2
-
Most positive power supply connection for internal logic and digital circuits.
18
VEE2
-
Most negative power supply connection for internal logic and digital circuits.
19
SDO1 ENABLE
I
Enable pin for the secondary cable driver (SDO1 and SDO1). Connect to most negative
power supply to enable. Leave open to disable (do NOT connect to VCC).
20
LOCK DET
O
TTL level which is high when the internal PLL is locked.
22
RSET0
I
External resistor used to set the data output amplitude for SDO0 and SDO0.
23, 26, 29
VEE
-
Most negative power supply connection for shielding (not connected).
24, 25
SDO0, SDO0
O
Primary, current mode, 75Ω cable driving output (inverse and true)
27, 28
SDO1, SDO1
O
Secondary, current mode, 75Ω cable driving output (inverse and true)
30
RSET1
I
External resistor used to set the data output amplitude for SDO1 and SDO1.
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PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
31
BYPASS
I
When high, the SMPTE Scrambler and NRZ encoder are bypassed.
32
AUTO/MAN
I
Autostandard or manual mode selectable operation.
33
RESET
I
Resets the scrambler when asserted.
34
VCC1
-
Most positive power supply connection for analog circuits.
35
VEE1
-
Most negative power supply connection for analog circuits.
36, 38
RVCO+, RVCO-
I
Differential VCO current setting resistor that sets the VCO frequency.
37
NC
I
No Connect.
39, 43
VEE
-
Most negative power supply connection (substrate).
40
LBWC
I
TTL level loop bandwidth control that adjusts the PLL bandwidth to optimize for lowest
jitter. If the pin is set to ground the loop bandwidth is BWMIN. If the pin is left floating, the
loop bandwidth is approximately 3 BWMIN, if the pin is tied to VCC the loop bandwidth is
approximately10 BWMIN
41, 42
LF+, LF-
I
Differential loop filter pins to optimize loop transfer performance at low loop bandwidths
(NC if not used).
44
SYNC DIS
I
Sync detect disable. Logic high disables sync detection. Logic low allows 8 bit operation
by mapping 000-003 to 000 and 3FC-3FF to 3FF.
GS90032
NUMBER
TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25°C unless otherwise shown. Guard band tested to 70°C only.)
500
155
150
480
4.75 RISE
470
CURRENT (mA)
RISE / FALL TIME (ps)
490
5.0 RISE
460
5.0 FALL
5.25 RISE
450
4.75 FALL
145
5.25
140
5.0
135
5.25 FALL
440
4.75
130
430
125
420
0
20
40
60
0
80
TEMPERATURE (˚C)
20
40
60
80
TEMPERATURE (˚C)
Fig. 1 Rise/Fall Times vs. Temperature
Fig. 2 Supply Current vs. Temperature (SDO0 & SDO1 ON)
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521 - 96 - 09
4ƒsc
DATA
STREAM
ACTIVE VIDEO
& H BLANKING
ACTIVE
VIDEO
E
A
V
ACTIVE VIDEO
& H BLANKING
E
A
V
S
H
BLNK A
V
5.25
1.000
5.0
SYNC
DETECT
4.75
PCLK IN
0.995
PDN XXX 3FF 000 000 XXX •••
0
20
40
60
S
A
V
XXX 3FF 000 000 XXX •••
80
SYNC
DETECT
TEMPERATURE (˚C)
Fig. 3a Output Swing vs. Temperature (1000mV)
Fig. 5 Timing Diagram
160
0.8075
140
0.805
5.25
120
0.8025
LF+ — LF- (mV)
OUTPUT SWING (V)
•••
H
BLNK
GS90032
4:2:2
DATA
STREAM
1.005
0.99
T
R
S
SYNC
DETECT
1.01
OUTPUT SWING (V)
T
R
S
T
R
S
5.0
0.800
4.75
0.7975
100
80
60
40
0.795
20
0.7925
0
20
40
60
0
80
0
20
TEMPERATURE (˚C)
40
60
80
TEMPERATURE (˚C)
Fig. 3b Output Swing vs. Temperature (800mV)
Fig. 6a Loop Filter Voltage vs. Temperature (360 Mode)
40
tCLKL = tCLKH
20
50%
LF+ — LF- (mV)
PARALLEL
CLOCK
PLCK
0
-20
-40
PARALLEL
DATA
PDn
-60
tSU
0
tHOLD
20
40
60
80
TEMPERATURE (˚C)
Fig. 4 Waveforms
Fig. 6b Loop Filter Voltage vs. Temperature (540 Mode)
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3000
2500
2000
GS90032
LOOP BANDWIDTH (kHz)
3500
LBWC to VCC
1500
1000
LBWC FLOATING
500
LBWC GROUNDED
0
0
143
177
270
360
540
DATA RATE (Mb/s)
Fig. 10 Output Eye Diagram (270Mb/s)
Fig. 7 Loop Bandwidth vs. Data Rate
600
JITTER p-p (ps)
500
400
300
200
100
For a data rate of 270Mb/s
0
GROUNDED
FLOATING
VCC
LOOP BANDWIDTH CONTROL (LBWC)
Fig. 11 Output Eye Diagram (540Mb/s)
Fig. 8 Output Jitter vs. LBWC
500
JITTER p-p (ps)
400
300
200
100
0
0
100
200
300
400
500
600
DATA RATE (Mb/s)
Fig. 9 Output Jitter vs. Data Rate
(Optimum LBW Setting)
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521 - 96 - 09
DETAILED DESCRIPTION
4. VCO CENTRE FREQUENCY SELECTION
For a given RVCO value, the VCO can oscillate at one of two
frequencies. When SS0=logic 1, the VCO centre frequency
corresponds to the ƒL curve. For SS0=logic 0, the VCO
centre frequency corresponds to the ƒH curve (ƒH is
approximately 1.5 x ƒL).
800
700
1. SYNC DETECTOR
The sync detector makes the system compatible with eight
or ten bit data. It looks for the reserved words 000-003 and
3FC-3FF in ten bit hexadecimal, or 00 and FF in eight bit
hexadecimal, used in the TRS-ID sync word. When the
occurrence of either all zeros or all ones at inputs PD2-PD9
is detected, the lower two bits PD0 and PD1 are forced to
zeros or ones respectively. For non-SMPTE standard
parallel data, the sync detector can be disabled through a
logic input, Sync Detect Disable (44).
600
500
400
ƒH
300
SSO=0
200
ƒL
100
SSO=1
0
0
200
400
600
800
1000
1200 1400
1600 1800
RVCO (Ω)
Fig. 12
2. SCRAMBLER
The scrambler is a linear feedback shift register used to
pseudo-randomize the incoming serial data according to
the fixed polynomial (X9+X4+1). This minimizes the DC
component in the output serial data stream. The NRZ to
NRZI converter uses another polynomial (X+1) to convert a
long sequence of ones to a series of transitions, minimizing
polarity effects. These functions can be disabled by setting
the BYPASS pin (31) high.
3. PHASE LOCKED LOOP
The PLL performs parallel clock multiplication and provides
the timing signal for the serializer. It is composed of a
phase/frequency detector (with no dead zone), charge
pump, VCO, a divide-by-ten counter, and a divide-by-two
counter.
The phase/frequency detector allows a wider capture range
and faster lock time than with a phase discriminator alone.
The discrimination of frequency eliminates harmonic
locking. With this type of discriminator, the PLL can be overdamped for good stability without sacrificing lock time.
The charge pump delivers a 'charge packet' to the loop
filter which is proportional to the system phase error.
Internal voltage clamps are used to constrain the loop filter
voltage between approximately 1.8 and 3.4 volts.
The VCO is a differential low phase noise, factory trimmed
design that provides increased immunity to PBC noise and
precise control of the VCO centre frequency. The VCO can
operate in excess of 800MHz and has a pull range of ±15%
The recommended RVCO value for auto rate SMPTE 259M
applications is 374Ω (see the Typical Application Circuit).
This value prevents false standards indication in auto mode.
For non-SMPTE applications (where data rates are x2
harmonically related) use Figure 12 to determine the RVCO
values.
The VCO and an internal divider generate the PLL clock.
Divider moduli of 1, 2, and 4 allow the PLL to lock to data
rates from 143Mb/s to 540Mb/s. The divider modulus is set
by the AUTO/MAN, and SS[2:0] pins (see Truth Table for
further details). In addition, a manually selectable modulus
8 divider allows operation at data rates as low as 18Mb/s
when RVCO is increased to 1kΩ.
When the loop is not locked, the lock detect circuit mutes
the serial data outputs. When the loop is locked, the Lock
Detect output is available from pin 20 and is HIGH.
The true and complement serial data, SDO and SDO, are
available from pins 24, 25, 27 and 28. These outputs drive
four 75Ω co-axial cables with SMPTE level serial digital
video signals. To disable the outputs from pins 27 and 28
(SDO1, SDO1), remove the resistor connected to the RSET1
pin (30) and float the SDO1 ENABLE pin (19).
NOTE: Do NOT connect pin 19 to VCC.
RSET calculation:
1.154 × R LOAD
R SET = -------------------------------------V SDO
where RLOAD = RPULL-UP || Z
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521 - 96 - 09
GS90032
Functional blocks within the device include the input
latches, sync detector, parallel to serial converter, SMPTE
scrambler, NRZ to NRZI converter, internal cable driver, PLL
for 10x parallel clock multiplication and lock detect. The
parallel data (PD0-PD9) and parallel clock (PCLKIN) are
applied via pins 1 through 11 respectively.
about the centre frequency. The single external resistor,
RVCO, sets the VCO frequency (see Figure 12).
VCO FREQUENCY (MHz)
The GS9032 Serializer is a bipolar integrated circuit used to
convert parallel data into a serial format according to the
SMPTE 259M standard. The device encodes both eight and
ten bit TTL-compatible parallel signals producing serial
data rates up to 540Mb/s. It operates from a single five volt
supply and is packaged in a 44 pin TQFP.
TYPICAL APPLICATION CIRCUIT (SMPTE Auto Mode)
VCC
VCC
J1
100n
LBWC
374
2 PD8
VEE1
VCC1
RVCO+
NC
VEE
RVCO
LBWC
LF-
LF+
VEE
AUTO/MAN
BYPASS_EN
4 PD6
RSET1
5 PD5
VEE
GS9032
6 PD4
SDO1
7 PD3
SDO1
8 PD2
VEE
9 PD1
RSET0
SS0
SDO0
LOCK
SDO1_EN
VEE2
VCC2
SS1
SS2
VCC3
VEE3
11 PCLKIN
NC (COSC)
SDO0
10 PD0
PARALLEL
CLOCK
INPUT
VCC
RESET
3 PD7
PARALLEL
DATA
INPUTS
VCC
VEE
33
100n
RESET
32
31
54.9
29
R
27
L
26
R
25
L
24
J3
R
75
L
75
SS0*
SS1*
SS2*
1µ
23
1µ
J4
VCC
100n
10k
R
VCC
L = 8.2nH
220
100n
All resistors on ohms,
all capacitors in farads,
unless otherwise stated.
1µ
J2
0
VCC
J1
75
28
54.9
VCC
1µ
L
75
30
12 13 14 15 16 17 18 19 20 21 22
100n
GS90032
1 PD9
SYNC_DIS
44 43 42 41 40 39 38 37 36 35 34
R = 75Ω
LOCK
* See Truth Table for settings. NC in auto mode.
TRUTH TABLE (Manual Mode)
DATA RATE
(Mb/s)
SS2
SS1
SS0
DIVIDER
MODULI
VCO
FREQUENCY
143
0
0
0
4
ƒH
177
0
0
1
2
ƒL
270
0
1
0
2
ƒH
360
0
1
1
1
ƒL
540
1
0
0
1
ƒH
45
1
0
1
8
ƒL
68
1
1
0
8
ƒH
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PACKAGE DIMENSIONS
12.00
10.00
12˚ TYP
0.20 MIN
7˚ MAX
0˚ MIN
12.00
10.00
0.20 MAX
RADIUS
GS90032
0 MIN
12˚ TYP
0.60
±0.15
0.08 MIN.
RADIUS
PIN 1
0.20 MIN
0.80
0.30
1.00
44 pin TQFP
1.10
0.10
All dimensions in millimetres
0.127
REVISION HISTORY
VERSION
ECR
DATE
9
136657
May 2005
CHANGES AND/OR MODIFICATIONS
Removed reference to EDH FPGA core. Changed ‘Green’ references to ‘RoHS
Compliant’.
DOCUMENT IDENTIFICATION
CAUTION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
GENNUM CORPORATION
Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo,
160-0023 Japan
Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505
GENNUM UK lIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no liability for any errors or omissions in this
document, or for the use of the circuits or devices described herein. The sale
of the circuit or device described herein does not imply any patent license,
and Gennum makes no representation that the circuit or device is free from
patent infringement.
GENNUM and the G logo are registered trademarks of Gennum Corporation.
© Copyright 1998 Gennum Corporation. All rights reserved.
Printed in Canada.
www.gennum.com
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