LXT36x/35x Master Clock Requirements Application Note January 2001 Order Number: 249172-001 As of January 15, 2001, this document replaces the Level One document known as AN087. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. 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Application Note LXT36x/35x Master Clock Requirements Contents 1.0 General Description ......................................................................................................... 5 1.1 Addressing Master Clock 20 Year Accuracy Issue ..............................................5 1 2 T1 Jitter Attenuation Characteristics ..................................................................... 6 E1 Jitter Attenuation Characteristics ..................................................................... 7 1 2 LXT36x/35x T1 jitter transfer measured per ATT Pub. 62411............................... 6 LXT36x/35x E1 Jitter Transfer Measured per G.736............................................. 8 Figures Tables Application Note 3 LXT36x/35x Master Clock Requirements 1.0 General Description The LXT360/61 and LXT350/51 require an external Master Clock (MCLK) independent from RCLK. The MCLK was originally defined to be jitter free and its accuracy to be better than ±32 ppm. A Master Clock (MCLK) with ±32 ppm accuracy requires a clock oscillator with a standard accuracy of ±25 ppm. This requirement makes the clock oscillator relatively expensive. MCLK is used as timing reference in the Jitter Attenuator and the clock recovery system. Its accuracy has an impact on the JA performance. Early analysis suggested that ±32 ppm is the minimum clock accuracy requirement for reliable performance against G.736 and Pub.62411 jitter transfer requirements. This report summarizes Jitter transfer performance tests on the LXT35x/36x transceivers with worst case frequency offsets. Tests have been done with MCLK specified with ±50 ppm and ±32 ppm accuracy. From the device theory of operation, it is known that the Jitter Attenuator performance is sensitive to frequency offsets between the frequency of the incoming signal and the frequency of the MCLK. The signal on the line is specified to be ±32ppm for T1 systems (per ANSI T1.408) and ±50 ppm for E1 systems (per ITU-G.703). In T1 applications, the maximum delta is (1.544 MHz ±50 ppm) (1.544 MHz ±32 ppm) = 82 ppm. The equivalent maximum frequency deviation is ±126.6 Hz. Table 1 on page 6 represents the jitter transfer performance measured per ATT Pub.62411 with both ±32 ppm and ±50 ppm MCLK stability. In both cases the performance stays well within Pub62411 limits, although there is an insignificant degradation of the performance with ±50 ppm vs. ±32 ppm. Figure 1 on page 6 shows T1 jitter transfer performance against Pub. 62411. In E1 systems, the line signal stability is ±50ppm. The maximum delta for E1 systems is (2.048 MHz ±50 ppm) -(2.048 ±50 ppm) = 100 ppm. The equivalent maximum frequency deviation is ±204.8 Hz. Table 2 on page 8 shows E1 jitter transfer performance measured per G.736 with MCLK of ±32 ppm and ±50 ppm stability. The performance degrades insignificantly with ±50 ppm but it is still well above the G.736 requirements as shown in Figure 2 on page 7. Jitter tolerance performance in both T1 and E1 applications is not affected by relaxing the MCLK from ±32 ppm to ±50 ppm. 1.1 Addressing Master Clock 20 Year Accuracy Issue Although, today the life cycle of Telecom Equipment gets shorter, some systems will operate for the next 20 years. In the previous section, we concluded that the LXT36x/35x needs ±50 stability on MCLK. Every clock oscillator undergoes an aging process and its stability will change over time. It is important to select a clock oscillator with 20 years stability with ±50 ppm or better. We recommend two manufacturers of clock oscillators meeting long term (20 years) stability requirements. Application Note 5 LXT36x/35x Master Clock Requirements Manufacturer Part # for T1 Application Part # for E1 Application ECLIPTEK Corp. ECX0-8421.544M ECX0-843-2.048M EPSON Corp. HG-1012JA1544000-BX HG-1012JA2048000-BX Figure 1. T1 Jitter Attenuation Characteristics Table 1. 6 LXT36x/35x T1 jitter transfer measured per ATT Pub. 62411 Freq Jitter Atten W/MCLK = 1.544 MHz ±32ppm Jitter Atten W/MCLK = 1.544 MHz ±50 ppm 2 -2.20 -1.50 5 -6.12 -5.07 10 -13.10 -11.32 50 -21.21 -18.74 100 -28.04 -26.11 300 -32.70 -29.91 Application Note LXT36x/35x Master Clock Requirements Table 1. LXT36x/35x T1 jitter transfer measured per ATT Pub. 62411 Freq Jitter Atten W/MCLK = 1.544 MHz ±32ppm Jitter Atten W/MCLK = 1.544 MHz ±50 ppm 500 -34.18 -32.09 1000 -53.10 -51.81 2000 -54.02 -52.12 5000 -54.31 -52.28 10000 -53.81 -51.75 40000 -54.08 -52.10 50000 -53.15 -50.91 70000 -53.04 -50.80 Figure 2. E1 Jitter Attenuation Characteristics Application Note 7 LXT36x/35x Master Clock Requirements Table 2. 8 LXT36x/35x E1 Jitter Transfer Measured per G.736 Freq Jitter Atten W/MCLK = 2.048 MHz ±32ppm [dB] Jitter Atten W/ MCLK = 2.048 MHz ±50 ppm [dB] 2 -1.72 -1.30 5 -7.78 -6.22 10 -11.38 -9.63 50 -21.09 -18.81 100 -33.18 -30.12 300 -42.55 39.22 500 -50.97 -48.51 1000 -57.64 -56.31 2000 -58.01 -56.41 5000 -58.08 -56.51 10000 -58.90 -56.50 40000 -58.81 -56.53 50000 -59.10 -56.82 70000 -58.72 -55.94 Application Note