Freescale MC145152DW2 Pll frequency synthesizers (cmos) Datasheet

Freescale Semiconductor
Technical Data
MC145151-2/D
Rev. 5, 12/2004
MC145151-2
MC145152-2
28
28
MC145151-2 and
MC145152-2
1
PLL Frequency Synthesizers
(CMOS)
The devices described in this document are typically
used as low-power, phase-locked loop frequency
synthesizers. When combined with an external low-pass
filter and voltage-controlled oscillator, these devices can
provide all the remaining functions for a PLL frequency
synthesizer operating up to the device's frequency limit.
For higher VCO frequency operation, a down mixer or a
prescaler can be used between the VCO and the
synthesizer IC.
These frequency synthesizer chips can be found in the
following and other applications:
CATV
TV Tuning
AM/FM Radios
Scanning Receivers
Two-Way Radios
Amateur Radio
OSC
÷R
φ
CONTROL
LOGIC
÷A
÷ P/P + 1
1
Package Information
DW Suffix
P Suffix
SOG Package
Plastic DIP
Case 751F
Case 710
÷N
Ordering Information
Device
Package
MC145151P2
Plastic DIP
MC145151DW2
SOG Package
MC145152P2
Plastic DIP
MC145152DW2
SOG Package
Contents
1 MC145151-2 Parallel-Input (Interfaces with
Single-Modulus Prescalers) . . . . . . . . . . . . . 2
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Typical Applications . . . . . . . . . . . . . . . . . . . 6
2 MC145152-2 Parallel-Input (Interfaces with
Dual-Modulus Prescalers) . . . . . . . . . . . . . . . 7
2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Typical Applications . . . . . . . . . . . . . . . . . . 10
3 MC145151-2 and MC145152-2
Electrical Characteristics . . . . . . . . . . . . . . 12
4 Design Considerations . . . . . . . . . . . . . . . . 18
4.1 Phase-Locked Loop — Low-Pass Filter
Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Crystal Oscillator Considerations . . . . . . . . 19
4.3 Dual-Modulus Prescaling . . . . . . . . . . . . . . 21
5 Package Dimensions . . . . . . . . . . . . . . . . . . 23
VCO
OUTPUT FREQUENCY
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers)
1
MC145151-2 Parallel-Input (Interfaces with
Single-Modulus Prescalers)
The MC145151-2 is programmed by 14 parallel-input data lines for the N counter and three input lines for
the R counter. The device features consist of a reference oscillator, selectable-reference divider,
digital-phase detector, and 14-bit programmable divide-by-N counter.
The MC145151-2 is an improved-performance drop-in replacement for the MC145151-1. The power
consumption has decreased and ESD and latch-up performance have improved.
1.1
•
•
•
•
•
•
•
•
•
•
•
•
Features
Operating Temperature Range: - 40 to 85°C
Low Power Consumption Through Use of CMOS Technology
3.0 to 9.0 V Supply Range
On- or Off-Chip Reference Oscillator Operation
Lock Detect Signal
÷ N Counter Output Available
Single Modulus/Parallel Programming
8 User-Selectable ÷ R Values: 8, 128, 256, 512, 1024, 2048, 2410, 8192
÷ N Range = 3 to 16383
“Linearized” Digital Phase Detector Enhances Transfer Function Linearity
Two Error Signal Options: Single-Ended (Three-State) or Double-Ended
Chip Complexity: 8000 FETs or 2000 Equivalent Gates
fin 1 •
28
LD
VSS 2
27
OSCin
VDD 3
26
OSCout
PDout 4
25
N11
RA0 5
24
N10
RA1 6
23
N13
RA2 7
22
N12
φR 8
21
T/R
φV 9
20
N9
fV
10
19
N8
N0
11
18
N7
N1
12
17
N6
N2
13
16
N5
N3
14
15 N4
Figure 1. MC145151-2 Pin Assignment
MC145151-2 and MC145152-2 Technical Data, Rev. 5
2
Freescale Semiconductor
MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers)
RA2
RA1
RA0
OSCout
14 x 8 ROM REFERENCE DECODER
LOCK
DETECT
14
LD
14-BIT ÷ R COUNTER
OSCin
PHASE
DETECTOR
A
PDout
14-BIT ÷ N COUNTER
fin
VDD
PHASE
DETECTOR
B
14
TRANSMIT OFFSET ADDER
T/R
φV
φR
fV
N13
N11
N9
N7 N6
N4
N2
N0
NOTE: N0 - N13 inputs and inputs RA0, RA1, and RA2 have pull-up resistors that are not shown.
Figure 2. MC145151-2 Block Diagram
1.2
1.2.1
Pin Descriptions
Input Pins
fin
Frequency Input (Pin 1)
Input to the ÷ N portion of the synthesizer. fin is typically derived from loop VCO and is ac coupled into
the device. For larger amplitude signals (standard CMOS logic levels) dc coupling may be used.
RA0 - RA2
Reference Address Inputs (Pins 5, 6, 7)
These three inputs establish a code defining one of eight possible divide values for the total reference
divider, as defined by the table below.
Pull-up resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter
data to the zero state.
Reference Address Code
RA2
RA1
RA0
Total
Divide
Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
128
256
512
1024
2048
2410
8192
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
3
MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers)
N0 - N11
N Counter Programming Inputs (Pins 11 - 20, 22 - 25)
These inputs provide the data that is preset into the ÷ N counter when it reaches the count of zero. N0 is
the least significant and N13 is the most significant. Pull-up resistors ensure that inputs left open remain
at a logic 1 and require only an SPST switch to alter data to the zero state.
T/R
Transmit/Receive Offset Adder Input (Pin 21)
This input controls the offset added to the data provided at the N inputs. This is normally used for offsetting
the VCO frequency by an amount equal to the IF frequency of the transceiver. This offset is fixed at 856
when T/R is low and gives no offset when T/R is high. A pull-up resistor ensures that no connection will
appear as a logic 1 causing no offset addition.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on-chip reference oscillator when connected to terminals of an external parallel
resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to
ground and OSCout to ground. OSCin may also serve as the input for an externally-generated reference
signal. This signal is typically ac coupled to OSCin, but for larger amplitude signals (standard CMOS logic
levels) dc coupling may also be used. In the external reference mode, no connection is required to OSCout.
1.2.2
Output Pins
PDout
Phase Detector A Output (Pin 4)
Three-state output of phase detector for use as loop-error signal. Double-ended outputs are also available
for this purpose (see φV and φR).
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High-Impedance State
φR, φV
Phase Detector B Outputs (Pins 8, 9)
These phase detector outputs can be combined externally for a loop-error signal. A single-ended output is
also available for this purpose (see PDout).
If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by φV
pulsing low. φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by φR
pulsing low. φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both φV and φR remain high except for a small
minimum time period when both pulse low in phase.
MC145151-2 and MC145152-2 Technical Data, Rev. 5
4
Freescale Semiconductor
MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers)
fV
N Counter Output (Pin 10)
This is the buffered output of the ÷ N counter that is internally connected to the phase detector input. With
this output available, the ÷ N counter can be used independently.
LD
Lock Detector Output (Pin 28)
Essentially a high level when loop is locked (fR, fV of same phase and frequency). Pulses low when loop
is out of lock.
1.2.3
Power Supply
VDD
Positive Power Supply (Pin 3)
The positive power supply potential. This pin may range from + 3 to + 9 V with respect to VSS.
VSS
Negative Power Supply (Pin 2)
The most negative supply potential. This pin is usually ground.
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
5
MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers)
1.3
Typical Applications
2.048 MHz
NC
OSCin
OSCout
NC
RA2 RA1
fin
MC145151-2
RA0
VOLTAGE
CONTROLLED
OSCILLATOR
PDout
N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
5 - 5.5 MHz
0 1 1 1 0 0 0 1 0 0 0 = 5 MHz
1 0 1 0 1 1 1 1 1 0 0 = 5.5 MHz
Figure 3. 5 MHz to 5.5 MHz Local Oscillator Channel Spacing = 1 kHz
LOCK DETECT SIGNAL
“1"
OSCout RA2
+V
REF. OSC.
10.0417 MHz
(ON-CHIP OSC.
OPTIONAL)
OSCin
VDD
VSS
“1"
“0"
RA1
RA0
MC145151-2
T/R
LD
fV
PDout
φR
fV
fin
CHOICE OF
DETECTOR
ERROR
SIGNALS
LOOP
FILTER
TRANSMIT
(ADDS 856 TO
÷ N VALUE)
VCO
T: 13.0833 - 18.0833 MHz
R: 9.5167 - 14.5167 MHz
“0" “0" “1"
RECEIVE
TRANSMIT: 440.0 - 470.0 MHz
RECEIVE: 418.6 - 448.6 MHz
(25 kHz STEPS)
CHANNEL PROGRAMMING
÷ N = 2284 TO 3484
X6
T: 73.3333 - 78.3333 MHz
R: 69.7667 - 74.7667 MHz
DOWN
MIXER
X6
60.2500 MHz
NOTES:
1. fR = 4.1667 kHz; ÷ R = 2410; 21.4 MHz low side injection during receive.
2. Frequency values shown are for the 440 - 470 MHz band. Similar implementation applies to the 406 - 440 MHz band.
For 470 - 512 MHz, consider reference oscillator frequency X9 for mixer injection signal (90.3750 MHz).
Figure 4. Synthesizer for Land Mobile Radio UHF Bands
MC145151-2 and MC145152-2 Technical Data, Rev. 5
6
Freescale Semiconductor
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
2
MC145152-2 Parallel-Input (Interfaces with
Dual-Modulus Prescalers)
The MC145152-2 is programmed by sixteen parallel inputs for the N and A counters and three input lines
for the R counter. The device features consist of a reference oscillator, selectable-reference divider,
two-output phase detector, 10-bit programmable divide-by-N counter, and 6-bit programmable
divide-by-A counter.
The MC145152-2 is an improved-performance drop-in replacement for the MC145152-1. Power
consumption has decreased and ESD and latch-up performance have improved.
2.1
•
•
•
•
•
•
•
•
•
Features
Operating Temperature Range: -40 to 85°C
Low Power Consumption Through Use of CMOS Technology
3.0 to 9.0 V Supply Range
On- or Off-Chip Reference Oscillator Operation
Lock Detect Signal
Dual Modulus/Parallel Programming
8 User-Selectable ÷ R Values: 8, 64, 128, 256, 512, 1024, 1160, 2048
÷ N Range = 3 to 1023, ÷ A Range = 0 to 63
Chip Complexity: 8000 FETs or 2000 Equivalent Gates
fin 1
•
28
LD
VSS 2
27
OSCin
VDD 3
26
OSCout
RA0 4
25
A4
RA1 5
24
A3
RA2 6
23
A0
φR 7
22
A2
φV 8
21
A1
20
N9
A5 10
19
N8
N0 11
18 N7
N1 12
17
N2 13
16 N5
N3 14
15
MC 9
N6
N4
Figure 5. MC145152-2 Pin Assignment
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
7
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
RA2
RA1
RA0
OSCout
12 x 8 ROM REFERENCE DECODER
12
LOCK
DETECT
12-BIT ÷ R COUNTER
OSCin
LD
MC
CONTROL
LOGIC
PHASE
DETECTOR
φV
φR
fin
6-BIT ÷ A COUNTER
A5
A3 A2
10-BIT ÷ N COUNTER
A0
N0
N2
N4 N5
N7
N9
NOTE: N0 - N9, A0 - A5, and RA0 - RA2 have pull-up resistors that are not shown.
Figure 6. MC145152-2 Block Diagram
2.2
2.2.1
Pin Descriptions
Input Pins
fin
Frequency Input (Pin 1)
Input to the positive edge triggered ÷ N and ÷ A counters. fin is typically derived from a dual-modulus
prescaler and is AC coupled into the device. For larger amplitude signals (standard CMOS logic levels)
DC coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 4, 5, 6)
These three inputs establish a code defining one of eight possible divide values for the total reference
divider. The total reference divide values are as follows:
Reference Address Code
RA2
RA1
RA0
Total
Divide
Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
64
128
256
512
1024
1160
2048
MC145151-2 and MC145152-2 Technical Data, Rev. 5
8
Freescale Semiconductor
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
N0 - N9
N Counter Programming Inputs (Pins 11 - 20)
The N inputs provide the data that is preset into the ÷ N counter when it reaches the count of 0. N0 is the
least significant digit and N9 is the most significant. Pull-up resistors ensure that inputs left open remain
at a logic 1 and require only a SPST switch to alter data to the zero state.
A0 - A5
A Counter Programming Inputs
(Pins 23, 21, 22, 24, 25, 10)
The A inputs define the number of clock cycles of fin that require a logic 0 on the MC output (see
Section 4.3, “Dual-Modulus Prescaling,” on page 21). The A inputs all have internal pull-up resistors that
ensure that inputs left open will remain at a logic 1.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on-chip reference oscillator when connected to terminals of an external parallel
resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to
ground and OSCout to ground. OSCin may also serve as the input for an externally-generated reference
signal. This signal is typically ac coupled to OSCin, but for larger amplitude signals (standard CMOS logic
levels) dc coupling may also be used. In the external reference mode, no connection is required to OSCout.
2.2.2
Output Pins
φR, φV
Phase Detector B Outputs (Pins 7, 8)
These phase detector outputs can be combined externally for a loop-error signal.
If the frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by
φV pulsing low. φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by φR
pulsing low. φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both φV and φR remain high except for a small
minimum time period when both pulse low in phase.
MC
Dual-Modulus Prescale Control Output (Pin 9)
Signal generated by the on-chip control logic circuitry for controlling an external dual-modulus prescaler.
The MC level will be low at the beginning of a count cycle and will remain low until the ÷ A counter has
counted down from its programmed value. At this time, MC goes high and remains high until the ÷ N
counter has counted the rest of the way down from its programmed value (N - A additional counts since
both ÷ N and ÷ A are counting down during the first portion of the cycle). MC is then set back low, the
counters preset to their respective programmed values, and the above sequence repeated. This provides for
a total programmable divide value (NT) = N • P + A where P and P + 1 represent the dual-modulus prescaler
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
9
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
divide values respectively for high and low MC levels, N the number programmed into the ÷ N counter,
and A the number programmed into the ÷ A counter.
LD
Lock Detector Output (Pin 28)
Essentially a high level when loop is locked (fR, fV of same phase and frequency). Pulses low when loop
is out of lock.
2.2.3
Power Supply
VDD
Positive Power Supply (Pin 3)
The positive power supply potential. This pin may range from + 3 to + 9 V with respect to VSS.
VSS
Negative Power Supply (Pin 2)
The most negative supply potential. This pin is usually ground.
2.3
Typical Applications
NO CONNECTS
“1"
“1"
“1"
R2
OSCout
RA2
RA1
OSCin
RA0
LD
φR
φV
MC145152-2
+V
VDD
MC
VSS
fin
N9
N0 A5
150 - 175 MHz
5 kHz STEPS
LOCK DETECT SIGNAL
10.24 MHz
NOTE 1
C
R1
R1
VCO
+
R2
NOTE 2
C
A0
CHANNEL PROGRAMMING
÷ 64/65 PRESCALER
NOTES:
1. Off-chip oscillator optional.
2. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase-Locked Loop - Low-Pass Filter Design page
for additional information. The φR and φV outputs swing rail-to-rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter.
Figure 7. Synthesizer for Land Mobile Radio VHF Bands
MC145151-2 and MC145152-2 Technical Data, Rev. 5
10
Freescale Semiconductor
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
REF. OSC.
15.360 MHz
(ON-CHIP OSC.
OPTIONAL)
X2
“1"
OSCout
RA2
“1"
“1"
RA1 RA0
MC145152-2
VDD
LD
N0 A5
VCO
+
R1
fin
N9
R1
φV
MC
VSS
RECEIVER FIRST L.O.
825.030 → 844.980 MHz
(30 kHz STEPS)
LOCK DETECT SIGNAL
R2
C
φR
OSCin
+V
RECEIVER 2ND L.O.
30.720 MHz
NO CONNECTS
X4
NOTE 5
NOTE 6
R2
C
A0
TRANSMITTER
MODULATION
X4
NOTE 5
÷ 64/65 PRESCALER
TRANSMITTER SIGNAL
NOTE 5
825.030 → 844.980 MHz
(30 kHz STEPS)
NOTES:
1. Receiver 1st I.F. = 45 MHz, low side injection; Receiver 2nd I.F. = 11.7 MHz, low side injection.
2. Duplex operation with 45 MHz receiver/transmit separation.
3. fR = 7.5 kHz; ÷ R = 2048.
4. Ntotal = N • 64 + A = 27501 to 28166; N = 429 to 440; A = 0 to 63.
5. High frequency prescalers may be used for higher frequency VCO and fref
implementations.
6. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase-Locked Loop - Low-Pass Filter Design page for
additional information. The φR and φV outputs swing rail-to-rail. Therefore, the user should be careful not to exceed the common mode
input range of the op amp used in the combiner/loop filter.
CHANNEL PROGRAMMING
Figure 8. 666-Channel Computer-Controlled, Mobile Radiotelephone Synthesizer
for 800 MHz Cellular Radio Systems
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
11
MC145151-2 and MC145152-2 Electrical Characteristics
3
MC145151-2 and MC145152-2 Electrical Characteristics
These devices contain protection circuitry to protect against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum
rated voltages to these high-impedance circuits. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD except for SW1 and SW2.
SW1 and SW2 can be tied through external resistors to voltages as high as 15 V, independent of the supply
voltage.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD), except
for inputs with pull-up devices. Unused outputs must be left open.
Table 1. Maximum Ratings1
(Voltages Referenced to VSS)
Ratings
Symbol
Value
Unit
VDD
- 0.5 to + 10.0
V
Vin, Vout
- 0.5 to VDD + 0.5
V
Vout
- 0.5 to + 15
V
Input or Output Current (DC or Transient), per Pin
Iin, Iout
± 10
mA
Supply Current, VDD or VSS Pins
IDD, ISS
± 30
mA
Power Dissipation, per Package†
PD
500
mW
Storage Temperature
Tstg
-65 to + 150
°C
TL
260
°C
DC Supply Voltage
Input or Output Voltage (DC or Transient) except SW1, SW2
Output Voltage (DC or Transient),
SW1, SW2 (Rpull-up = 4.7 kΩ)
Lead Temperature, 1 mm from Case for 10 seconds
1
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be
restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.
† Power Dissipation Temperature Derating:
Plastic DIP: - 12 mW/°C from 65 to 85°C
SOG Package: - 7 mW/°C from 65 to 85°C
MC145151-2 and MC145152-2 Technical Data, Rev. 5
12
Freescale Semiconductor
MC145151-2 and MC145152-2 Electrical Characteristics
Table 2. Electrical Characteristics
(Voltages Referenced to VSS)
Symbol
VDD
Parameter
Test Condition
Power Supply Voltage
Range
fin = OSCin = 10 MHz,
1 V p-p ac coupled sine wave
R = 128, A = 32, N = 128
VDD
V
- 40°C
25°C
85°C
Unit
Min
Max
Min
Max
Min
Max
-
3
9
3
9
3
9
V
3
5
9
-
3.5
10
30
-
3
7.5
24
-
3
7.5
24
mA
Iss
Dynamic Supply
Current
ISS
Quiescent Supply
Vin = VDD or VSS
Current (not including Iout = 0 µA
pull-up current
component)
3
5
9
-
800
1200
1600
-
800
1200
1600
-
1600
2400
3200
µA
Vin
Input Voltage - fin,
OSCin
Input ac coupled sine wave
-
500
-
500
-
500
-
mV p-p
VIL
Low-Level Input
Voltage - fin, OSCin
Vout ≥ 2.1 V
Vout ≥ 3.5 V
Vout ≥ 6.3 V
Input dc
coupled
square wave
3
5
9
-
0
0
0
-
0
0
0
-
0
0
0
V
VIH
High-Level Input
Voltage - fin, OSCin
Vout ≤ 0.9 V
Vout ≤ 1.5 V
Vout ≤ 2.7 V
Input dc
coupled
square wave
3
5
9
3.0
5.0
9.0
-
3.0
5.0
9.0
-
3.0
5.0
9.0
-
V
VIL
Low-Level Input
Voltage - except fin,
OSCin
3
5
9
-
0.9
1.5
2.7
-
0.9
1.5
2.7
-
0.9
1.5
2.7
V
VIH
High-Level Input
Voltage - except fin,
OSCin
3
5
9
2.1
3.5
6.3
-
2.1
3.5
6.3
-
2.1
3.5
6.3
-
V
Iin
Input Current
(fin, OSCin)
Vin = VDD or VSS
9
±2
± 50
±2
± 25
±2
± 22
µA
IIL
Input Leakage
Current (Data, CLK,
ENB - without
pull-ups)
Vin = VSS
9
-
- 0.3
-
- 0.1
-
- 1.0
µA
IIH
Input Leakage
Current (all inputs
except fin, OSCin)
Vin = VDD
9
-
0.3
-
0.1
-
1.0
µA
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
13
MC145151-2 and MC145152-2 Electrical Characteristics
Table 3. DC Electrical Characteristics
Symbol
Parameter
Test Condition
- 40°C
25°C
85°C
VDD
V
Min
Max
Min
Max
Min
Max
Unit
IIL
Pull-up Current (all inputs Vin = VSS
with pull-ups)
9
- 20
- 400
- 20
- 200
- 20
- 170
µA
Cin
Input Capacitance
-
-
10
-
10
-
10
pF
VOL
Low-Level Output
Voltage - OSCout
Iout ≈ 0 µA
Vin = VDD
3
5
9
-
0.9
1.5
2.7
-
0.9
1.5
2.7
-
0.9
1.5
2.7
V
VOH
High-Level Output
Voltage - OSCout
Iout ≈ 0 µA
Vin = VSS
3
5
9
2.1
3.5
6.3
-
2.1
3.5
6.3
-
2.1
3.5
6.3
-
V
VOL
Low-Level Output
Voltage - Other Outputs
Iout ≈ 0 µA
3
5
9
-
0.05
0.05
0.05
-
0.05
0.05
0.05
-
0.05
0.05
0.05
V
VOH
High-Level Output
Voltage - Other Outputs
Iout ≈ 0 µA
3
5
9
2.95
4.95
8.95
-
2.95
4.95
8.95
-
2.95
4.95
8.95
-
V
Rpull-up = 4.7 kΩ
-
15
-
15
-
15
-
V
V(BR)DSS Drain-to-Source
Breakdown Voltage SW1, SW2
IOL
Low-Level Sinking
Current - MC
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
3
5
9
1.30
1.90
3.80
-
1.10
1.70
3.30
-
0.66
1.08
2.10
-
mA
IOH
High-Level Sourcing
Current - MC
Vout = 2.7 V
Vout = 4.6 V
Vout = 8.5 V
3
5
9
- 0.60
- 0.90
- 1.50
-
- 0.50
- 0.75
- 1.25
-
- 0.30
- 0.50
- 0.80
-
mA
IOL
Low-Level Sinking
Current - LD
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
3
5
9
0.25
0.64
1.30
-
0.20
0.51
1.00
-
0.15
0.36
0.70
-
mA
IOH
High-Level Sourcing
Current - LD
Vout = 2.7 V
Vout = 4.6 V
Vout = 8.5 V
3
5
9
- 0.25
- 0.64
- 1.30
-
- 0.20
- 0.51
- 1.00
-
- 0.15
- 0.36
- 0.70
-
mA
IOL
Low-Level Sinking
Current - SW1, SW2
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
3
5
9
0.80
1.50
3.50
-
0.48
0.90
2.10
-
0.24
0.45
1.05
-
mA
IOL
Low-Level Sinking
Current - Other Outputs
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
3
5
9
0.44
0.64
1.30
-
0.35
0.51
1.00
-
0.22
0.36
0.70
-
mA
IOH
High-Level Sourcing
Current - Other Outputs
Vout = 2.7 V
Vout = 4.6 V
Vout = 8.5 V
3
5
9
- 0.44
- 0.64
- 1.30
-
- 0.35
- 0.51
- 1.00
-
- 0.22
- 0.36
- 0.70
-
mA
IOZ
Output Leakage Current - Vout = VDD or VSS
PDout
Output in Off State
9
-
± 0.3
-
± 0.1
-
± 1.0
µA
IOZ
Output Leakage Current - Vout = VDD or VSS
SW1, SW2
Output in Off State
9
-
± 0.3
-
± 0.1
-
± 3.0
µA
Cout
Output Capacitance PDout
-
-
10
-
10
-
10
pF
PDout - Three-State
MC145151-2 and MC145152-2 Technical Data, Rev. 5
14
Freescale Semiconductor
MC145151-2 and MC145152-2 Electrical Characteristics
Table 4. AC Electrical Characteristics
(CL = 50 pF, Input tr = tf = 10 ns)
Symbol
tPLH, tPHL
VDD
V
Parameter
Guaranteed Limit Guaranteed Limit
Unit
25°C
-40 to 85°C
Maximum Propagation Delay, fin to MC
(Figure 9a and Figure 9d)
3
5
9
110
60
35
120
70
40
ns
Maximum Propagation Delay, ENB to SW1, SW2
(Figure 9a and Figure 9e)
3
5
9
160
80
50
180
95
60
ns
Output Pulse Width, φR, φV, and LD with fR in Phase with fV
(Figure 9b and Figure 9d)
3
5
9
25 to 200
20 to 100
10 to 70
25 to 260
20 to 125
10 to 80
ns
tTLH
Maximum Output Transition Time, MC
(Figure 9c and Figure 9d)
3
5
9
115
60
40
115
75
60
ns
tTHL
Maximum Output Transition Time, MC
(Figure 9c and Figure 9d)
3
5
9
60
34
30
70
45
38
ns
tTLH, tTHL
Maximum Output Transition Time, LD
(Figure 9c and Figure 9d)
3
5
9
180
90
70
200
120
90
ns
tTLH, tTHL
Maximum Output Transition Time, Other Outputs
(Figure 9c and Figure 9d)
3
5
9
160
80
60
175
100
65
ns
tPHL
tw
VDD
INPUT
50%
- VSS
tPLH
OUTPUT
tPHL
tw
φR, φV, LD*
50%
50%
* fR in phase with fV.
Figure 9a. Maximum Propagation Delay
tTLH
Figure 9b. Output Pulse Width
tTHL
ANY
OUTPUT
90%
10%
Figure 9c. Maximum Output Transition Time
TEST
POINT
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and fixture capacitance.
VDD
15 kΩ
CL*
* Includes all probe and fixture capacitance.
Figure 9d. Test Circuit
Figure 9e. Test Circuit
Figure 9. Switching Waveforms
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
15
MC145151-2 and MC145152-2 Electrical Characteristics
Table 5. Timing Requirements
(Input tr = tf = 10 ns unless otherwise indicated)
Symbol
Parameter
VDD
V
Guaranteed Limit Guaranteed Limit
25°C
- 40 to 85°C
fclk
Serial Data Clock Frequency, Assuming 25% Duty Cycle
NOTE: Refer to CLK tw(H) below
(Figure 10a)
3
5
9
dc to 5.0
dc to 7.1
dc to 10
dc to 3.5
dc to 7.1
dc to 10
MHz
tsu
Minimum Setup Time, Data to CLK
(Figure 10b)
3
5
9
30
20
18
30
20
18
ns
th
Minimum Hold Time, CLK to Data
(Figure 10b)
3
5
9
40
20
15
40
20
15
ns
tsu
Minimum Setup Time, CLK to ENB
(Figure 10b)
3
5
9
70
32
25
70
32
25
ns
trec
Minimum Recovery Time, ENB to CLK
(Figure 10b)
3
5
9
5
10
20
5
10
20
ns
tw(H)
Minimum Pulse Width, CLK and ENB
(Figure 10a)
3
5
9
50
35
25
70
35
25
ns
tr, tf
Maximum Input Rise and Fall Times - Any Input
(Figure 10c)
3
5
9
5
4
2
5
4
2
µs
tw(H)
- VDD
CLK,
ENB
50%
DATA
VSS
tsu
CLK
th
50%
*Assumes 25% Duty Cycle.
Figure 10a. Serial Data Clock
Frequency and Minimum Pulse Width
tt
ANY
OUTPUT
- VDD
50%
VSS
1 *
4 fclk
90%
FIRST
CLK
LAST
CLK
tsu
- VDD
VSS
trec
- VDD
50%
ENB
VSS
PREVIOUS
DATA
LATCHED
tf
10%
Unit
- VDD
VSS
Figure 10b. Minimum Setup, Hold,
and Recovery Times
Figure 10c. Maximum Input Rise and Fall Times
Figure 10. Switching Waveforms
MC145151-2 and MC145152-2 Technical Data, Rev. 5
16
Freescale Semiconductor
MC145151-2 and MC145152-2 Electrical Characteristics
Table 6. Frequency Characteristics
(Voltages References to VSS, CL = 50 pF, Input tr = tf =10 ns unless otherwise indicated)
Symbol
fi
Parameter
Input Frequency
(fin, OSCin)
Test Condition
VDD
V
- 40°C
25°C
85°C
Unit
Min
Max
Min
Max
Min
Max
R ≥ 8, A ≥ 0, N ≥ 8
Vin = 500 mV p-p ac coupled
sine wave
3
5
9
-
6
15
15
-
6
15
15
-
6
15
15
MHz
R ≥ 8, A ≥ 0, N ≥ 8
Vin = 1 V p-p ac coupled
sine wave
3
5
9
-
12
22
25
-
12
20
22
-
7
20
22
MHz
R ≥ 8, A ≥ 0, N ≥ 8
Vin = VDD to VSS dc coupled
square wave
3
5
9
-
13
25
25
-
12
22
25
-
8
22
25
MHz
Note: Usually, the PLL's propagation delay from fin to MC plus the setup time of the prescaler determines the upper frequency
limit of the system. The upper frequency limit is found with the following formula: f = P / (tP + tset) where f is the upper frequency
in Hz, P is the lower of the dual modulus prescaler ratios, tP is the fin to MC propagation delay in seconds, and tset is the prescaler
setup time in seconds. For example, with a 5 V supply, the fin to MC delay is 70 ns. If the MC12028A prescaler is used, the setup
time is 16 ns. Thus, if the 64/65 ratio is utilized, the upper frequency limit is f = P / (tP + tset) = 64/(70 + 16) = 744 MHz.
fR
REFERENCE
OSC ÷ R
VH
VL
VH
fV
FEEDBACK
(fin ÷ N)
*
VL
VH
HIGH IMPEDANCE
PDout
VL
VH
φR
VL
VH
φV
VL
VH
LD
VL
VH = High Voltage Level.
VL = Low Voltage Level.
* At this point, when both fR and fV are in phase, the output is forced to near mid-supply.
NOTE: The PDout generates error pulses during out-of-lock conditions. When locked in phase and frequency the output is high
and the voltage at this pin is determined by the low-pass filter capacitor.
Figure 11. Phase Detector/Lock Detector Output Waveforms
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
17
Design Considerations
4
Design Considerations
4.1
Phase-Locked Loop — Low-Pass Filter Design
A)
PDout
φR -
ωn =
VCO
R1
C
ζ =
φV -
F(s) =
B)
PDout
φR -
VCO
ωn =
R1
R2
φV -
R2
PDout φR
φV
Nωn
2KφKVCO
1
R1sC + 1
KφKVCO
NC(R1 + R2)
ζ = 0.5 ωn
C
F(s) =
C)
KφKVCO
NR1C
R1
_
+A
ωn =
C
VCO
ζ =
R1
(
R 2C +
N
KφKVCO
)
R2sC + 1
(R1 + R2)sC + 1
KφKVCO
NCR1
ωnR2C
2
R2
Assuming gain A is very large, then:
C
F(s) =
R2sC + 1
R1sC
NOTE: Sometimes R1 is split into two series resistors, each R1 ÷ 2. A capacitor CC is then placed from the midpoint to ground to further
filter φV and φR. The value of CC should be such that the corner frequency of this network does not significantly affect ωn.
The φR and φV outputs swing rail-to-rail. Therefore, the user should be careful not to exceed the common mode input range of the
op amp used in the combiner/loop filter.
Definitions:
N = Total Division Ratio in feedback loop
Kφ (Phase Detector Gain) = VDD/4π for PDout
Kφ (Phase Detector Gain) = VDD/2π for φV and φR
KVCO (VCO Gain) =
2π∆fVCO
∆VVCO
for a typical design wn (Natural Frequency) ≈ 2πfr (at phase detector input).
10
Damping Factor: ζ ≅ 1
Figure 12. Phase-Locked Loop — Low-Pass Filter Design
MC145151-2 and MC145152-2 Technical Data, Rev. 5
18
Freescale Semiconductor
Design Considerations
4.2
Crystal Oscillator Considerations
The following options may be considered to provide a reference frequency to Freescale's CMOS frequency
synthesizers.
4.2.1
Use of a Hybrid Crystal Oscillator
Commercially available temperature-compensated crystal oscillators (TCXOs) or crystal-controlled data
clock oscillators provide very stable reference frequencies. An oscillator capable of sinking and sourcing
50 µA at CMOS logic levels may be direct or dc coupled to OSCin. In general, the highest frequency
capability is obtained utilizing a direct-coupled square wave having a rail-to-rail (VDD to VSS) voltage
swing. If the oscillator does not have CMOS logic levels on the outputs, capacitive or ac coupling to OSCin
may be used. OSCout, an unbuffered output, should be left floating.
4.2.2
Design an Off-Chip Reference
The user may design an off-chip crystal oscillator using ICs specifically developed for crystal oscillator
applications, or using discrete transistors. The reference signal from the oscillator is ac coupled to OSCin.
For large amplitude signals (standard CMOS logic levels), dc coupling is used. OSCout, an unbuffered
output, should be left floating. In general, the highest frequency capability is obtained with a
direct-coupled square wave having rail-to-rail voltage swing.
4.2.3
Use of the On-Chip Oscillator Circuitry
The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a
reference source frequency. A fundamental mode crystal, parallel resonant at the desired operating
frequency, should be connected as shown in Figure 13.
FREQUENCY
SYNTHESIZER
Rf
OSCin
C1
R1*
OSCout
C2
* May be deleted in certain cases. See text.
Figure 13. Pierce Crystal Oscillator Circuit
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
19
Design Considerations
For VDD = 5.0 V, the crystal should be specified for a loading capacitance, CL, which does not exceed
32 pF for frequencies to approximately 8.0 MHz, 20 pF for frequencies in the area of 8.0 to 15 MHz, and
10 pF for higher frequencies. These are guidelines that provide a reasonable compromise between IC
capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across the crystal can be estimated to be:
CL =
CinCout
+ Ca + Co +
Cin + Cout
C1 • C2
C1 + C2
where
Cin
Cout
Ca
CO
=
=
=
=
5 pF (see Figure 14)
6 pF (see Figure 14)
1 pF (see Figure 14)
the crystal's holder capacitance (see Figure 15)
C1 and C2 = external capacitors (see Figure 13)
Ca
Cin
Cout
Figure 14. Parasitic Capacitances of the Amplifier
RS
1
2
LS
CS
1
2
CO
1
Re
Xe
2
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
Figure 15. Equivalent Crystal Networks
The oscillator can be “trimmed” on-frequency by making a portion or all of C1 variable. The crystal and
associated components must be located as close as possible to the OSCin and OSCout pins to minimize
distortion, stray capacitance, stray inductance, and startup stabilization time. In some cases, stray
capacitance should be added to the value for Cin and Cout.
Power is dissipated in the effective series resistance of the crystal, Re, in Figure 15. The drive level
specified by the crystal manufacturer is the maximum stress that a crystal can withstand without damage
or excessive shift in frequency. R1 in Figure 13 limits the drive level. The use of R1 may not be necessary
in some cases (i.e., R1 = 0 Ω).
MC145151-2 and MC145152-2 Technical Data, Rev. 5
20
Freescale Semiconductor
Design Considerations
To verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency
as a function of voltage at OSCout. (Care should be taken to minimize loading.) The frequency should
increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in
frequency or become unstable with an increase in supply voltage. The operating supply voltage must be
reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can
prove very helpful.
4.3
4.3.1
Dual-Modulus Prescaling
Overview
The technique of dual-modulus prescaling is well established as a method of achieving high performance
frequency synthesizer operation at high frequencies. Basically, the approach allows relatively
low-frequency programmable counters to be used as high-frequency programmable counters with speed
capability of several hundred MHz. This is possible without the sacrifice in system resolution and
performance that results if a fixed (single-modulus) divider is used for the prescaler.
In dual-modulus prescaling, the lower speed counters must be uniquely configured. Special control logic
is necessary to select the divide value P or P + 1 in the prescaler for the required amount of time (see
modulus control definition).
4.3.2
Design Guidelines
The system total divide value, Ntotal (NT) will be dictated by the application:
NT =
frequency into the prescaler
=N•P+A
frequency into the phase detector
N is the number programmed into the ÷ N counter, A is the number programmed into the ÷ A counter, P
and P + 1 are the two selectable divide ratios available in the dual-modulus prescalers. To have a range of
NT values in sequence, the ÷ A counter is programmed from zero through P - 1 for a particular value N in
the ÷ N counter. N is then incremented to N + 1 and the ÷ A is sequenced from 0 through P - 1 again.
There are minimum and maximum values that can be achieved for NT. These values are a function of P
and the size of the ÷ N and ÷ A counters.
The constraint N ≥ A always applies. If Amax = P - 1, then Nmin ≥ P - 1. Then NTmin = (P - 1) P + A or
(P - 1) P since A is free to assume the value of 0.
NTmax = Nmax • P + Amax
To maximize system frequency capability, the dual-modulus prescaler output must go from low to high
after each group of P or P + 1 input cycles. The prescaler should divide by P when its modulus control line
is high and by P + 1 when its MC is low.
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
21
Design Considerations
For the maximum frequency into the prescaler (fVCOmax), the value used for P must be large enough such
that:
1. fVCOmax divided by P may not exceed the frequency capability of fin (input to the ÷ N and ÷ A
counters).
2. The period of fVCO divided by P must be greater than the sum of the times:
a) Propagation delay through the dual-modulus prescaler.
b) Prescaler setup or release time relative to its MC signal.
c) Propagation time from fin to the MC output for the frequency synthesizer device.
A sometimes useful simplification in the programming code can be achieved by choosing the values for P
of 8, 16, 32, or 64. For these cases, the desired value of NT results when NT in binary is used as the program
code to the ÷ N and ÷ A counters treated in the following manner:
1. Assume the ÷ A counter contains “a” bits where 2a ≥ P.
2. Always program all higher order ÷ A counter bits above “a” to 0.
3. Assume the ÷ N counter and the ÷ A counter (with all the higher order bits above “a” ignored)
combined into a single binary counter of n + a bits in length (n = number of divider stages in the
÷ N counter). The MSB of this “hypothetical” counter is to correspond to the MSB of ÷ N and the
LSB is to correspond to the LSB of ÷ A. The system divide value, NT, now results when the value
of NT in binary is used to program the “new” n + a bit counter.
By using the two devices, several dual-modulus values are achievable.
MC145151-2 and MC145152-2 Technical Data, Rev. 5
22
Freescale Semiconductor
Package Dimensions
5
Package Dimensions
P SUFFIX
PLASTIC DIP
28
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
4. CONTROLLING DIMENSION: INCH.
15
B
A
H
F
M
K
D
G
L
C
N
INCHES
MIN
MAX
1.435
1.465
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.085
0.008
0.015
0.115
0.135
0.600 BSC
0˚
15˚
0.020
0.040
DIM
A
B
C
D
F
G
H
J
K
L
M
N
14
1
J
SEATING
PLANE
MILLIMETERS
MIN
MAX
36.45
37.21
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
0˚
15˚
0.51
1.02
Figure 16. Outline Dimensions for Plastic DIP
(Case Outline 710-02, Issue B)
DW SUFFIX
SOG PACKAGE
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.
4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
15
0.25
E
H
M
B
M
28
1
14
B
A
PIN 1 IDENT
A1
L
0.10
e
C
B
C
0.025
M
C A
S
B
SEATING
PLANE
θ
DIM
A
A1
B
C
D
E
e
H
L
θ
MILLIMETERS
MIN
MAX
2.35
2.65
0.13
0.29
0.35
0.49
0.23
0.32
17.80
18.05
7.40
7.60
1.27 BSC
10.05
10.55
0.41
0.90
0˚
8˚
S
Figure 17. Outline Dimensions for SOG Package
(Case Outline 751F-05, Issue F)
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
23
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
[email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
[email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
[email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
[email protected]
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
[email protected]
RoHS-compliant and/or Pb- free versions of Freescale products have the functionality
and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
For information on Freescale.s Environmental Products program, go to
http://www.freescale.com/epp.
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
MC145151-2/D
Rev. 5
12/2004
/
Similar pages