NSC DS92LV090A 9 channel bus lvds transceiver Datasheet

DS92LV090A
9 Channel Bus LVDS Transceiver
General Description
Features
The DS92LV090A is one in a series of Bus LVDS transceivers
designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from
a single 3.3V power supply and includes nine differential line
drivers and nine receivers. To minimize bus loading, the driver
outputs and receiver inputs are internally connected. The
separate I/O of the logic side allows for loop back support.
The device also features a flow through pin out which allows
easy PCB routing for short stubs between its pins and the
connector.
The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high
speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides
common mode noise rejection of ±1V.
The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to
standard (TTL/CMOS) levels. (See Applications Information
Section for more details.)
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Bus LVDS Signaling
3.2 nanosecond propagation delay max
Chip to Chip skew ±800ps
Low power CMOS design
High Signaling Rate Capability (above 100 Mbps)
0.1V to 2.3V Common Mode Range for VID = 200mV
±100 mV Receiver Sensitivity
Supports open and terminated failsafe on port pins
3.3V operation
Glitch free power up/down (Driver & Receiver disabled)
Light Bus Loading (5 pF typical) per Bus LVDS load
Designed for Double Termination Applications
Balanced Output Impedance
Product offered in 64 pin TQFP package
High impedance Bus pins on power off (VCC = 0V)
Driver Channel to Channel skew (same device) 230ps
typical
■ Receiver Channel to Channel skew (same device) 370ps
typical
Simplified Functional Diagram
10011101
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation
100111
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DS92LV090A 9 Channel Bus LVDS Transceiver
December 14, 2007
DS92LV090A
Connection Diagram
10011102
Top View
Order Number DS92LV090ATVEH
See NS Package Number VEH064DB
Pin Descriptions
Pin Name
Pin #
Input/Output
DO+/RI+
27, 31, 35, 37, 41, 45,
47, 51, 55
I/O
True Bus LVDS Driver Outputs and Receiver Inputs.
DO−/RI−
26, 30, 34, 36, 40, 44,
46, 50, 54
I/O
Complimentary Bus LVDS Driver Outputs and Receiver Inputs.
DIN
2, 6, 12, 18, 20, 22, 58,
60, 62
I
TTL Driver Input.
RO
3, 7, 13, 19, 21, 23, 59,
61, 63
O
TTL Receiver Output.
RE
17
I
Receiver Enable TTL Input (Active Low).
DE
16
I
Driver Enable TTL Input (Active High).
GND
4, 5, 9, 14, 25, 56
Power
Ground for digital circuitry (must connect to GND on PC board). These pins
connected internally.
VCC
10, 15, 24, 57, 64
Power
VCC for digital circuitry (must connect to VCC on PC board). These pins
connected internally.
AGND
28, 33, 43, 49, 53
Power
Ground for analog circuitry (must connect to GND on PC board). These pins
connected internally.
AVCC
29, 32, 42, 48, 52
Power
Analog VCC (must connect to VCC on PC board). These pins connected
internally.
NC
1, 8, 11, 38, 39
N/A
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Descriptions
Leave open circuit, do not connect.
2
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
Enable Input Voltage
(DE, RE)
Driver Input Voltage (DIN)
Receiver Output Voltage
(ROUT)
Bus Pin Voltage (DO/RI±)
4.0V
260°C
Recommended Operating
Conditions
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to +3.9V
Supply Voltage (VCC)
Receiver Input Voltage
Operating Free Air Temperature
Maximum Input Edge Rate
ESD (HBM 1.5 kΩ, 100 pF)
>4.5 kV
Driver Short Circuit Duration
momentary
Receiver Short Circuit Duration
momentary
Maximum Package Power Dissipation at 25°C
TQFP
1.74 W
Derate TQFP Package
13.9 mW/°C
θja
10.9°C/W
+150°C
−65°C to +150°C
Min
3.0
0.0
−40
(Note 6)(20% to 80%)
Data
Control
Max
3.6
2.4
+85
Units
V
V
°C
1.0
3.0
Δt/ΔV
ns/V
ns/V
71.7°C/W
DC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3)
Symbol
Parameter
Conditions
Pin
RL = 27Ω, Figure 1
VOD
Output Differential Voltage
ΔVOD
VOD Magnitude Change
VOS
Offset Voltage
ΔVOS
Offset Magnitude Change
VOH
Driver Output High Voltage
RL = 27Ω
VOL
Driver Output Low Voltage
RL = 27Ω
IOSD
Output Short Circuit Current VOD = 0V, DE = VCC, Driver outputs
(Note 10)
shorted together
VOH
Voltage Output High (Note
11)
VID = +300 mV
DO+/RI+,
DO−/RI−
Min
Typ
Max
Units
240
300
460
mV
27
mV
1.1
1.3
1.5
V
5
10
mV
1.4
1.65
V
0.95
IOH = −400 µA
1.1
|36|
|65|
mA
VCC−0.2
V
Inputs Open
VCC−0.2
V
Inputs Terminated,
RL = 27Ω
VCC−0.2
V
VOL
Voltage Output Low
IOL = 2.0 mA, VID = −300 mV
IOD
Receiver Output Dynamic
Current (Note 10)
VID = 300mV, VOUT = VCC−1.0V
VTH
Input Threshold High
DE = 0V, VCM = 1.5V
VTL
Input Threshold Low
VCMR
Receiver Common Mode
Range
IIN
Input Current
VIH
Minimum Input High Voltage
VIL
Maximum Input Low Voltage
IIH
Input High Current
VIN = VCC or 2.4V
IIL
Input Low Current
VIN = GND or 0.4V
VCL
Input Diode Clamp Voltage
ICLAMP = −18 mA
ROUT
V
0.05
−110
VID = −300mV, VOUT = 1.0V
|75|
DO+/RI+,
DO−/RI−
VCC = 0V, VIN = +2.4V or 0V
DIN, DE, RE
110
mA
+100
mV
mV
−20
±1
−20
±1
2.0
GND
2.4 − |
VID|/2
V
+20
µA
+20
µA
VCC
V
0.8
V
±10
+20
µA
−20
±10
+20
µA
−1.5
−0.8
−20
3
V
mA
−100
|VID|/2
DE = 0V, RE = 2.4V,
VIN = +2.4V or 0V
0.075
|75|
V
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DS92LV090A
θjc
Junction Temperature
Storage Temperature Range
Lead Temperature
(Soldering, 4 sec.)
Absolute Maximum Ratings (Notes 1, 2)
DS92LV090A
Symbol
ICCD
ICCR
ICCZ
ICC
IOFF
Parameter
Typ
Max
Units
55
80
mA
Power Supply Current
DE = RE = 0V, VID = ±300mV
Drivers Disabled, Receivers
Enabled
73
80
mA
Power Supply Current,
Drivers and Receivers TRISTATE®
DE = 0V; RE = VCC,
DIN = VCC or GND
35
80
mA
Power Supply Current,
Drivers and Receivers
Enabled
DE = VCC; RE = 0V,
DIN = VCC or GND,
170
210
mA
Power Off Leakage Current
VCC = 0V or OPEN,
DIN, DE, RE = 0V or OPEN,
VAPPLIED = 3.6V (Port Pins)
+20
µA
Power Supply Current
Drivers Enabled, Receivers
Disabled
Conditions
Pin
No Load, DE = RE = VCC,
DIN = VCC or GND
Min
VCC
RL = 27Ω
DO+/RI+,
DO−/RI−
−20
COUTPUT Capacitance @ Bus Pins
DO+/RI+,
DO−/RI−
5
pF
cOUTPUT
ROUT
7
pF
Capacitance @ ROUT
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4
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.6
1.4
2.2
ns
0.6
1.4
2.2
ns
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
tPHLD
Differential Prop. Delay High to Low (Note 8)
tPLHD
Differential Prop. Delay Low to High (Note 8)
tSKD1
Differential Skew |tPHLD–tPLHD| (Note 9)
tSKD2
Chip to Chip Skew (Note 12)
tSKD3
Channel to Channel Skew (Note 13)
tTLH
Transition Time Low to High
tTHL
Transition Time High to Low
tPHZ
Disable Time High to Z
tPLZ
Disable Time Low to Z
tPZH
Enable Time Z to High
tPZL
Enable Time Z to Low
RL = 27Ω,
Figures 2, 3,
CL = 10 pF
80
ps
1.6
ns
0.25
0.45
ns
0.6
1.2
ns
0.5
1.2
ns
3
8
ns
3
8
ns
3
8
ns
3
8
ns
1.6
2.4
3.2
ns
1.6
2.4
3.2
ns
RL = 27Ω,
Figures 4, 5,
CL = 10 pF
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
tPHLD
Differential Prop. Delay High to Low (Note 8)
Figures 6, 7,
CL = 35 pF
tPLHD
Differential Prop Delay Low to High (Note 8)
tSDK1
Differential Skew |tPHLD–tPLHD| (Note 9)
tSDK2
Chip to Chip Skew (Note 12)
1.6
ns
tSDK3
Channel to Channel Skew (Note 13)
0.35
0.60
ns
tTLH
Transition Time Low to High
1.5
2.5
ns
tTHL
Transition Time High to Low
1.5
2.5
ns
tPHZ
Disable Time High to Z
4.5
10
ns
tPLZ
Disable Time Low to Z
3.5
8
ns
tPZH
Enable Time Z to High
3.5
8
ns
tPZL
Enable Time Z to Low
3.5
8
ns
80
RL = 500Ω,
Figures 8, 9,
CL = 35 pF
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified
except VOD, ΔVOD and VID.
Note 3: All typicals are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) > 4.5 kV EIAJ (0Ω, 200 pF) > 300V.
Note 5: CL includes probe and fixture capacitance.
Note 6: Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr, tf = <1.0 ns (0%–100%). To ensure fastest propagation delay and
minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge
rate, the better the AC performance.
Note 7: The DS92LV090A functions within datasheet specification when a resistive load is applied to the driver outputs.
Note 8: Propagation delays are guaranteed by design and characterization.
Note 9: tSKD1 |tPHLD–tPLHD| is the worse case skew between any channel and any device over recommended operation conditions.
Note 10: Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity.
Note 11: VOH failsafe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied.
Note 12: Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
Note 13: Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, either edge.
5
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DS92LV090A
AC Electrical Characteristics
DS92LV090A
TABLE 1. Functional Table
Applications Information
General application guidelines and hints may be found in the
following application notes: AN-808, AN-903, AN-971,
AN-977, and AN-1108.
There are a few common practices which should be implied
when designing PCB for Bus LVDS signaling. Recommended
practices are:
• Use at least 4 PCB board layer (Bus LVDS signals,
ground, power and TTL signals).
• Keep drivers and receivers as close to the (Bus LVDS port
side) connector as possible.
• Bypass each Bus LVDS device and also use distributed
bulk capacitance between power planes. Surface mount
capacitors placed close to power and ground pins work
best. Two or three high frequency, multi-layer ceramic
(MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel
should be used between each VCC and ground. The
capacitors should be as close as possible to the VCC pin.
Multiple vias should be used to connect VCC and Ground
planes to the pads of the by-pass capacitors.
In addition, randomly distributed by-pass capacitors
should be used.
• Use the termination resistor which best matches the
differential impedance of your transmission line.
• Leave unused Bus LVDS receiver inputs open (floating).
Limit traces on unused inputs to <0.5 inches.
• Isolate TTL signals from Bus LVDS signals
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
• Use controlled impedance media. The backplane and
connectors should have a matched differential
impedance.
MODE SELECTED
DE
RE
H
DRIVER MODE
H
RECEIVER MODE
L
L
TRI-STATE MODE
L
H
LOOP BACK MODE
H
L
TABLE 2. Transmitter Mode
INPUTS
DE
OUTPUTS
DIN
DO−
H
H
L
L
H
H
H
L
H
0.8V< DIN <2.0V
X
X
L
X
Z
Z
TABLE 3. Receiver Mode
INPUTS
OUTPUT
RE
(RI+) – (RI−)
L
L (< −100 mV)
L
L
H (> +100 mV)
H
L
−100 mV < VID < +100 mV
X
H
X
Z
X = High or Low logic state
L = Low state
Z = High impedance state
H = High state
Test Circuits and Timing Waveforms
10011103
FIGURE 1. Differential Driver DC Test Circuit
10011104
FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit
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DO+
6
DS92LV090A
10011105
FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms
10011106
FIGURE 4. Driver TRI-STATE Delay Test Circuit
10011107
FIGURE 5. Driver TRI-STATE Delay Waveforms
7
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DS92LV090A
10011108
FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit
10011109
FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms
10011110
FIGURE 8. Receiver TRI-STATE Delay Test Circuit
10011111
FIGURE 9. Receiver TRI-STATE Delay Waveforms
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8
DS92LV090A
Typical Bus Application Configurations
10011112
Bi-Directional Half-Duplex Point-to-Point Applications
10011113
Multi-Point Bus Applications
9
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DS92LV090A
Physical Dimensions inches (millimeters) unless otherwise noted
64-Lead Molded TQFP Package
Order Number DS92LV090ATVEH
NS Package Number VEH064DB
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10
DS92LV090A
Notes
11
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DS92LV090A 9 Channel Bus LVDS Transceiver
Notes
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