TI ONET2501PARGTR 155-mbps to 2.5-gbps limiting amplifier Datasheet

features
D Multi-Rate Operation from 155 Mbps Up to
D
D
D
D
D
D
D
D
2.5 Gbps
Low Power Consumption
Input Offset Cancellation
High Input Dynamic Range
Output Disable
Output Polarity Select
CML Data Outputs
Receive Signals Strength Indicator (RSSI)
Loss of Signal Detection
SLLS602A − MARCH 2004 − REVISED JULY 2004
D Single 3.3-V Supply
D Surface Mount Small Footprint 3 mm ×
3 mm 16-Pin QFN Package
applications
D SONET/SDH Transmission Systems at OC3,
D
D
OC12, OC24, OC48
1.0625-Gbps and 2.125-Gbps Fibre Channel
Receivers
Gigabit Ethernet Receivers
description
The ONET2501PA is a versatile high-speed limiting amplifier for multiple fiber optic applications with data rates
up to 2.5 Gbps.
This device provides a gain of about 50 dB, which ensures a fully differential output swing for input signals as
low as 3 mVp−p.
The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal
swings as high as 1200 mVp−p.
The ONET2501PA is available in a small footprint 3 mm × 3 mm 16-pin QFN package. The circuit requires a
single 3.3-V supply.
This power efficient limiting amplifier is characterized for operation from –40°C to 85°C
available options
TA
−40°C to 85°C
PACKAGED DEVICE
ONET2501PARGT
FEATURES
2.5-Gbps limiting amplifier with LOS and RSSI
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLLS602A − MARCH 2004 − REVISED JULY 2004
block diagram
A simplified block diagram of the ONET2501PA is shown in Figure 1.
These compact, low power 2.5-Gbps limiting amplifiers consist of a high-speed data path with offset cancellation
block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation
block.
The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below.
COC2 COC1
VCC
Offset
Cancellation
GND
OUTPOL
VCCO
DIN+
DIN−
+
−
Input Buffer
+
+
+
Gain Stage
Gain Stage
+
DOUT+
−
DOUT−
Gain Stage
CML
Output
Buffer
DISABLE
Bandgap Voltage
Reference and
Bias Current
Generation
Loss of Signal
and
RSSI Detection
LOS
RSSI
TH
Figure 1. Block Diagram
high-speed data path
The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data
path consists of the input stage with 2 × 50-Ω on-chip line termination to VCC, three gain stages, which provide
the required typical gain of about 50 dB, and a CML output stage. The amplified data output signal is available
at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCCO. The output stage also
includes a data polarity switching function, which is controlled by the OUTPOL input, and a disable function,
controlled by the signal applied to the DISABLE input pin.
An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even
for very small input data signals.
The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor.
For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be
connected to the COC1/COC2 pins.
los of signal and RSSI detection
The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block
a signal is generated, which is linear proportional to the input amplitude over a wide input voltage range. This
signal is available at the RSSI output pin.
Furthermore, this circuit block compares the input signal to a threshold, which can be programmed by means
of an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of
signal is indicated at the LOS pin.
2
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• DALLAS, TEXAS 75265
SLLS602A − MARCH 2004 − REVISED JULY 2004
bandgap voltage and bias generation
The ONET2501PA limiting amplifier is supplied by a single 3.3-V ±10% supply voltage connected to the VCC
and VCCO pins. This voltage is referred to ground (GND).
An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other
internally required voltages and bias currents are derived.
package
RSSI
COC1
COC2
GND
For the ONET2501PA a small footprint 3 mm × 3 mm 16-pin QFN Package is used, with a lead pitch of 0,5 mm.
The pinout is shown in Figure 2.
VCC
VCCO
DIN+
DOUT+
DIN−
VCC
DOUT−
GND
DISABLE
LOS
TH
OUTPOL
Figure 2. Pinout of ONET2501PA in a 3 mm y 3 mm 16-Pin QFN Package
terminal functions
The following table shows a pin description for the ONET2501PA in a 3 mm x 3 mm 16-pin QFN package.
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
3.3-V ±10% supply voltage
VCC
1, 4
Supply
DIN+
2
Analog in
Noninverted data input. On-chip 50-Ω terminated to VCC.
DIN–
3
Analog in
Inverted data input. On-chip 50-Ω terminated to VCC.
TH
5
Analog in
LOS threshold adjustment with resistor to GND.
DISABLE
6
CMOS in
Disables CML output stage when set to high level.
LOS
7
CMOS out
GND
8, 16, EP
Supply
OUTPOL
9
CMOS in
Output data signal polarity select (internally pulled up): Setting to high level or leaving pin open selects
normal polarity. Low level selects inverted polarity.
High level indicates that the input signal amplitude is below the programmed threshold level.
Circuit ground. Exposed die pad (EP) must be grounded.
DOUT–
10
CML out
Inverted data output. On-chip 50-Ω back-terminated to VCCO
DOUT+
11
CML out
Noninverted data output. On-chip 50-Ω back-terminated to VCCO
VCCO
12
Supply
RSSI
13
Analog out
COC1
14
Analog
Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin
and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
COC2
15
Analog
Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin
and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
3.3-V ±10% supply voltage for output stage
Analog output voltage proportional to the input data amplitude. Indicates the strength of the received
signal (RSSI).
POST OFFICE BOX 655303
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3
SLLS602A − MARCH 2004 − REVISED JULY 2004
absolute maximum ratings
over operating free-air temperature range unless otherwise noted†
VALUE
UNIT
–0.3 to 4
V
0.5 to 4
V
–0.3 to 4
V
±1
V
VCC, VCCO
VDIN+, VDIN−
Supply voltage, See Note 1
VTH,VDISABLE,VLOS,VOUTPOL,VDOUT+,
VDOUT−, VRSSI, VCOC1, VCOC2+
Voltage at TH, DISABLE, LOS, OUTPOL, DOUT+, DOUT–, RSSI,
COC1, and COC2, See Note 1
VCOC,DIFF
VDIN,DIFF
Differential voltage between COC1 and COC2
ILOS
IDIN+, IDIN−, IDOUT+, IDOUT–
Current into LOS
ESD
ESD rating at all pins
TJ(max)
Tstg
Maximum junction temperature
Storage temperature range
TA
TL
Characterized free-air operating temperature range
−40 to 85
°C
260
°C
Voltage at DIN+, DIN–, See Note 1
Differential voltage between DIN+ and DIN–
Continuous current at inputs and outputs
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
±2.5
V
–1 to 9
mA
–25 to 25
mA
3
kV (HBM)
125
°C
−65 to 85
°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
recommended operating conditions
Supply voltage, VCC, VCCO
Operating free-air temperature, TA
MIN
TYP
MAX
3
3.3
3.6
V
85
°C
−40
UNIT
dc electrical characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC,VCCO
ICC
Supply voltage
VOD
Differential data output voltage swing
rIN, rOUT
Data input/output resistance
MIN
3
Supply current
DISABLE = low (excludes CML output current)
DISABLE = high
V(IN_MIN)
V(IN_MAX)
DISABLE = low
600
Single ended
TYP
3.6
V
32
40
mA
0.25
10
780
1200
mVp−p
mVp−p
100
RSSI output voltage
Input = 80 mVp−p, RRSSI ≥ 10 kΩ
2800
RSSI linearity
20−dB input signal, VIN ≤ 60 mVpp
BER < 10–10
±3%
±8%
3
5
Data input overload
2.1
LOS hysteresis
LOS assert threshold range
223−1 PRBS (at 2.5 Gbps and 155 Mbps)
Power supply noise rejection
f < 2 MHz
LOS low voltage
POST OFFICE BOX 655303
2.4
• DALLAS, TEXAS 75265
4.5
2−40
26
V
V
0.8
2.5
mVp−p
mVp−p
V
0.6
ISOURCE = –30 µA
ISINK = 1 mA
223−1 PRBS (at 2.5 Gbps and 155 Mbps)
LOS high voltage
mV
1200
CMOS input low voltage
4
Ω
Input = 2 mVp−p, RRSSI ≥ 10 kΩ
Data input sensitivity
UNIT
3.3
50
CMOS input high voltage
VTH
PSNR
MAX
V
dB
mVp−p
dB
SLLS602A − MARCH 2004 − REVISED JULY 2004
ac electrical characteristics
over recommended operating conditions (unless otherwise noted) typical operating condition is at VCC = 3.3 V and
TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
COC = open
COC = 2.2 nF
Low frequency −3-dB bandwidth
DJ
MAX
45
kHz
2.5
Gb/s
Input referred noise
300
Deterministic jitter, See Note 2
UNIT
70
0.8
Data rate
vNI
TYP
K28.5 pattern at 2.5 Gbps
223−1 PRBS equivalent pattern at 2.5 Gbps
8.5
25
9.3
30
223−1 PRBS equivalent pattern at 155 Mbps
25
50
Input = 5 mVpp
6.5
µVRMS
psp−p
RJ
Random jitter
tr
tf
Output rise time
20% to 80%
60
85
ps
Output fall time
20% to 80%
60
85
ps
tDIS
tLOS
Disable response time
100
µs
Input = 10 mVpp
psRMS
3
20
LOS assert/deassert time
2
ns
NOTE 2: Deterministic jitter does not include pulse-width distortion due to residual small output offset voltage.
APPLICATION INFORMATION
Figure 3 shows the ONET2501PA connected with an ac-coupled interface to the data signal source as well as
to the output load.
Besides the ac-coupling capacitors C1 through C4 in the input and output data signal lines, the only required
external component is the LOS threshold setting resistor RTH. In addition, an optional external filter capacitor
(COC) may be used if a low cutoff frequency is desired.
RSSI
RSSI
COC1
GND
COC2
COC
Optional
VCC
DIN+
DIN−
ONET2501PA DOUT+
16 Pin QFN
DOUT−
TH
VCC
OUTPOL
VCC
C3
C4
DOUT+
DOUT−
OUTPOL
GND
C2
LOS
DIN−
VCCO
DISABLE
DIN+
C1
DISABLE
LOS
RTH
Figure 3. Basic Application Circuit With AC-Coupled I/Os
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ONET2501PARGT
ACTIVE
QFN
RGT
16
121
TBD
CU NIPDAU
Level-2-220C-1 YEAR
ONET2501PARGTR
ACTIVE
QFN
RGT
16
3000
TBD
CU NIPDAU
Level-2-220C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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