Cypress CY7C141-35JC 1k x 8 dual-port static ram Datasheet

fax id: 5200
1CY 7C14 0
CY7C130/CY7C131
CY7C140/CY7C141
1K x 8 Dual-Port Static Ram
Features
Functional Description
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• 1K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 90 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Master CY7C130/CY7C131 easily expands data bus
width to 16 or more bits using slave CY7C140/CY7C141
• BUSY output flag on CY7C130/CY7C131; BUSY input
on CY7C140/CY7C141
• INT flag for port-to-port communication
• Available in 48-pin DIP (CY7C130/140), 52-pin PLCC and
52-pin TQFP
• Pin-compatible and functionally equivalent to
IDT7130/IDT7140
The CY7C130/CY7C131/CY7C140 and CY7C141 are
high-speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/ CY7C131 can be utilized as either a
standalone 8-bit dual-port static RAM or as a master dual-port
RAM in conjunction with the CY7C140/CY7C141 slave dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). Two flags are
provided on each port, BUSY and INT. BUSY signals that the
port is trying to access the same location currently being accessed by the other port. INT is an interrupt flag indicating that
data has been placed in a unique location (3FF for the left port
and 3FE for the right port). An automatic power-down feature
is controlled independently on each port by the chip enable
(CE) pins.
The CY7C130 and CY7C140 are available in 48-pin DIP. The
CY7C131 and CY7C141 are available in 52-pin PLCC and
PQFP.
Logic Block Diagram
Pin Configurations
R/WL
CEL
R/WR
CER
OEL
OER
I/O7L
I/O
CONTROL
I/O0L
[1]
BUSYL
A 9L
A 0L
DIP
Top View
I/O7R
I/O
CONTROL
I/O0R
BUSYR
MEMORY
ARRAY
ADDRESS
DECODER
CEL
OEL
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
R/WL
A 9R
ADDRESS
DECODER
A 0R
CER
OER
R/WR
[2]
INTL
INTR
[2]
CE L
R/W L
BUSY L
INTL
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
12 7C130 37
13 7C140 36
14
35
15
34
16
33
17
32
18
31
30
19
20
29
28
21
22
27
23
26
24
25
VCC
CER
R/WR
BUSYR
INTR
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
C130-2
C130-1
Notes:
1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor
CY7C140/CY7C141 (Slave): BUSY is input.
2. Open drain outputs: pull-up resistor required
s
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
May 1989 – Revised March 27, 1997
CY7C130/CY7C131
CY7C140/CY7C141
Pin Configuration (continued)
PLCC
Top View
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
8
9
10
11
12
13
14
15
16
17
18
19
20
PQFP
Top View
7 6 5 4 3 2 1 52 51 50 49 48 47
46
45
44
43
42
41
7C131
40
7C141
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
OER
A0R
A1R
A2R
A3R
A4R
A5R
52 5150 49 48 47 4645 44 43 42 41 40
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
A6R
A7R
A8R
A9R
NC
I/O7R
C130-3
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
7C131
33
7C141
32
31
30
29
28
27
1415 16 17 18 19 20 21 22 23 24 25 26
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
NC
I/O7R
C130-4
Selection Guide
7C131-15[3,4] 7C131-25[3]
7C141-15
7C141-25
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Com’l/Ind
Maximum Standby
Current (mA)
Com’l/Ind
7C130-30
7C131-30
7C140-30
7C141-30
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
15
25
30
35
45
55
190
170
170
120
90
90
170
120
120
75
65
65
45
35
35
65
45
45
Military
Military
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-Up Current .................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Range
Ambient
Temperature
VCC
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
Commercial
0°C to +70°C
5V ± 10%
Industrial
–40°C to +85°C
5V ± 10%
DC Input Voltage............................................ –3.5V to +7.0V
Military[5]
–55°C to +125°C
5V ± 10%
Supply Voltage to Ground Potential
(Pin 48 to Pin 24) ........................................... –0.5V to +7.0V
Output Current into Outputs (LOW) ............................. 20 mA
Notes:
3. 15 and 25-ns version available only in PLCC/PQFP packages.
4. Shaded area contains preliminary information.
5. TA is the “instant on” case temperature
2
CY7C130/CY7C131
CY7C140/CY7C141
Electrical Characteristics Over the Operating Range[6]
7C131-15[3,4]
7C141-15
Parameter
Test Conditions
Min.
VOH
Output HIGH
Voltage
Description
VCC = Min., IOH = –4.0 mA
2.4
VOL
Output LOW
Voltage
IOL = 4.0 mA
IOL = 16.0
Max.
7C130-30[3]
7C131-25,30
7C140-30
7C141-25,30
Min.
0.4
mA[7]
Max.
2.4
Min.
2.4
2.4
0.4
0.5
V
0.4
0.5
V
0.5
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
IIX
Input Leakage
Current
GND < VI < VCC
–5
+5
–5
+5
–5
+5
–5
+5
µA
IOZ
Output Leakage
Current
GND < VO < VCC,
Output Disabled
–5
+5
–5
+5
–5
+5
–5
+5
µA
IOS
Output Short
Circuit Current[8, 9]
VCC = Max.,
VOUT = GND
ICC
VCC Operating
Supply Current
CE = VIL,
Outputs Open,
f = fMAX[10]
Com’l
Standby Current
Both Ports,
TTL Inputs
CEL and CER >
VIH, f = fMAX[10]
Com’l
Standby Current
One Port,
TTL Inputs
CEL or CER > VIH, Com’l
Active Port OutMil
puts Open,
[10]
f = fMAX
135
Standby Current
Both Ports,
CMOS Inputs
Both Ports CEL
Com’l
and CER > VCC – Mil
0.2V,
VIN > VCC – 0.2V
or VIN < 0.2V, f = 0
15
Standby Current
One Port,
CMOS Inputs
One Port CEL or
Com’l
CER > VCC – 0.2V, Mil
VIN > VCC – 0.2V
or VIN < 0.2V,
Active Port Outputs
Open,
f = fMAX[10]
125
ISB2
ISB3
ISB4
0.8
2.2
Max. Unit
VIH
ISB1
2.2
7C130-45,55
7C131-45,55
7C140-45,55
7C141-45,55
Min. Max.
0.4
0.5
2.2
7C130-35
7C131-35
7C140-35
7C141-35
0.8
2.2
0.8
V
–350
–350
–350
–350
mA
190
170
120
90
mA
170
120
45
35
65
45
90
75
115
90
15
15
15
15
85
70
105
85
Mil
75
65
Mil
115
15
105
Notes:
6. See the last page of this specification for Group A subgroup testing information.
7. BUSY and INT pins only.
8. Duration of the short circuit should not exceed 30 seconds.
9. This parameter is guaranteed but not tested.
10. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V.
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
]
3
Max.
Unit
15
pF
10
pF
mA
mA
mA
mA
CY7C130/CY7C131
CY7C140/CY7C141
AC Test Loads and Waveforms
R1 893Ω
5V
OUTPUT
5V
R1 893Ω
5V
OUTPUT
R2
347Ω
30 pF
INCLUDING
JIGAND
SCOPE
5 pF
INCLUDING
JIGAND
SCOPE
(a)
30
pF
(b)
C130-5
BUSY Output Load
(CY7C130/CY7C131 ONLY)
ALL INPUT PULSES
THÉVENIN EQUIVALENT
Equivalent to:
250Ω
OUTPUT
1.40V
281Ω
BUSY
OR
INT
R2
347Ω
3.0V
GND
10%
90%
10%
90%
C130-6
≤5ns
≤ 5 ns
Switching Characteristics Over the Operating Range[6,11]
7C131-15[3,4]
7C141-15
Parameter
Min.
Description
Max.
7C130-25[3]
7C131-25
7C140-25
7C141-25
Min.
Max.
7C130-30
7C131-30
7C140-30
7C141-30
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
Valid[12]
tAA
Address to Data
tOHA
Data Hold from Address Change
25
15
0
30
25
0
ns
30
0
ns
ns
tACE
CE LOW to Data
Valid[12]
15
25
30
ns
tDOE
OE LOW to Data Valid[12]
10
15
20
ns
tLZOE
OE LOW to Low Z[9,13, 14]
Z[9,13, 14]
tHZOE
OE HIGH to High
tLZCE
CE LOW to Low Z[9,13, 14]
tHZCE
CE HIGH to High
CE LOW to Power-Up[9]
CE HIGH to
3
10
3
Z[9,13, 14]
tPU
tPD
3
15
5
10
0
Power-Down[9]
3
15
5
15
0
15
ns
ns
15
0
25
ns
ns
ns
25
ns
WRITE CYCLE[15]
tWC
Write Cycle Time
15
25
30
ns
tSCE
CE LOW to Write End
12
20
25
ns
tAW
Address Set-Up to Write End
12
20
25
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
R/W Pulse Width
12
15
25
ns
tSD
Data Set-Up to Write End
10
15
15
ns
tHD
Data Hold from Write End
0
tHZWE
R/W LOW to High Z[14]
tLZWE
R/W HIGH to Low Z[14]
0
10
0
0
15
0
ns
15
0
ns
ns
Notes:
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
IOL/IOH, and 30-pF load capacitance.
12. AC Test Conditions use VOH = 1.6V and VOL = 1.4V.
13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
14. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
15. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate
a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write
4
CY7C130/CY7C131
CY7C140/CY7C141
Switching Characteristics Over the Operating Range[6,11] (continued)
7C131-15[3,4]
7C141-15
Parameter
Min.
Description
Max.
7C130-25[3]
7C131-25
7C140-25
7C141-25
Min.
Max.
7C130-30
7C131-30
7C140-30
7C141-30
Min.
Max.
Unit
BUSY/INTERRUPT TIMING
tBLA
BUSY LOW from Address Match
15
20
20
ns
tBHA
BUSY HIGH from Address Mismatch[16]
15
20
20
ns
tBLC
BUSY LOW from CE LOW
15
20
20
ns
tBHC
BUSY HIGH from CE HIGH[16]
15
20
20
ns
tPS
Port Set Up for Priority
tWB[17]
R/W LOW after BUSY LOW
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH
13
20
30
ns
5
5
5
ns
tBDD
BUSY HIGH to Valid Data
15
25
30
ns
tDDD
Write Data Valid to Read Data Valid
Note
18
Note
18
Note
18
ns
tWDD
Write Pulse to Data Delay
Note
18
Note
18
Note
18
ns
INTERRUPT TIMING
tWINS
R/W to INTERRUPT Set Time
15
25
25
ns
tEINS
CE to INTERRUPT Set Time
15
25
25
ns
tINS
Address to INTERRUPT Set Time
15
25
25
ns
tOINR
OE to INTERRUPT Reset
Time[16]
15
25
25
ns
tEINR
CE to INTERRUPT Reset Time[16]
15
25
25
ns
INTERRUPT Reset Time[16]
Address to
15
25
25
tINR
Notes:
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. CY7C140/CY7C141 only.
18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
ns
Switching Characteristics Over the Operating Range[6,11]
7C130-35
7C131-35
7C140-35
7C141-35
Parameter
Description
Min.
Max.
7C130-45
7C131-45
7C140-45
7C141-45
Min.
Max.
7C130-55
7C131-55
7C140-55
7C141-55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
35
Valid[12]
tAA
Address to Data
tOHA
Data Hold from Address Change
45
35
0
55
45
0
ns
55
0
ns
ns
tACE
CE LOW to Data
Valid[12]
35
45
55
ns
tDOE
OE LOW to Data Valid[12]
20
25
25
ns
Z[9,13, 14]
tLZOE
OE LOW to Low
tHZOE
OE HIGH to High Z[9,13, 14]
tLZCE
CE LOW to Low Z[9,13, 14]
tHZCE
CE HIGH to High Z[9,13, 14]
tPU
CE LOW to Power-Up[9]
tPD
CE HIGH to Power-Down[9]
3
3
20
5
5
20
0
ns
25
5
20
0
35
5
3
20
25
0
35
ns
ns
ns
ns
35
ns
CY7C130/CY7C131
CY7C140/CY7C141
Switching Characteristics Over the Operating Range[6,11] (continued)
7C130-35
7C131-35
7C140-35
7C141-35
Parameter
Description
Min.
Max.
7C130-45
7C131-45
7C140-45
7C141-45
Min.
Max.
7C130-55
7C131-55
7C140-55
7C141-55
Min.
Max.
Unit
WRITE CYCLE[15]
tWC
Write Cycle Time
35
45
55
ns
tSCE
CE LOW to Write End
30
35
40
ns
tAW
Address Set-Up to Write End
30
35
40
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
R/W Pulse Width
25
30
30
ns
tSD
Data Set-Up to Write End
15
20
20
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
R/W LOW to High Z[14]
tLZWE
R/W HIGH to Low Z[14]
20
0
20
0
25
0
ns
ns
BUSY/INTERRUPT TIMING
tBLA
BUSY LOW from Address Match
20
25
30
ns
tBHA
BUSY HIGH from Address Mismatch[16]
20
25
30
ns
tBLC
BUSY LOW from CE LOW
20
25
30
ns
tBHC
BUSY HIGH from CE HIGH[16]
20
25
30
ns
tPS
Port Set Up for Priority
5
5
5
ns
tWB[17]
R/W LOW after BUSY LOW
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH
30
tBDD
BUSY HIGH to Valid Data
tDDD
tWDD
35
35
ns
35
45
45
ns
Write Data Valid to Read Data Valid
Note
18
Note
18
Note
18
ns
Write Pulse to Data Delay
Note
18
Note
18
Note
18
ns
INTERRUPT TIMING
tWINS
R/W to INTERRUPT Set Time
25
35
45
ns
tEINS
CE to INTERRUPT Set Time
25
35
45
ns
tINS
Address to INTERRUPT Set Time
25
35
45
ns
tOINR
OE to INTERRUPT Reset Time[16]
25
35
45
ns
tEINR
CE to INTERRUPT Reset Time[16]
25
35
45
ns
tINR
Address to INTERRUPT Reset Time[16]
25
35
45
ns
Switching Waveforms
[19, 20]
Either Port Address Access
Read Cycle No.1
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATAVALID
DATA VALID
C130-7
Notes:
19. R/W is HIGH for read cycle.
20. Device is continuously selected, CE = VIL and OE = VIL.
6
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Read Cycle No. 2 [19, 21]
Either Port CE/OE Access
CE
tHZCE
tACE
OE
tLZOE
tHZOE
tDOE
tLZCE
DATA VALID
DATA OUT
tPU
tPD
ICC
ISB
Read Cycle
C130-8
No.3 [20]
Read with BUSY, Master: CY7C130 and CY7C131
tRC
ADDRESSR
ADDRESS MATCH
tPWE
R/WR
tHD
DINR
VALID
ADDRESS MATCH
ADDRESSL
tPS
tBHA
BUSYL
tBLA
tBDD
DOUTL
VALID
tWDD
tDDD
C130-9
[15, 22]
Write Cycle No.1 (OE Three-States Data I/Os - Either Port)
Either Port
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
R/W
tSD
DATAIN
tHD
DATA VALID
OE
tHZOE
HIGH IMPEDANCE
DOUT
C130-10
Notes:
21. Address valid prior to or coincident with CE transition LOW.
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data
to be placed on the bus for the required tSD.
7
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Write Cycle No. 2 (R/W Three-States Data I/Os - Either Port)
[16, 23]
Either Port
tWC
ADDRESS
tSCE
tHA
CE
tAW
tSA
tPWE
R/W
tSD
DATAIN
tHD
DATA VALID
tLZWE
tHZWE
HIGH IMPEDANCE
DATAOUT
C130-11
Busy Timing Diagram No. 1 (CE Arbitration)
CEL Valid First:
ADDRESSL,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
C130-12
CER Valid First:
ADDRESSL,R
ADDRESS MATCH
CER
tPS
CEL
tBLC
tBHC
BUSYL
C130-13
Note:
23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state
8
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
tRC or tWC
ADDRESS MATCH
ADDRESSL
ADDRESS MISMATCH
tPS
ADDRESS R
tBLA
tBHA
BUSYR
C130-14
Right Address Valid First:
tRC or tWC
ADDRESS MATCH
ADDRESSR
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSYL
C130-15
Busy Timing Diagram No. 3
Write with BUSY (Slave:CY7C140/CY7C141)
CE
tPWE
R/W
tWB
tWH
BUSY
C130-16
9
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR
tWC
ADDRL
WRITE 3FF
tINS
tHA
CEL
tEINS
R/WL
tSA
tWINS
INTR
C130-17
Right Side Clears INTR
tRC
ADDRR
READ 3FF
tHA
tINT
CER
tEINR
R/WR
OER
tOINR
INTR
C130-18
Right Side Sets INTL
t WC
ADDRR
WRITE 3FE
tHA
tINS
CER
tEINS
R/WR
tSA
tWINS
INTL
C130-19
Left Side Clears INTL
tRC
ADDRR
READ 3FE
tHA
tINR
CEL
tEINR
R/WL
OEL
tOINR
INTL
C130-20
10
CY7C130/CY7C131
CY7C140/CY7C141
Typical DC and AC Characteristics
1.4
120
1.2
1.2
ICC
1.0
ICC
1.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs.SUPPLYVOLTAGE
100
80
0.8
0.8
0.6
0.4
0.4
0.2
I SB3
0.2
0.0
4.0
4.5
5.0
5.5
6.0
60
VCC =5.0V
VIN =5.0V
0.6
VCC =5.0V
TA =25°C
40
20
ISB3
0
0.6
-55
25
0
125
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1.4
1.6
1.3
1.4
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.0
OUTPUT SINK CURRENT
vs.OUTPUT VOLTAGE
140
120
100
1.2
1.2
80
1.1
1.0
VCC =5.0V
40
0.8
0.9
0.8
4.0
4.5
5.0
5.5
6.0
25
125
SUPPLYVOLTAGE (V)
AMBIENT TEMPERATURE (°C)
TYPICAL POWER -ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
2.5
25.0
2.0
20.0
1.5
15.0
1.0
10.0
0.5
5.0
0
1.0
2.0
3.0
4.0
SUPPLYVOLTAGE (V)
5.0
0
VCC =5.0V
TA =25°C
20
0.6
-55
3.0
0.0
60
1.0
TA =25°C
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED I CC vs.CYCLETIME
1.25
VCC =4.5V
TA =25°C
VIN =0.5V
1.0
0.75
VCC =4.5V
TA =25°C
0
200
400
600
800 1000
CAPACITANCE (pF)
11
0.50
10
20
30
CYCLE FREQUENCY (MHz)
40
CY7C130/CY7C131
CY7C140/CY7C141
Ordering Information
Speed
(ns)
30
35
45
55
Speed
(ns)
15
25
30
35
45
55
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C130-30PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C130-30PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C130-35PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C130-35PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C130-35DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C130-45PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C130-45PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C130-45DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C130-55PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C130-55PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C130-55DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
Package
Name
Package Type
Operating
Range
CY7C131-15JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C131-15NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-25JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-25NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-25JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-25NI
N52
52-Pin Plastic Quad Flatpack
CY7C131-30JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-30NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-30JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C131-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C131-35NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-35JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-35NI
N52
52-Pin Plastic Quad Flatpack
CY7C131-45JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-45NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-45JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-45NI
N52
52-Pin Plastic Quad Flatpack
CY7C131-55JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-55NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-55JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-55NI
N52
52-Pin Plastic Quad Flatpack
Ordering Code
Shaded area contains preliminary information.
12
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
CY7C130/CY7C131
CY7C140/CY7C141
Ordering Information (continued)
Speed
(ns)
30
35
45
55
Speed
(ns)
Ordering Code
CY7C140-30PC
Package
Name
P25
Package Type
48-Lead (600-Mil) Molded DIP
Operating
Range
Commercial
CY7C140-30PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C140-35PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C140-35PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C140-35DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C140-45PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C140-45PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C140-45DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C140-55PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C140-55PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C140-55DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
Ordering Code
Package
Name
Package Type
Operating
Range
52-Lead Plastic Leaded Chip Carrier
Commercial
15
CY7C141-15JC
J69
CY7C141-15NC
N52
52-Pin Plastic Quad Flatpack
25
CY7C141-25JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-25NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-25JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-25NI
N52
52-Pin Plastic Quad Flatpack
CY7C141-30JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-30NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-30JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C141-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C141-35NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-35JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-35NI
N52
52-Pin Plastic Quad Flatpack
CY7C141-45JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-45NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-45JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-45NI
N52
52-Pin Plastic Quad Flatpack
CY7C141-55JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-55NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-55JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-55NI
N52
52-Pin Plastic Quad Flatpack
30
35
45
55
Shaded area contains preliminary information.
13
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
CY7C130/CY7C131
CY7C140/CY7C141
MILITARY SPECIFICATIONS
Switching Characteristics
Group A Subgroup Testing
Parameter
DC Characteristics
Parameter
VOH
VOL
VIH
VIL Max.
IIX
IOZ
ICC
ISB1
ISB2
ISB3
ISB4
Subgroups
READ CYCLE
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
tRC
7, 8, 9, 10, 11
tAA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
tDOE
7, 8, 9, 10, 11
WRITE CYCLE
tWC
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tPWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
Parameter
Subgroups
BUSY/INTERRUPT TIMING
tBLA
7, 8, 9, 10, 11
tBHA
7, 8, 9, 10, 11
tBLC
7, 8, 9, 10, 11
tBHC
7, 8, 9, 10, 11
tPS
7, 8, 9, 10, 11
tWINS
7, 8, 9, 10, 11
tEINS
7, 8, 9, 10, 11
tINS
7, 8, 9, 10, 11
tOINR
7, 8, 9, 10, 11
tEINR
7, 8, 9, 10, 11
tINR
7, 8, 9, 10, 11
BUSY TIMING
tWB[24]
7, 8, 9, 10, 11
tWH
7, 8, 9, 10, 11
tBDD
7, 8, 9, 10, 11
Note:
24. CY7C140/CY7C141 only.
Document #: 38-00027-L
r
14
CY7C130/CY7C131
CY7C140/CY7C141
Package Diagrams
48-Lead (600-Mil) Sidebraze DIP D26
52-Lead Plastic Leaded Chip Carrier J69
15
CY7C130/CY7C131
CY7C140/CY7C141
Package Diagrams (continued)
48-Lead (600-Mil) Molded DIP P25
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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