Order this document by MC33470/D The MC33470 is a digitally programmable switching voltage regulator, specifically designed for Microprocessor supply, Voltage Regulator Module and general purpose applications, to provide a high power regulated output voltage using a minimum of external parts. A 5–bit digital–to–analog converter defines the dc output voltage. This product has three additional features. The first is a pair of high speed comparators which monitor the output voltage and expedite the circuit response to load current changes. The second feature is a soft start circuit which establishes a controlled response when input power is applied and when recovering from external circuit fault conditions. The third feature is two output drivers which provide synchronous rectification for optimum efficiency. This product is ideally suited for computer, consumer, and industrial equipment where accuracy, efficiency and optimum regulation performance is desirable. SYNCHRONOUS RECTIFICATION DC/DC CONVERTER PROGRAMMABLE INTEGRATED CONTROLLER SEMICONDUCTOR TECHNICAL DATA 20 1 DW SUFFIX PLASTIC PACKAGE CASE 751D (SO–20L) MC33470 Features: • • • • • • • • • 5–Bit Digital–to–Analog Converter Allows Digital Control of Output Voltage High Speed Response to Transient Load Conditions Output Enable Pin Provides On/Off Control Programmable Soft Start Control PIN CONNECTIONS High Current Output Drives for Synchronous Rectification Internally Trimmed Reference with Low Temperature Coefficient Programmable Overcurrent Protection Overvoltage Fault Indication Functionally Similar to the LTC1553 20 G1 G2 1 2 PV CC PGnd 3 18 VID0 AGnd 4 17 VID1 VCC 5 16 VID2 Sense 6 15 VID3 Imax 7 14 VID4 19 OUTEN Ifb 8 13 Pwrgd SS 9 12 Fault Compensation 10 11 OT (Top View) ORDERING INFORMATION Device Operating Temperature Range Package MC33470DW TA = 0° to +75°C SO–20L Motorola, Inc. 1999 MOTOROLA ANALOG IC DEVICE DATA Rev 1 1 MC33470 Simplified Block Diagram OT 18 VID0 17 Voltage Identification 16 Code Input 15 VID1 VID3 14 VID4 11 Outen 19 VCC 5 Over Temp VID2 Digitally Programmed Reference Vref VCC 7 Over Current Detect Oscillator 2.5 V VCC 90 µA 1.5 V S Q 800 µ + G1 Q R SS Vref Delay PWM Latch 1 G2 3 + 1.04 Vref PGnd OTA Error Amp 20 µA + 1.04 Vref 13 R Power Good + 8 Ifb 6 Sense 2 20 10 µA 0.96 Vref Imax PV CC En PWM Comparator 9 190 µA Q 0.93 Vref Delay S 14 Fault 1.14 Vref AGnd 4 Compensation 10 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ MAXIMUM RATINGS (TC = 25°C, unless otherwise noted.) Rating Symbol Value Unit VCC 7.0 V PV CC 18 V Imax, Ifb Inputs Vin –0.3 to 18 V All Other Inputs and Digital (OT, Fault, Power Good) Outputs Vin –0.3 to VCC + 0.3 V PD RθJA RθJC 0.60 91 60 W °C/W °C/W Operating Junction Temperature TJ 125 °C Operating Ambient Temperature (Notes 1 and 2) TA 0 to +70 °C Tstg –55 to +125 °C Power Supply Voltage Output Driver Supply Voltage (Operating) Power Dissipation and Thermal Characteristics Maximum Power Dissipation Case 751D DW Suffix (TA = 70°C) Thermal Resistance Junction–to–Ambient Thermal Resistance Junction–to–Case Storage Temperature Range NOTE: 2 ESD data available upon request MOTOROLA ANALOG IC DEVICE DATA MC33470 ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, PVCC VCC, = 12 V for typical values TA = Low to High [Notes 1, 2, 3], for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit fosc 210 300 390 kHz Vsense 1.764 2.744 3.43 1.8 2.8 3.5 1.836 2.856 3.57 V V V Input Bias Current (VCM = 2.8 V) IIB – 20 – µA Transconductance (VCM = 2.8 V, VCOMP = 2.0 V) GM 400 800 1200 µmho Open Loop Voltage Gain (VCOMP = 2.0 V) AVOL – 67 – dB Output Line Regulation (VCC = 4.5 to 5.5 V) Regline – 7.0 – mV Output Load Regulation Regload – 5.0 – mV IOH IOL – – 120 120 – – Duty Cycle at G1 Output Maximum Minimum DCmax DCmin 77 – 88 – 95 0 Propagation Delay Comp Input to G1 Output, TJ = 25°C Comp Input to G2 Output, TJ = 25°C tPLH1 tPLH2 – – 0.1 0.1 – – Charge Current (VSoft–Start = 0 V) Ichg 7.0 10 13 µA Discharge Current under Current Limit (Note 5) (VSoft–Start = 2.0 V, Vsense = Vout, Vimax = VCC, Vifb = 0 V) ISSIL 30 90 150 µA Discharge Current under Hard Current Limit (VSoft–Start = 2.0 V, Vsense < Vout/2, Vimax = VCC, Vifb = 0 V) ISSHIL 40 64 – mA Hard Current Limit Hold Time tSSHIL 100 200 300 µs IOL 133 190 247 µA – 0.93 1.04 0.96 1.07 – 200 50 400 100 600 150 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ OSCILLATOR Frequency (VCC = 4.5 to 5.5 V) FEEDBACK AMPLIFIER Voltage Feedback Input Threshold (Note 4) VID0, VID1, VID2 and VID4 = “1” and VID3 = “0” VID4 = “1” and VID0, VID1, VID2 and VID3 = “0” Output Current Source Sink µA PWM SECTION % µs SOFT–START SECTION IMAX INPUT Sink Current (Vin max = VCC, Vifb = VCC) POWER GOOD OUTPUT Threshold For Logic “1” to “0” Transition Upper Threshold Lower Threshold Vth Response Time Logic “0” to “1” (Vsense changes from 0 V to VO) Logic “1” to “0” (Vsense changes from VO to 0 V) trPG Vsense µs Sink Current (VOL = 0.5 V) IOLPG – 10 – mA Output Low Voltage (IOL = 100 µA) (Note 6) VOLPG – 250 500 mV NOTES: 1. Maximum package power dissipation limits must be observed. 2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 3. VID1, VID3, VID4 = logic 0, and VID0, VID2 = logic 1. 4. Vsense is provided from a low impedance voltage source or shorted to the output voltage. 5. Under a typical soft current limit, the net soft–start discharge current will be 90 µA (ISSIL) – 10 µA (Ichg) = 80 µA. The softstart sink to source current ratio is designed to be 9:1. 6 Sense (Pin 6) = 5.0 V, Comp (Pin 10) open, VID4, VID2, VID1, VID0 = 1.0, VID3 = 0. 7. OUTEN is internally pulled low if VID0, 1, 2, 3, and 4 are floating. 8. Due to internal pull–up resistors, there will be an additional 0.5 mA per pin if any of the VID0, 1, 2, 3, or 4 pins are pulled low. MOTOROLA ANALOG IC DEVICE DATA 3 MC33470 ELECTRICAL CHARACTERISTICS (continued) (VCC = 5.0 V, PVCC V , = 12 V for typical values TA = Low to High [Notes 1, 2, 3], for CC min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit VthF 1.12 1.14 1.2 Vref ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ FAULT OUTPUT Threshold For Logic “0” to “1” Transition trF 50 100 150 µs IOLF – 10 – mA VthOUTEN 1.85 2.0 2.2 V Delay Time tDOT 25 50 100 µs Sink Current (VOL = 0.5 V) IOLF – 10 – mA Input Low State VIL – – 0.8 V Input High State VIH 3.5 – – V Input Impedance Rin – 10 – kΩ VOTDD 1.55 1.70 1.85 V Source Resistance (Vsense = 2.0 V, VG = PPVCC VCC – 1.0 V) Sink Resistance (Vsense = 0 V, VG = 1.0 V) ROH – 0.5 – Ω ROL – 0.5 – Output Voltage with OUTEN Reset (Isink = 1.0 mA) VOL – 0.1 0.5 V Output Voltage Rise Time (CL = 10 nF, TJ = 25°C) tr – 70 140 ns Output Voltage Fall Time (CL = 10 nF, TJ = 25°C) tf – 70 140 ns tNOL 30 150 210 ns PV CC min 10.8 – – V VCC min 3.0 – 4.25 V ICC – 3.7 8.0 mA PI CC – 15 – mA Vsense Response Time Switches from 2.8 V to VCC Sink Current (VOL = 0.5 V) OVERTEMPERATURE OUTPUT Threshold For Logic “1” to “0” Transition (OUTEN Voltage Decreasing) LOGIC INPUTS (VID0, VID1, VID2, VID3, VID4) OUTPUT ENABLE CONTROL (OUTEN) Over–Temperature Driver Disable and Reset (OUTEN Voltage Decreasing) (Note 7) OUTPUT SECTIONS (G1, G2) G1, G2 Non–Overlap Time (CL = 10 nF, TJ = 25°C) TOTAL DEVICE ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ PVCC Minimum Operating Voltage After Turn–On (P VCC Decreasing) Minimum Operating Voltage After Turn–On (VCC Decreasing) VCC Current (Note 8) (OUTEN and PPVCC VCC open, VID0, 1, 2, 3, 4 Floating) PV Current (OUTEN = 5.0 V, VID0, 1, 2, 3, 4 Open, PPVCC VCC VCC = 12 V) CC NOTES: 1. Maximum package power dissipation limits must be observed. 2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 3. VID1, VID3, VID4 = logic 0, and VID0, VID2 = logic 1. 4. Vsense is provided from a low impedance voltage source or shorted to the output voltage. 5. Under a typical soft current limit, the net soft–start discharge current will be 90 µA (ISSIL) – 10 µA (Ichg) = 80 µA. The softstart sink to source current ratio is designed to be 9:1. 6 Sense (Pin 6) = 5.0 V, Comp (Pin 10) open, VID4, VID2, VID1, VID0 = 1.0, VID3 = 0. 7. OUTEN is internally pulled low if VID0, 1, 2, 3, and 4 are floating. 8. Due to internal pull–up resistors, there will be an additional 0.5 mA per pin if any of the VID0, 1, 2, 3, or 4 pins are pulled low. 4 MOTOROLA ANALOG IC DEVICE DATA MC33470 Figure 1. Output Drive Waveform Figure 2. 5.0 V Supply Current VO = 2.8 V IO = 3.3 A Figure 13 Circuit I CC, SUPPLY CURRENT (mA) 2.0 V/DIV 8.0 TA = 25°C 7.0 6.0 5.0 PV CC 4.0 + 12 V 3.0 PV CC + Open 5.0 6.0 2.0 1.0 0 0 1.0 2.0 3.0 4.0 7.0 8.0 200 nS/DIV INPUT VOLTAGE (V) Figure 3. Error Amplifier Transient Response Figure 4. Drive Output Source/Sink Saturation Voltage versus Load Current 0 PV CC –0.5 Source Saturation (Load to Ground) 500 mV/DIV –1.0 0 VO = 2.8 V IO transient = 0.3 to 16 A Figure 13 Circuit Sink Saturation (Load to PV ) CC 1.0 0.5 Ground 0 2.5 mS/DIV 0 0.4 0.6 0.8 1.0 Figure 6. Feedback Loop Gain and Phase versus Frequency 20 VO = 2.8 V IO transient = 0.3 to 16 A Figure 13 Circuit 50 mV/DIV LOOP GAIN (dB) 15 MOTOROLA ANALOG IC DEVICE DATA 10 0 VCCP = 12 V VCC = 5.0 V VO = 2.8 V IO = 3.3 A TA = 25°C Gain 30 Phase 60 90 5.0 0 120 –5.0 150 –10 300 1.0 k 3.0 k 10 k 30 k f, FREQUENCY (Hz) 100 k 180 300 k 5 ∅ 2.5 mS/DIV 1.2 , EXCESS PHASE (DEGREES) Figure 5. Feedback Circuit Load Transient Response 0.2 MC33470 Figure 7. Drive Output Source/Sink Saturation Voltage versus Load Current 0.8 30 VCCP = 12 V VCC = 5.0 V VO = 2.8 V R2 = 18.2 k C16 = 0 TA = 25°C Figure 13 100 10 60 90 Phase 120 180 1000 1.0 1.0 10 ∅ 150 THRESHOLD VOLTAGE CHANGE (%) Gain , EXCESS PHASE (DEGREES) 0 1000 GAIN (µmho) Figure 8. Feedback Threshold Voltage versus Temperature 100 FREQUENCY (kHz) –4.0 UVLO THRESHOLD CHANGE (%) 50 –25 0 25 50 75 75 100 2.0 0 –2.0 –4.0 –5.0 –75 125 –50 –25 0 25 50 75 Figure 11. VCC Undervoltage Lockout Trip Point versus Temperature Figure 12. Oscillator Frequency versus Temperature 1.0 2.5 0.5 2.0 0 –0.5 –1.0 –1.5 –2.0 –2.5 VCC Increasing IO = 3.3 A VO = 2.8 V –3.0 –50 –25 0 25 50 125 IO = 3.3 A VO = 2.8 V TA, AMBIENT TEMPERATURE (°C) –3.5 100 4.0 TA, AMBIENT TEMPERATURE (°C) –4.0 –75 75 TA, AMBIENT TEMPERATURE (°C) 6 I sense, CURRENT CHANGE (%) –2.0 UVLO THRESHOLD CHANGE (%) I max, CURRENT CHANGE (%) 0 25 –50 5.0 IO = 3.3 A VO = 2.8 V 0 0 Figure 10. Vsense Current Source versus Temperature 2.0 –25 0.2 TA, AMBIENT TEMPERATURE (°C) 4.0 –50 0.4 –0.2 –75 Figure 9. Imax Current versus Temperature –6.0 –75 IO = 3.3 A VO = 2.8 V 0.6 100 125 1.5 1.0 100 125 100 125 IO = 3.3 A VO = 2.8 V 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –75 –50 –25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) MOTOROLA ANALOG IC DEVICE DATA MOTOROLA ANALOG IC DEVICE DATA To µP J1–B9 R3 100 k SS 13 Power Good 6 Sense 4 AGnd + + + + 2.5 V 1.04 Vref C1, C2 – C3 – C6, C13 – C10, C11 – C17 100 pF 0.96 Vref 1.04 Vref 1.14 Vref Vref Over Temp Q Delay En OSCON 16SA150M TDK C3216Y5V1C476Z TDK C3216Y5V1C106Z OSCON 4SP820M PWM Latch R S + 4.0/3.8 VCC 5 Q U1 S R Delay I max R4 56 20 Ifb 12 Fault 3 1 PGnd G2 8 R8 4.7 4 2, 3 Q1 MMSF3300R2 5, 6, 7, 8 12 V J1–A4, B4 C5 470 pF R5 1.2 k R6 100 k D2 Fault Indicate C11 C13 C10 820 µ F 820 µ F 1.0 µ F 4.0 V 4.0 V + C2 150 µ F 16 V Q2 MMSF3300R2 5, 6, 7, 8 L1 1.5 µH + C1 150 µ F 16 V Q4 MBRD1035CT MMSF3300R2 2, 3 Q3 MMSF3300R2 5, 6, 7, 8 R7 4.7 4 R9 10 2 G1 V DRIVE + C6 1.0 µF 7 R1 2.7 k C3 4.7 µ F L2 1.5 µ H Input Voltage Vin = 5.0 V J1–A1, A2, A3, B1, B2 J1 – AMP 532956–7 L1, L2 – Coilraft U6904 VCC R10 10 Over Current 190 µA Detect ≤90 µA OUTEN 19 J1–B5 D1 J1–B6 Undervoltage Lockout 11 10 Compensation C16 2200 pF R2 8.2 k 0.96 Vref PWM Comparator OTA Error Amp 800 µ Vref /2 1.5 V Digitally Programmed Reference Oscillator Vref 20 µA 64 mA 10 µA VCC 14 VID4 15 VID3 16 VID2 17 VID1 9 C18 0.01 µF J1–A9 Voltage Identification J1–A8 Code Input J1–B8 J1–B7 J1–A7 18 VID0 OT UP# OUTEN VSS J1–A11, A13, A15 A17, A19, B10, B12 B14, B16, B18, B20 VO 0.3 to 14 A J1–A10, A12, A14, A16, A18, A20, B11, B13, B15, B17, B19 MC33470 Figure 13. MC33470 Application Circuit 7 MC33470 Figure 14. Timing Diagram UVL Threshold 12 V UVL Threshold 5.0 V Internal Vref Timing Capacitor 2.5 V 1.5 V Compensation G1 G2 OPERATING DESCRIPTION The MC33470 is a monolithic, fixed frequency power switching regulator specifically designed for dc–to–dc converter applications which provide a precise supply voltage for state of the art processors. The MC33470 operates as fixed frequency, voltage mode regulator containing all the active functions required to directly implement digitally programmable step–down synchronous rectification with a minimum number of external components. Oscillator The oscillator frequency is internally programmed to 300 kHz. The charge to discharge ratio is controlled to yield a 95% maximum duty cycle at the switch outputs. During the fall time of the internal sawtooth waveform, the oscillator generates an internal blanking pulse that disables the G1 output switching MOSFET. The internal sawtooth waveform has a nominal peak voltage of 2.5 V and a valley voltage of 1.5 V. Pulse Width Modulator The pulse width modulator consists of a comparator with the oscillator ramp voltage applied to the noninverting input, while the error amplifier output is applied to the inverting input. Output switch conduction is initiated when the ramp waveform is discharged to the valley voltage. As the ramp voltage increases to a voltage that exceeds the error amplifer output, the latch resets, terminating output G1 MOSFET conduction, and turning on output G2 MOSFET, for the duration of the oscillator ramp. This PWM/latch combination 8 prevents multiple output pulses during a given oscillator cycle. The sense voltage input at Pin 6 is applied to the noninverting inputs of a pair of high speed comparators. The high speed comparators’ inverting inputs are tied 0.96 x Vref and 1.04 x Vref, respectively, to provide an optimum response to load changes. When load transients which cause the output voltage to fall outside a 4% regulation window occur, the high speed comparators override the PWM comparator to force a zero or maximum duty cycle operating condition until the output voltage is once again within the linear window. When voltages are initially provided to the supply pins, VCC and PV , undervoltage lockout circuits monitor each CC of the supply voltage levels. Both G1 and G2 output pins are held low until the VCC pin voltage exceeds 4.0 V and the pin voltage exceeds 9.0 V. PV CC " Error Amplifier and Voltage Reference The error amplifier is a transconductance type amplifier, having a nominal transconductance of 800 µmho. The transconductance has a negative temperature coefficient. Typical transconductance is 868 µmho at 0°C and 620 µmho at 125°C junction temperature. The amplifier has a cascode output stage which provides a typical 3.0 Mega–Ohms of impedance. The typical error amplifier dc voltage gain is 67 dB. External loop compensation is required for converter stability. Compensation components may be connected from MOTOROLA ANALOG IC DEVICE DATA MC33470 the compensation pin to ground. The error amplifier input is tied to the sense pin which also has an internal 20 µA current source to ground. The current source is intended to provide a 24 mV offset when an external 1.2 k resistor is placed between the output voltage and the sense pin. The 24 mV offset voltage is intended to allow a greater dynamic load regulation range within a given specified tolerance for the output voltage. The offset may be increased by increasing the resistor value. The offset can be eliminated by connecting the sense pin directly to the regulated output voltage. The voltage reference consists of an internal, low temperature coefficient, reference circuit with an added offset voltage. The offset voltage level is the output of the digital–to–analog converter. Control bits VID0 through VID4 control the amount of offset voltage which sets the value of the voltage reference, as shown in Table 1. The VID0–4 input bits each have internal 10 k pullup resistances. Therefore, the reference voltage, and the output voltage, may be programmed by connecting the VID pins to ground for logic “0” or by an open for a logic “1”. Typically, a logic “1” will be recognized by a voltage > 0.67 x VCC. A logic “0” is a voltage < VCC/3. MOSFET Switch Outputs The output MOSFETs are designed to switch a maximum of 18 V, with a peak drain current of 2.0 A. Both G1 and G2 output drives are designed to switch N–channel MOSFETs. Output drive controls to G1 and G2 are phased to prevent cross conduction of the internal IC output stages. Output dead time is typically 100 nanoseconds between G1 and G2 in order to minimize cross conduction of the external switching MOSFETs. Current Limit and Soft–Start Controls The soft–start circuit is used both for initial power application and during current limit operation. A single external capacitor and an internal 10 µA current source control the rate of voltage increase at the error amplifier output, establishing the circuit turn on time. The G1 output will increase from zero duty cycle as the voltage across the soft–start capacitor increases beyond about 0.5 V. When the soft–start capacitor voltage has reached about 1.5 V, normal duty cycle operation of G1 will be allowed. An overcurrent condition is detected by the current limit amplifier. The current limit amplifier is activated whenever the G1 output is high. The current limit amplifier compares the voltage drop across the external MOSFET driven by G1, as measured at the IFB pin, with the voltage at the Imax pin. Because the Imax pin draws 190 µA of input current, the overcurrent threshold is programmed by an external resistor. Referring to Figure 13, the current limit resistor value can be determined from the following equation: R1 + [( I )(R )] L(max) DS(on) ( Imax) where: I L(max) + I O ) Iripple 2 IO = Maximum load current Iripple = Inductor peak to peak ripple current OUTEN Input and OT Output Pins On and off control of the MC33470 may be implemented with the OUTEN pin. A logic “1” applied the OUTEN pin, where a logic “1” is above 2.0 V, will allow normal operation of the MC33470. The OUTEN pin also has multiple thresholds to provide over temperature protection. An negative temperature coefficient thermistor can be connected to the OUTEN pin, as shown in Figure 15. Together with RS, a voltage divider is formed. The divider voltage will decrease as the thermistor temperature increases. Therefore, the thermistor should be mounted to the hottest part on the circuit board. When the OUTEN voltage drops below 2.0 V typically, the MC33470 OT pin open collector output will switch from a logic “1” to a logic “0”, providing a warning to the system. If the OUTEN voltage drops below 1.7 V, both G1 and G2 output driver pins are latched to a logic “0” state. Figure 15. OUTEN/OT Overtemperature Function VCC 10 k OT VCC RS MC33470 OUTEN NTC Thermistor APPLICATIONS INFORMATION Design Example Given the following dc–to–dc converter: VCC = VCCP = VID4–0 bits = Output current = requirements, design a switching 5.0 V 12 V 10111 – Output Voltage = 2.8 V 0.3 A to 14 A Efficiency > 80% at full load Output ripple voltage ≈ 1% of output voltage MOTOROLA ANALOG IC DEVICE DATA 1. Choose power MOSFETs. In order to meet the efficiency requirement, MOSFETs should be chosen which have a low value of RDS(on). However, the threshold voltage rating of the MOSFET must also be greater than 1.5 V, to prevent turn on of the synchronous rectifier MOSFETs due to dv/dt coupling through the Miller capacitance of the MOSFET drain–to–source junction. Figure 16 shows the gate voltage transient due to this effect. 9 MC33470 In this design, choose two parallel MMSF3300 MOSFETs for both the main switch and the synchronous rectifier to maximize efficiency. 2. D ≈ VO/Vin = 2.8/5.0 = 0.56 3. Inductor selection In order to maintain continuous mode operation at 10% of full load current, the minimum value of the inductor will be: Lmin = (Vin – VO)(DTs)/(2IO min) = (5 – 2.8)(0.56 x 3.3 µs)/(2 x 1.4 A) = 1.45 µH Coilcraft’s U6904, or an equivalent, provides a surface mount 1.5 µH choke which is rated for for full load current. 4. Output capacitor selection Vripple ≈ ∆ IL x ESR, where ESR is the equivalent series resistance of the output capacitance. Therefore: ESRmax = Vripple/∆ IL = 0.01 x 2.8 V/1.4 A = 0.02 Ω maximum The AVX TPS series of tantalum chip capacitors may be chosen. Or OSCON capacitors may be used if leaded parts are acceptable. In this case, the output capacitance consists of two parallel 820 µF, 4.0 V capacitors. Each capacitor has a maximum specified ESR of 0.012 Ω. 5. Input Filter As with all buck converters, input current is drawn in pulses. In this case, the current pulses may be 14 A peak. If a 1.5 µH choke is used, two parallel OSCON 150 µF, 16 V capacitors will provide a filter cutoff frequency of 7.5 kHz. unity gain frequency to be 10% of the switching frequency, or 30 kHz. Plotting the PWM gain over frequency, at a frequency of 30 kHz the gain is about –16.5 dB = 0.15. Therefore, to have a 30 kHz unity gain loop, the error amplifier gain at 30 kHz should be 1/0.15 = 6.7. Choose a design phase margin for the loop of 60°. Also, choose the error amp type to be an integrator for best dc regulation performance. The phase boost needed by the error amplifier is then 60° for the desired phase margin. Then, the following calculations can be made: k = tan [Boost/2 + 45°] = tan [60/2 + 45] = 3.73 Error Amp zero freq = fc/K = 30 kHz/3.73 = 8.0 kHz Error Amp pole freq = Kfc = 3.73 x 30 kHz = 112 kHz R2 = Error Amp Gain/Gm = 6.7/800 µ = 8.375 k – use an 8.2 k standard value C16 = 1/(2π R2 fz) = 1/(2π x 8.2 k x 8.0 kHz) = 2426 pF – use 2200 pF C17 = 1/(2π R2 fp) = 1/(2π x 8.2 k x 112 kHz) = 173 pF – use 100 pF The complete design is shown in Figure 13. The PC board top and bottom views are shown in Figures 17 and 18. Figure 16. Voltage Coupling Through Miller Capacitance 6. Feedback Loop Compensation The corner frequency of the output filter with L = 1.5 µH and Co = 1640 µF is 3.2 kHz. In addition, the ESR of each output capacitor creates a zero at: fz = 1/(2π C ESR) = 1/(2π x 820 µF x 0.012) = 16.2 kHz The dc gain of the PWM is: Gain = Vin/Vpp = 5/1 = 5.0. Where Vpp is the peak–to–peak sawtooth voltage across the internal timing capacitor. In order to make the feedback loop as responsive as possible to load changes, choose the 10 MOTOROLA ANALOG IC DEVICE DATA MC33470 PIN FUNCTION DESCRIPTION Pin 1 Name G2 Description This is a high current dual totem pole output Gate Drive for the Lower, or rectifier, N–channel MOSFET. Its output swings from ground to P V . During initial power application, both G2 CC and G1 are held low until both VCC and P V have reached proper levels. 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It may be connected to 12 V. 3 PGnd This is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. 4 AGnd This pin is the ground for the control circuitry. 5 VCC This pin is the positive supply of the control IC. 6 Sense This pin is used for feedback from the output of the power supply. It has a 20 µA current source to ground which can be used to provide offset in the converter output voltage. 7 Imax This pin sets the current limit threshold. 190 µA must be sourced into the pin. The external resistor is determined from the following equation: R = ([RDS(on)] [ILIM]/[190 µA]) 8 IFB This pin has two functions. First, it provides cycle–by–cycle current limiting. Second, if the current is excessive, this pin will reinitiate a soft–start cycle. If the voltage at the IFB pin drops below the voltage at the Imax pin when G1 is on, the controller will go into current limit. The current limit circuit can be disabled by floating the Imax pin and shorting the IFB pin to VCC. 9 SS This is the soft–start pin. A capacitor at this pin, in conjunction with a 10 µA internal current source, sets the soft–start time. During moderate overload (current limit with VO > 50% of the set value), the soft–start capacitor will be discharged by an internal 90 µA current source in order to reduce the duty cycle of G1. During hard current limit (current limit with VO < 50% of set value), the soft–start capacitor will be discharged by a 64 mA current source. 10 Comp This pin is provided for compensating the error amp for poles and zeros encountered in the power supply system, mostly the output LC filter. 11 OT This is the over temperature fault pin. OT is an open drain output that will be pulled low if the OUTEN pin is less than 2.0 V. 12 Fault This pin indicates a fault condition. Fault is an open drain output that switches low if VO exceeds 115% of its set value. Once triggered, the controller will remain in this state until the power supply is recycled or the OUTEN pin is toggled. 13 Pwrgd This pin is an open drain output which indicates that VO is properly regulated. A high level on Pwrgd indicates that VO is within 4% of its set value for more than 400 µs. Pwrgd will switch low if VO is outside 4% for more than 100 µs. 14 VID4 Voltage ID pin. This CMOS–compatible input programs the output voltage as shown in Table 2. This pin has an internal 10 k pull–up resistor to VCC. 15 VID3 Voltage ID pin. This CMOS–compatible input programs the output voltage as shown in Table 2. This pin has an internal 10 k pull–up resistor to VCC. 16 VID2 Voltage ID pin. This CMOS–compatible input programs the output voltage as shown in Table 2. This pin has an internal 10 k pull–up resistor to VCC. 17 VID1 Voltage ID pin. This CMOS–compatible input programs the output voltage as shown in Table 2. This pin has an internal 10 k pull–up resistor to VCC. 18 VID0 Voltage ID pin. This CMOS–compatible input programs the output voltage as shown in Table 2. This pin has an internal 10 k pull–up resistor to VCC. 19 OUTEN This is the on/off control pin. A CMOS–compatible logic “1” allows the controller to operate. This pin can also be used as a temperature sensor to trigger the OT pin (when OUTEN drops below 2.0 V OT pulls low). When OUTEN drops below 1.7 V for longer than 50 µs, the controller will shut down. 20 G1 This is a high current dual totem pole output Gate Drive for the Upper, or switching, N–channel MOSFET. Its output swings from ground to PVCC VCC . During initial power application, both G2 and PVCC G1 are held low until both VCC and P VCC have reached proper levels. MOTOROLA ANALOG IC DEVICE DATA 11 MC33470 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Table 1. Voltage Identification Code 12 VID4 VID3 VID2 VID1 VID0 VO 0 1 1 1 1 – 0 1 1 1 0 – 0 1 1 0 1 – 0 1 1 0 0 – 0 1 0 1 0 – 0 1 0 0 1 – 0 1 0 0 0 – 0 0 1 1 1 – 0 0 1 1 0 – 0 0 1 0 1 1.8 0 0 1 0 0 1.85 0 0 0 1 1 1.9 0 0 0 1 0 1.95 0 0 0 0 1 2.0 0 0 0 0 0 2.05 1 1 1 1 1 No CPU 1 1 1 1 0 2.1 1 1 1 0 1 2.2 1 1 1 0 0 2.3 1 1 0 1 1 2.4 1 1 0 1 0 2.5 1 1 0 0 1 2.6 1 1 0 0 0 2.7 1 0 1 1 1 2.8 1 0 1 1 0 2.9 1 0 1 0 1 3.0 1 0 1 0 0 3.1 1 0 0 1 1 3.2 1 0 0 1 0 3.3 1 0 0 0 1 3.4 1 0 0 0 0 3.5 MOTOROLA ANALOG IC DEVICE DATA MC33470 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Table 2. Connector Pin Function PIN ROW A ROW B 1 5.0 Vin 5.0 Vin 2 5.0 Vin 5.0 Vin 3 5.0 Vin Reserved 4 12 Vin 12 Vin 5 Reserved UP# 6 Ishare OUTEN 7 VID0 VID1 8 VID2 VID3 9 VID4 Pwrgd 10 VCCP VSS 11 VSS VCCP 12 VCCP VSS 13 VSS VCCP 14 VCCP VSS 15 VSS VCCP 16 VCCP VSS 17 VSS VCCP 18 VCCP VSS 19 VSS VCCP 20 VCCP VSS MOTOROLA ANALOG IC DEVICE DATA 13 MC33470 Figure 17. PC Board Top View C1 R10 L2 C2 R8 L1 R9 C3 C12 C11 C10 Figure 18. PC Board Bottom View R1 R3 C5 R5 Q1 D2 Q2 J1 Q3 Q4 R4 C6 R7 R2 C13 R6 C16 R2 C17 14 MOTOROLA ANALOG IC DEVICE DATA MC33470 OUTLINE DIMENSIONS DW SUFFIX PLASTIC PACKAGE CASE 751D (SO–20L) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 20 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) M T A B S J S F R X 45 _ C –T– 18X G K MOTOROLA ANALOG IC DEVICE DATA SEATING PLANE DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M 15 MC33470 Motorola reserves the right to make changes without further notice to any products herein. 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