SN74LS174 Hex D Flip-Flop The LSTTL / MSI SN74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops. The LS174 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families. • • • • http://onsemi.com LOW POWER SCHOTTKY Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Asynchronous Common Reset Input Clamp Diodes Limit High Speed Termination Effects GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current – High – 0.4 mA IOL Output Current – Low 8.0 mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Device Package Shipping SN74LS174N 16 Pin DIP 2000 Units/Box SN74LS174D 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS174/D SN74LS174 CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q5 D5 D4 Q4 D3 Q3 CP 16 15 14 13 12 11 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 MR 2 Q0 3 D0 4 D1 5 Q1 6 D2 7 Q2 8 GND LOADING (Note a) PIN NAMES D0 – D5 CP MR Q0 – Q5 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. LOGIC SYMBOL 3 4 6 11 13 14 9 1 D0 D1 D2 D3 D4 D5 CP MR Q0 Q1 Q2 Q3 Q4 Q5 2 5 7 10 12 15 VCC = PIN 16 GND = PIN 8 LOGIC DIAGRAM MR CP D5 1 9 D4 14 D3 13 D2 D1 6 11 D0 4 3 D Q D Q D Q D Q D Q D Q CP CD CP CD CP CD CP CD CP CD CP CD 15 Q5 10 12 Q4 Q3 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS http://onsemi.com 2 7 Q2 5 2 Q1 Q0 SN74LS174 FUNCTIONAL DESCRIPTION A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The LS174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The LS174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW to HIGH Clock (CP) transition. TRUTH TABLE Inputs (t = n, MR = H) Outputs (t = n+1) Note 1 D Q H L H L Note 1: t = n + 1 indicates conditions after next clock. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Min Typ Max 2.0 0.8 – 0.65 2.7 – 1.5 3.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 26 mA VCC = MAX – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. http://onsemi.com 3 SN74LS174 AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ 30 40 Max Unit fMAX Maximum Input Clock Frequency tPHL Propagation Delay, MR to Output 23 35 ns tPLH tPHL Propagation Delay, Clock to Output 20 21 30 30 ns Max Unit Test Conditions MHz VCC = 5.0 V CL = 15 pF F AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ tW Clock or MR Pulse Width 20 ns ts Data Setup Time 20 ns th Data Hold Time 5.0 ns trec Recovery Time 25 ns Test Conditions VCC = 5 5.0 0V AC WAVEFORMS 1/fmax tw 1.3 V CP 1.3 V ts(H) D * th(H) 1.3 V Q ts(L) 1.3 V MR th(L) 1.3 V tW 1.3 V trec 1.3 V tPLH tPHL 1.3 V 1.3 V 1.3 V CP Q tPHL 1.3 V 1.3 V *The shaded areas indicate when the input is permitted to *change for predictable output performance. Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. http://onsemi.com 4 SN74LS174 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 5 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SN74LS174 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 9 1 8 –B– P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 6 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 SN74LS174 Notes http://onsemi.com 7 SN74LS174 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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