SAMSUNG S6E63D6

Data Sheet
S6E63D6
Preliminary
240 RGB X 320 Dot 1-Chip Driver IC with LTPS Interface
for 262,144 Color AMOLED Display Panel
November 7, 2006
System LSI Division
Device Solution Network
SAMSUNG ELECTRONICS CO., LTD.
(http://www.samsung.com/Products/Semiconductor/DisplayDriverIC)
Contents in this document are subject to change without notice. No part of this document may be reproduced or
transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written
permission of LCD Driver IC Team.
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
CONTENTS
ALIGN KEY CONFIGURATION AND COORDINATE ......................................................................................10
POWER SUPPLY PINS ....................................................................................................................................15
SYSTEM / RGB INTERFACE PINS..................................................................................................................17
DISPLAY PINS..................................................................................................................................................20
MISCELLANEOUS PINS ..................................................................................................................................20
SYSTEM INTERFACE ......................................................................................................................................21
HIGH SPEED SERIAL INTERFACE (MDDI) ....................................................................................................22
SUB PANEL CONTROL....................................................................................................................................22
EXTERNAL INTERFACE (RGB-I/F) .................................................................................................................22
ADDRESS COUNTER (AC)..............................................................................................................................22
GRAPHICS RAM (GRAM) ................................................................................................................................22
TIMING GENERATOR ......................................................................................................................................22
GRAYSCALE VOLTAGE GENERATOR ..........................................................................................................22
OSCILLATION CIRCUIT (OSC)........................................................................................................................22
SOURCE DRIVER CIRCUIT.............................................................................................................................23
LTPS PANEL INTERFACE CIRCUIT ...............................................................................................................23
GRAM ADDRESS MAP ....................................................................................................................................24
INSTRUCTION TABLE .....................................................................................................................................27
Index ..........................................................................................................................................................30
Status Read ...............................................................................................................................................30
No Operation (R00h) .................................................................................................................................30
STAND BY (R10h).....................................................................................................................................47
POWER GEN1 (R12h) ..............................................................................................................................48
POWER GEN2 (R13h) ..............................................................................................................................49
POWER STEP UP CONTROL 1 (R14h) ...................................................................................................51
START OSCILLATION (R18h) ..................................................................................................................52
SOURCE DRIVER CONTROL (R1Ah)......................................................................................................53
WRITE DATA TO GRAM (R22h)...............................................................................................................55
READ DATA FROM GRAM (R22h)...........................................................................................................56
SELECT DATA BUS 1 (R23h)...................................................................................................................57
SELECT DATA BUS 2 (R24h)...................................................................................................................57
VERTICAL SCROLL CONTROL 1 (R30h, R31h) .....................................................................................58
VERTICAL SCROLL CONTROL 2 (R32h) ................................................................................................59
PARTIAL SCREEN DRIVING POSITION (R33h, R34h)...........................................................................61
RESTRICTION ON PARTIAL DISPLAY AREA SETTING ........................................................................62
[NOTE] 000h ≤ SS18 to 10 ≤ SE18 to 10 ≤ 13Fh......................................................................................62
VERTICAL RAM ADDRESS POSITION (R35h,R36h)..............................................................................63
HORIZONTAL RAM ADDRESS POSITION (R37h)..................................................................................63
CLIENT INITIATED WAKE-UP (R38h)......................................................................................................64
MDDI LINK WAKE-UP START POSITION (R39h) ...................................................................................64
SUB PANEL CONTROL 1 (R3Ah / R3Bh) ................................................................................................64
SUB PANEL CONTROL 2 (R3Ch) ............................................................................................................65
TEST KEY COMMAND (R60h) .................................................................................................................66
MTP CONTROL (R61h) ............................................................................................................................66
MTP REGISTER SETTING (R62h, R63h, R64h, R65h) ...........................................................................66
GPIO CONTROL (R66h/R67h/R68h/R69h/R6Ah) ....................................................................................71
GAMMA CONTROL (R70h to R78h).........................................................................................................72
2
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
INSTRUCTION SET INITIALIZATION .............................................................................................................. 73
PATTERN DIAGRAMS FOR VOLTAGE SETTING.......................................................................................... 74
VOLTAGE REGULATION FUNCTION ............................................................................................................. 75
SYSTEM INTERFACE...................................................................................................................................... 77
68-SYSTEM 18-BIT BUS INTERFACE..................................................................................................... 79
68-SYSTEM 16-BIT BUS INTERFACE..................................................................................................... 80
68-SYSTEM 9-BIT BUS INTERFACE....................................................................................................... 81
68-SYSTEM 8-BIT BUS INTERFACE....................................................................................................... 82
80-SYSTEM 18-BIT BUS INTERFACE..................................................................................................... 83
80-SYSTEM 16-BIT BUS INTERFACE..................................................................................................... 84
80-SYSTEM 9-BIT BUS INTERFACE....................................................................................................... 85
80-SYSTEM 8-BIT BUS INTERFACE....................................................................................................... 86
68-/80-SYSTEM 8-/9-BIT INTERFACE SYNCHRONIZATION FUNCTION ............................................. 87
SERIAL PERIPHERAL INTERFACE ........................................................................................................ 88
INDEX AND PARAMETER RECOGNITION............................................................................................. 90
18-Bit RGB interface ................................................................................................................................. 92
16-Bit RGB interface ................................................................................................................................. 92
6-Bit RGB interface ................................................................................................................................... 93
USAGE ON EXTERNAL DISPLAY INTERFACE ............................................................................................. 96
INTRODUCTION OF MDDI .............................................................................................................................. 97
DATA-STB ENCODING.................................................................................................................................... 97
MDDI DATA / STB ............................................................................................................................................ 98
HIBERNATION / WAKE-UP.............................................................................................................................. 99
MDDI LINK WAKE-UP PROCEDURE ............................................................................................................ 100
1) Host-initiated Link Wake-up Procedure .............................................................................................. 102
VSYNC Based Link Wake-up.................................................................................................................. 105
GPIO Based Link Wake-up ..................................................................................................................... 106
GPIO CONTROL............................................................................................................................................. 108
MDDI PACKET................................................................................................................................................ 111
Sub-frame header packet........................................................................................................................ 111
Register access packet ........................................................................................................................... 112
Video Stream packet ............................................................................................................................... 112
Filler packet ............................................................................................................................................. 113
Link shutdown packet.............................................................................................................................. 113
TEARING-LESS DISPLAY ............................................................................................................................. 116
1. 1. Display speed is faster than data write........................................................................................ 116
2. Display speed is slower than data write. ............................................................................................. 116
MAIN / SUB PANEL SELECTION .................................................................................................................. 118
SUB PANEL CONTROL TIMING.................................................................................................................... 119
1. TFT type sub panel timing................................................................................................................... 119
1.1 Register data transfer timing ............................................................................................................. 119
1.2 Video data transfer timing ................................................................................................................. 120
2. STN type sub panel timing .................................................................................................................. 123
2.1 Register data transfer timing ............................................................................................................. 123
2.2 Video data transfer timing ................................................................................................................. 124
SUB PANEL CONTROL TIMING.................................................................................................................... 125
1. Index/parameter write for sub panel LDI ............................................................................................. 125
2. Image data write for sub panel LDI ..................................................................................................... 125
3. Change data path from sub panel to main panel ................................................................................ 125
ABSOLUTE MAXIMUM RATINGS ................................................................................................................. 143
3
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
DC CHARACTERISTICS ................................................................................................................................144
AC CHARACTERISTICS ................................................................................................................................149
RESET TIMING...............................................................................................................................................153
EXTERNAL POWER ON / OFF SEQUENCE.................................................................................................154
NOTICE ...........................................................................................................................................................155
4
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
INTRODUCTION
The S6E63D6 is a single chip solution for Gate-IC-less AMOLED panel. Source driver with built-in memory,
gate-IC-less level shifter and power circuits are integrated on this LSI. It can display to the maximum of 240-RGB x
320-dot graphics on 260k-color AMOLED panel. Moreover, the chip supports LTPS panel.
The S6E63D6 supports Qualcomm’s high-speed serial interface, MDDI (Mobile Display Digital Interface) type I,
which is an implementation of client device Video Electronics Standards Association (VESA) standard.
The MDDI is a cost-effective low-power solution that enables high-speed short-range communication with a display
device using a digital packet data link.
The S6E63D6 also supports 18-/16-/9-/8-bit high-speed bus interface to enable efficient data transfer to the GRAM.
There is an external interface. In case of display data, the S6E63D6 offers a flexible 18-/16-/6-bits bus of RGB
interface for transferring the 260k colors display data.
The motion picture area can be designated in GRAM by window function. The specified window area can be
updated selectively so that motion picture can be displayed simultaneously independent of still picture area.
The LSI operates at low voltage and has internal GRAMs to store 240-RGB x 320-dot 260k-color image data.
Additionally, it has an internal booster that generates the OLED driving voltage and the voltage follower circuit for
OLED driver.
The S6E63D6 is suitable for any medium-sized or small portable mobile solution requiring long-term driving
capabilities such as digital cellular phones supporting a web browser, bi-directional pagers, PMP, MP3P and small
PDAs.
5
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
FEATURES
Overalls
− 240-RGBx320-dot AM-OLED display controller/driver IC for 262,144 colors
− Gate IC less
− 240 channel source driver with time shared driving function
Various color-display control functions
− 262,144 colors can be displayed at the same time with RGB separated gamma adjust.
− 262,144 / 65,536/ 8 colors can be displayed.
− Vertical scroll display function in line units
Various interfaces
− 18-/16-/9-/8-bit high-speed parallel bus interface (80- and 68- system)
− Serial peripheral interface (SPI)
− 18-/16-/6-bit RGB interface
− MDDI (Mobile Display Digital Interface) support
Internal ram capacity: 240 x 18 x 320 = 1,382,400 bits
Writing to a window-ram address area by using a window-address function
Efficiently panel driving signals
−
−
SOUT[1:240] : V0~V63 grayscale
FLM, SFTCLK, SFTCLKB, SCLK1, SCLK2, CLA, CLB, CLC, BICTL_L, BICTL_R, EX_FLM, EX_CLK,
EX_CLKB, ESR : VGL to VGH level
Low-power operation supports:
− Power-save mode: standby mode
− Partial display mode in any position
Internal oscillation circuit and external hardware reset
Internal power supply circuit
Operating voltage
• Apply voltage
− I/O power-supply VDD3 to VSS = 1.65 to 3.3V
− Analog power-supply VCI to VSS = 2.5 to 3.3V
• Generated voltage
− VGH = 4.6 to 6.6V (gate circuit power supply)
− VGL = -7.8 to -5.0V (gate circuit power supply)
− VINT = - 4.0 to -1.0V (OLED pixel initialization first power supply)
− Source output range = 0.96 to 4.2V
Released package type
−
6
S6E63D6 is released COG type package format only.
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
BLOCK DIAGRAM
Figure1: S6E63D6 Block Diagram
7
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
PAD CONFIGURATION
Figure2: Pad Configuration
8
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table1: S6E63D6 Pad Dimensions
Size
Items
Pad name.
Chip size
(With scribe lane; 80um)
-
Chip thickness
-
300
Input pad
60
Output pad
54
Bump pitch
Input pad
(1-251)
Output pad
(264-539)
Output pad
(252-263, 540-551)
Pad size
Bump Height
All PADs
X
Y
15,580
1,330
30
91
36
91
91
36
Unit
um
15 ± 3
Pitch
Y
OUTPUT BUMP
X
Y
PITCH
X
INPUT BUMP
9
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
ALIGN KEY CONFIGURATION AND COORDINATE
Figure3: COG Align Key
10
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
PAD CENTER COORDINATES
Table2: Pad Center Coordinates
[Unit: um]
NO
NAME
X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DUMMY
MTPG
MTPD
VCI
VCI
VCI
VCI
VCI
VCI1
VCI1
VCI1
VCI1
VCI1
VSSC
VSSC
VSSC
VSSC
VSSC
VSSC
C12M
C12M
C12M
C12P
C12P
C12P
C11M
C11M
C11M
C11P
C11P
C11P
VLOUT1
VLOUT1
VLOUT1
VLOUT1
VLOUT1
VLOUT1
VLIN1
VLIN1
VLIN1
VLIN1
VLIN1
VLIN1
C31P
C31P
C31P
C31M
C31M
C31M
C32P
-7500.0
-7440.0
-7380.0
-7320.0
-7260.0
-7200.0
-7140.0
-7080.0
-7020.0
-6960.0
-6900.0
-6840.0
-6780.0
-6720.0
-6660.0
-6600.0
-6540.0
-6480.0
-6420.0
-6360.0
-6300.0
-6240.0
-6180.0
-6120.0
-6060.0
-6000.0
-5940.0
-5880.0
-5820.0
-5760.0
-5700.0
-5640.0
-5580.0
-5520.0
-5460.0
-5400.0
-5340.0
-5280.0
-5220.0
-5160.0
-5100.0
-5040.0
-4980.0
-4920.0
-4860.0
-4800.0
-4740.0
-4680.0
-4620.0
-4560.0
Y
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
NO
NAME
X
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
C32P
C32P
DUMMYL3
DUMMYL2
DUMMYL1
C32M
C32M
C32M
VLOUT3
VLOUT3
VLOUT3
VLOUT3
VLOUT3
VLIN3
VLIN3
VLIN3
VLIN3
VLIN3
DUMMY
DUMMY
VLIN2
VLIN2
VLIN2
VLIN2
VLIN2
VLOUT2
VLOUT2
VLOUT2
VLOUT2
VLOUT2
C21P
C21P
C21P
DUMMY
DUMMY
C21M
C21M
C21M
V0
V0
V63
V63
VGS
VGS
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
-4500.0
-4440.0
-4380.0
-4320.0
-4260.0
-4200.0
-4140.0
-4080.0
-4020.0
-3960.0
-3900.0
-3840.0
-3780.0
-3720.0
-3660.0
-3600.0
-3540.0
-3480.0
-3420.0
-3360.0
-3300.0
-3240.0
-3180.0
-3120.0
-3060.0
-3000.0
-2940.0
-2880.0
-2820.0
-2760.0
-2700.0
-2640.0
-2580.0
-2520.0
-2460.0
-2400.0
-2340.0
-2280.0
-2220.0
-2160.0
-2100.0
-2040.0
-1980.0
-1920.0
-1860.0
-1800.0
-1740.0
-1680.0
-1620.0
-1560.0
Y
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
NO
NAME
X
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RTEST
VSS_MDDI
VSS_MDDI
VSS_MDDI
VSS_MDDI
MDP
MDP
MDP
MDN
MDN
MDN
MSP
MSP
MSP
MSN
MSN
MSN
VCI_MDDI
VCI_MDDI
VCI_MDDI
VCI_MDDI
Vtest
Vtest
VDD3
VDD3
VDD3
VDD3
VDD3
FUSE_EN
S_PB
VSSDUM
ID_MIB
VDD3DUM
MDDI_EN
TEST_MODE[1]
TEST_MODE[0]
-1500.0
-1440.0
-1380.0
-1320.0
-1260.0
-1200.0
-1140.0
-1080.0
-1020.0
-960.0
-900.0
-840.0
-780.0
-720.0
-660.0
-600.0
-540.0
-480.0
-420.0
-360.0
-300.0
-240.0
-180.0
-120.0
-60.0
0.0
60.0
120.0
180.0
240.0
300.0
360.0
420.0
480.0
540.0
600.0
660.0
720.0
780.0
840.0
900.0
960.0
1020.0
1080.0
1140.0
1200.0
1260.0
1320.0
1380.0
1440.0
Y
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
11
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table3: Pad Center Coordinates (continued)
[Unit: um]
NO
NAME
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
EXCLK
EN_EXCLK
TEST_IN[6]
TEST_IN[5]
TEST_IN[4]
TEST_IN[3]
TEST_IN[2]
TEST_IN[1]
TEST_IN[0]
VSSDUM
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
VSSDUM
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VSSDUM
VSYNC
HSYNC
DOTCLK
ENABLE
SDI
SDO
CSB
RW_WRB
RS
VDD3DUM
E_RDB
RESETB
TE
TEST_OUT[2]
TEST_OUT[1]
TEST_OUT[0]
VDD
VDD
VDD
VDD
12
X
1500.0
1560.0
1620.0
1680.0
1740.0
1800.0
1860.0
1920.0
1980.0
2040.0
2100.0
2160.0
2220.0
2280.0
2340.0
2400.0
2460.0
2520.0
2580.0
2640.0
2700.0
2760.0
2820.0
2880.0
2940.0
3000.0
3060.0
3120.0
3180.0
3240.0
3300.0
3360.0
3420.0
3480.0
3540.0
3600.0
3660.0
3720.0
3780.0
3840.0
3900.0
3960.0
4020.0
4080.0
4140.0
4200.0
4260.0
4320.0
4380.0
4440.0
Y
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
NO
NAME
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
MVDD
MVDD
MVDD
MVDD
RVDD
RVDD
RVDD
RVDD
DUMMY
VSP
VSP
VSP
VSP
VREG1OUT
VREG1OUT
VREG1OUT
VREG1OUT
VCI
VCI
VCI
VCI
VCI
VCIRIN
DUMMYR3
DUMMYR2
DUMMYR1
VGH
VGH
VGH
VGH
VGH
DUMMY
VGL
VGL
VGL
VGL
VGL
VINT
VINT
VINT
VINT
VINT
VINT
VINT
DUMMY
EL_ON
ELVDD
ELVDD
ELVDD
ELVDD
X
4500.0
4560.0
4620.0
4680.0
4740.0
4800.0
4860.0
4920.0
4980.0
5040.0
5100.0
5160.0
5220.0
5280.0
5340.0
5400.0
5460.0
5520.0
5580.0
5640.0
5700.0
5760.0
5820.0
5880.0
5940.0
6000.0
6060.0
6120.0
6180.0
6240.0
6300.0
6360.0
6420.0
6480.0
6540.0
6600.0
6660.0
6720.0
6780.0
6840.0
6900.0
6960.0
7020.0
7080.0
7140.0
7200.0
7260.0
7320.0
7380.0
7440.0
Y
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
-572.5
NO
NAME
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
EX_FLM
EX_FLM
EX_CLKB
EX_CLKB
EX_CLK
EX_CLK
BICTL_R
BICTL_R
ESR
ESR
CLA
CLA
CLB
CLB
CLC
CLC
DUMMY
DUMMY
SOUT_DUM1
SOUT[1]
SOUT[2]
SOUT[3]
SOUT[4]
SOUT[5]
SOUT[6]
SOUT[7]
SOUT[8]
SOUT[9]
SOUT[10]
SOUT[11]
SOUT[12]
SOUT[13]
SOUT[14]
SOUT[15]
SOUT[16]
SOUT[17]
X
7500.0
7697.5
7697.5
7697.5
7697.5
7697.5
7697.5
7697.5
7697.5
7697.5
7697.5
7697.5
7697.5
7425.0
7371.0
7317.0
7263.0
7209.0
7155.0
7101.0
7047.0
6993.0
6939.0
6885.0
6831.0
6777.0
6723.0
6669.0
6615.0
6561.0
6507.0
6453.0
6399.0
6345.0
6291.0
6237.0
6183.0
6129.0
6075.0
6021.0
5967.0
5913.0
5859.0
5805.0
5751.0
5697.0
5643.0
5589.0
5535.0
5481.0
Y
-572.5
-296.0
-242.0
-188.0
-134.0
-80.0
-26.0
28.0
82.0
136.0
190.0
244.0
298.0
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table4: Pad Center Coordinates (continued)
[Unit: um]
NO
NAME
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
SOUT[18]
SOUT[19]
SOUT[20]
SOUT[21]
SOUT[22]
SOUT[23]
SOUT[24]
SOUT[25]
SOUT[26]
SOUT[27]
SOUT[28]
SOUT[29]
SOUT[30]
SOUT[31]
SOUT[32]
SOUT[33]
SOUT[34]
SOUT[35]
SOUT[36]
SOUT[37]
SOUT[38]
SOUT[39]
SOUT[40]
SOUT[41]
SOUT[42]
SOUT[43]
SOUT[44]
SOUT[45]
SOUT[46]
SOUT[47]
SOUT[48]
SOUT[49]
SOUT[50]
SOUT[51]
SOUT[52]
SOUT[53]
SOUT[54]
SOUT[55]
SOUT[56]
SOUT[57]
SOUT[58]
SOUT[59]
SOUT[60]
SOUT[61]
SOUT[62]
SOUT[63]
SOUT[64]
SOUT[65]
SOUT[66]
SOUT[67]
X
5427.0
5373.0
5319.0
5265.0
5211.0
5157.0
5103.0
5049.0
4995.0
4941.0
4887.0
4833.0
4779.0
4725.0
4671.0
4617.0
4563.0
4509.0
4455.0
4401.0
4347.0
4293.0
4239.0
4185.0
4131.0
4077.0
4023.0
3969.0
3915.0
3861.0
3807.0
3753.0
3699.0
3645.0
3591.0
3537.0
3483.0
3429.0
3375.0
3321.0
3267.0
3213.0
3159.0
3105.0
3051.0
2997.0
2943.0
2889.0
2835.0
2781.0
Y
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
NO
NAME
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
SOUT[68]
SOUT[69]
SOUT[70]
SOUT[71]
SOUT[72]
SOUT[73]
SOUT[74]
SOUT[75]
SOUT[76]
SOUT[77]
SOUT[78]
SOUT[79]
SOUT[80]
SOUT[81]
SOUT[82]
SOUT[83]
SOUT[84]
SOUT[85]
SOUT[86]
SOUT[87]
SOUT[88]
SOUT[89]
SOUT[90]
SOUT[91]
SOUT[92]
SOUT[93]
SOUT[94]
SOUT[95]
SOUT[96]
SOUT[97]
SOUT[98]
SOUT[99]
SOUT[100]
SOUT[101]
SOUT[102]
SOUT[103]
SOUT[104]
SOUT[105]
SOUT[106]
SOUT[107]
SOUT[108]
SOUT[109]
SOUT[110]
SOUT[111]
SOUT[112]
SOUT[113]
SOUT[114]
SOUT[115]
SOUT[116]
SOUT[117]
X
2727.0
2673.0
2619.0
2565.0
2511.0
2457.0
2403.0
2349.0
2295.0
2241.0
2187.0
2133.0
2079.0
2025.0
1971.0
1917.0
1863.0
1809.0
1755.0
1701.0
1647.0
1593.0
1539.0
1485.0
1431.0
1377.0
1323.0
1269.0
1215.0
1161.0
1107.0
1053.0
999.0
945.0
891.0
837.0
783.0
729.0
675.0
621.0
567.0
513.0
459.0
405.0
351.0
297.0
243.0
189.0
135.0
81.0
Y
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
NO
NAME
X
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
SOUT[118]
SOUT[119]
SOUT[120]
SOUT[121]
SOUT[122]
SOUT[123]
SOUT[124]
SOUT[125]
SOUT[126]
SOUT[127]
SOUT[128]
SOUT[129]
SOUT[130]
SOUT[131]
SOUT[132]
SOUT[133]
SOUT[134]
SOUT[135]
SOUT[136]
SOUT[137]
SOUT[138]
SOUT[139]
SOUT[140]
SOUT[141]
SOUT[142]
SOUT[143]
SOUT[144]
SOUT[145]
SOUT[146]
SOUT[147]
SOUT[148]
SOUT[149]
SOUT[150]
SOUT[151]
SOUT[152]
SOUT[153]
SOUT[154]
SOUT[155]
SOUT[156]
SOUT[157]
SOUT[158]
SOUT[159]
SOUT[160]
SOUT[161]
SOUT[162]
SOUT[163]
SOUT[164]
SOUT[165]
SOUT[166]
SOUT[167]
27.0
-27.0
-81.0
-135.0
-189.0
-243.0
-297.0
-351.0
-405.0
-459.0
-513.0
-567.0
-621.0
-675.0
-729.0
-783.0
-837.0
-891.0
-945.0
-999.0
-1053.0
-1107.0
-1161.0
-1215.0
-1269.0
-1323.0
-1377.0
-1431.0
-1485.0
-1539.0
-1593.0
-1647.0
-1701.0
-1755.0
-1809.0
-1863.0
-1917.0
-1971.0
-2025.0
-2079.0
-2133.0
-2187.0
-2241.0
-2295.0
-2349.0
-2403.0
-2457.0
-2511.0
-2565.0
-2619.0
Y
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
13
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table5: Pad Center Coordinates (continued)
[Unit: um]
NO
NAME
X
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
SOUT[168]
SOUT[169]
SOUT[170]
SOUT[171]
SOUT[172]
SOUT[173]
SOUT[174]
SOUT[175]
SOUT[176]
SOUT[177]
SOUT[178]
SOUT[179]
SOUT[180]
SOUT[181]
SOUT[182]
SOUT[183]
SOUT[184]
SOUT[185]
SOUT[186]
SOUT[187]
SOUT[188]
SOUT[189]
SOUT[190]
SOUT[191]
SOUT[192]
SOUT[193]
SOUT[194]
SOUT[195]
SOUT[196]
SOUT[197]
SOUT[198]
SOUT[199]
SOUT[200]
SOUT[201]
SOUT[202]
SOUT[203]
SOUT[204]
SOUT[205]
SOUT[206]
SOUT[207]
SOUT[208]
SOUT[209]
SOUT[210]
SOUT[211]
SOUT[212]
SOUT[213]
SOUT[214]
SOUT[215]
SOUT[216]
SOUT[217]
-2673.0
-2727.0
-2781.0
-2835.0
-2889.0
-2943.0
-2997.0
-3051.0
-3105.0
-3159.0
-3213.0
-3267.0
-3321.0
-3375.0
-3429.0
-3483.0
-3537.0
-3591.0
-3645.0
-3699.0
-3753.0
-3807.0
-3861.0
-3915.0
-3969.0
-4023.0
-4077.0
-4131.0
-4185.0
-4239.0
-4293.0
-4347.0
-4401.0
-4455.0
-4509.0
-4563.0
-4617.0
-4671.0
-4725.0
-4779.0
-4833.0
-4887.0
-4941.0
-4995.0
-5049.0
-5103.0
-5157.0
-5211.0
-5265.0
-5319.0
14
Y
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
NO
NAME
X
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
SOUT[218]
SOUT[219]
SOUT[220]
SOUT[221]
SOUT[222]
SOUT[223]
SOUT[224]
SOUT[225]
SOUT[226]
SOUT[227]
SOUT[228]
SOUT[229]
SOUT[230]
SOUT[231]
SOUT[232]
SOUT[233]
SOUT[234]
SOUT[235]
SOUT[236]
SOUT[237]
SOUT[238]
SOUT[239]
SOUT[240]
SOUT_DUM240
DUMMY
DUMMY
BICTI_L
BICTI_L
SCLK1
SCLK1
SCLK2
SCLK2
SFTCLK
SFTCLK
SFTCLKB
SFTCLKB
FLM
FLM
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
-5373.0
-5427.0
-5481.0
-5535.0
-5589.0
-5643.0
-5697.0
-5751.0
-5805.0
-5859.0
-5913.0
-5967.0
-6021.0
-6075.0
-6129.0
-6183.0
-6237.0
-6291.0
-6345.0
-6399.0
-6453.0
-6507.0
-6561.0
-6615.0
-6669.0
-6723.0
-6777.0
-6831.0
-6885.0
-6939.0
-6993.0
-7047.0
-7101.0
-7155.0
-7209.0
-7263.0
-7317.0
-7371.0
-7425.0
-7697.5
-7697.5
-7697.5
-7697.5
-7697.5
-7697.5
-7697.5
-7697.5
-7697.5
-7697.5
-7697.5
Y
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
572.5
298.0
244.0
190.0
136.0
82.0
28.0
-26.0
-80.0
-134.0
-188.0
-242.0
NO
NAME
X
551
DUMMY
-7697.5
Y
-296.0
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
PIN DESCRIPTION
POWER SUPPLY PINS
Table6: Power supply pin description
Symbol
I/O
Description
VDD
Power
Power supply for internal logic and internal RAM.
Internally, voltage regulator output is connected to this pin.
Connect a capacitor for stabilization.
Don’t apply any external power to this pin.
MVDD
Power
Internal power for RAM. Connect this pin to VDD externally.
RVDD
Power
Regulated logic power voltage (1.5V)
VDD3
Power
I/O power supply. (1.65V ~ 3.3V)
VCI
Power
Power supply for analog circuits. (VCI : 2.5 ~ 3.3V)
An internal reference power supply for VCI1 amp.
VCI_MDDI
Power
Analog power supply (VCI_MDDI : 2.5 ~ 3.3V)
VSS VSSA
VSSC
Ground
System ground (0V).
VSS_MDDI
Power
System ground level for I/O
VGS
I
VCI1
I/O
A reference level for the grayscale voltage generation circuit.
Connect this pin to an external resistor when a source driver is used to adjust grayscale
levels for each panel.
A reference voltage for 1st booster.
A reference voltage input pin for power block when using an external VCIR generation
mode.
VCIRIN
I
VLIN1 /
VLOUT1
I/O
Input pin for applying VLOUT1 voltage level /
1st booster output pin.
Recommend to connect VLIN1 to VLOUT1.
VLIN2 /
VLOUT2
I/O
Input pin for applying VLOUT2 voltage level /
2nd booster output pin.
Recommend to connect VLIN2 to VLOUT2.
VLIN3 /
VLOUT3
I/O
Input pin for applying VLOUT3 voltage level /
3rd booster output pin.
Recommend to connect VLIN3 to VLOUT3.
C11P,C11M
C12P,C12M
I/O
External capacitor connection pins used for the 1’st booster circuit.
C21P,C21M
I/O
External capacitor connection pins used for the 2nd booster circuit.
15
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table7: Power supply pin description(Continued)
Symbol
I/O
C31P,C31M
C32P,C32M
I/O
External capacitor connection pins used for the 3rd booster circuit.
VREG1OUT
I/O
A reference level for the grayscale voltage with the amplitude between VLOUT1 and GND.
VGH
O
The positive voltage used in the gate driver.
VGL
O
The negative voltage used in the gate driver.
VINT
O
A voltage for initializing an OLED panel.
VSP
O
Power supply for the external photo sensor.
If not use, this pin must be open.
ELVDD
I
Power supply for the generation of VSP.
If not use, this pin must be fixed to VSS level.
MTPG
I
A voltage for the MTP programming (Initialization, Erasing, and Programming).
If not use, this pin must be open.
MTPD
I
A voltage for the MTP programming (Initialization, Erasing, and Programming).
If not use, this pin must be open.
Vex
I
Must be fixed to VSS level.
16
Description
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SYSTEM / RGB INTERFACE PINS
Symbol
S_PB
I
MDDI_EN
I
ID_MIB
I
CSB
I
RS
I
RW_WRB/
SCL
Table8: System interface pin description
Description
I/O
I
Selects the CPU interface mode
“Low” = Parallel Interface, “High” = Serial Interface
Selects the MDDI interface
“Low” = MDDI Disable, “High” = MDDI Enable
Selects the CPU type
“Low” = Intel 80x-system, “High” = Motorola 68x-system
If S-PB = “High”, the pin is used as ID setting bit for a device code.
Chip select signal input pin.
Low: S6E63D6 is selected and can be accessed
High: S6E63D6 is not selected and cannot be accessed
Register select pin.
Low: Index/status, High: Instruction parameter, GRAM data
Must be fixed at VDD3 level when not used.
Pin function
CPU type
RW
68-system
WRB
80-system
Pin function
Serial Peripheral Interface
(SPI)
CPU type
E
68-system
RDB
80-system
SCL
E_RDB
I
Pin description
Read/Write operation selection pin.
Low: Write, High: Read
Write strobe signal. (Input pin)
Data is fetched at the rising edge.
The synchronous clock signal.
(Input pin)
Pin description
Read/Write operation enable pin.
Read strobe signal. (Input pin)
Read out data at the low level.
When SPI mode is selected, fix this pin at VDD3 level.
SDI
I
For a serial peripheral interface (SPI), input data is fetched at the rising edge of the SCL
signal. Fix SDI pin at VSS level if the pin is not used.
SDO
O
For a serial peripheral interface (SPI), serves as the serial data output pin (SDO). Successive
bits are output at the falling edge of the SCL signal.
RESETB
I
Reset pin Initializes the IC when low. Should be reset after power-on.
DB17-DB0
I/O
Bi-directional data bus.
When CPU I/F,
18-bit interface : DB 17-0
16-bit interface : DB 17-10, DB 8-1
9-bit interface : DB 8-0
8-bit interface : DB 8-1
When RGB I/F,
18-bit interface : DB 17-0
16-bit interface : DB 17-10, DB 8-1
6-bit interface : DB 8-3
Fix unused pin to the VSS level.
17
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Symbol
I/O
Table9: System interface pin description (Continued)
Description
Data enable signal pin for RGB interface.
EPL=”0”: Only in case of ENABLE=”Low”, the IC can be access via RGB interface.
EPL=”1”: Only in case of ENABLE=”High”, the IC can be access via RGB interface
EPL
ENABLE
GRAM write
0
0
Valid
0
1
Invalid
1
0
Invalid
1
1
Valid
Fix ENABLE pin at VSS level if the pin is not used.
ENABLE
I
VSYNC
I
Frame-synchronizing signal.
VSPL= “0”: Low active, VSPL=”1”: High active
Fix this pin at VSS level if the pin is not used.
HSYNC
I
Line-synchronizing signal.
HSPL=”0”: Low active, HSPL=”1”: High active
Fix this pin at VSS level if the pin is not used.
I
Input pin for clock signal of external interface: dot clock.
DPL=”0”: Display data is fetched at DOTCLK’s rising edge
DPL=”1”: Display data is fetched at DOTCLK’s falling edge
Fix this pin at VSS level if the pin is not used.
DOTCLK
18
GRAM address
Updated
Held
Held
Updated
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Tabel10: MDDI pin description
Symbol
I/O
Description
MDP
I/O
Positive MDDI data input/output. If MDDI is not used, this pad should be floating.
MDN
I/O
Negative MDDI data input/output. If MDDI is not used, this pad should be floating.
MSP
I
Positive MDDI strobe input. If MDDI is not used, this pad should be floating.
MSN
I
Negative MDDI strobe input. If MDDI is not used, this pad should be floating.
GPIO[9:0]
(DB[17:8])
I/O
General purpose input/output
If GPIO is not used in MDDI mode, this pin should be fixed at VSS level.
O
Chip select for Sub Panel Driver IC
Low: Sub Panel Driver IC is selected and can be accessed.
High: Sub Panel Driver IC is not selected and can not be accessed.
If sub panel is not used in MDDI mode, this pin should be floating
S_RS
(DB[6])
O
Register select for Sub Panel Driver IC
Low : Index/status, High : Control
Must be fixed at VSS level, when this signal is not used.
If sub panel is not used in MDDI mode, this pin should be floating
S_WRB
(DB[5])
O
Write Strobe signal for Sub Panel Driver IC
Only 80-system 18/16 bit mode is enabled, so Data is fetched at the rising edge.
If sub panel is not used in MDDI mode, this pin should be floating
S_DB[8-0]
(DB[4:0], TE,
TEST_OUT[2:0])
O
For Sub Panel, this pin can be used to transfer DB[8:0] data to Sub Panel Driver IC.
If sub panel is not used in MDDI mode, this pin should be floating.
HSYNC
VSYNC
ENABLE
DOTCLK
I
In MDDI mode, Fixed at VSS level.
RW_WRB
E_RDB
RS
I
In MDDI mode, Fixed at VDD3 level.
CSB
I
In MDDI mode, Fixed at VDD3 level.
S_CSB (DB[7])
19
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
DISPLAY PINS
Table11: Display pin description
Description
Source driver output pins.
The direction of them is determined by the value of SS register.
Symbol
I/O
SOUT[1:240]
O
FLM
O
Start pulse of vertical line shift.
SFTCLK,
SFTCLKB
O
Clock for gate driver shift.
SCLK1, SCLK2
O
LTPS signals
CLA, CLB, CLC
O
LTPS signals
BICTL_L
O
LTPS signal
BICTL_R
O
LTPS signal
EX_FLM
O
Don’t use this pin. IC maker’s test pins.
EX_CLK,
EX_CLKB
O
Don’t use this pin. IC maker’s test pins.
ESR
O
Shift register enable signal
EL_ON
O
The external ELVDD regulator enable pin
MISCELLANEOUS PINS
Table12: Oscillator and internal power regulator pin description
Symbol
I/O
Description
DUMMYR[3:1]
DUMMYL[3:1]
-
Contact resistance measurement pin. In normal operation, leave this pin open
DUMMY
-
Dummy pins don’t care. Leave these pins open.
V0/V63
O
Gamma voltage monitoring pin.
VDD3DUM
O
This pin is connected to VDD3 line internally. Use for to connect neighbor-setting pins.
VSSDUM
O
FUSE_EN
I
RTEST
I
EN_EXCLK
I
EXCLK
I
TEST_MODE[1:0]
I
TEST_IN[6:0]
I
TE
O
TEST_OUT[2:0]
O
This pin is connected to VSS line internally. Use for to connect neighbor-setting pins.
Don’t use this pin. IC maker’s test pins.
This pin must be tied to VDD3.
Don’t use this pin. IC maker’s test pins.
This pin must be tied to VSS.
Don’t use this pin. IC maker’s test pins.
Fix this pin at VSS level if the pin is not used.
Don’t use this pin. IC maker’s test pins.
Fix this pin at VSS level if the pin is not used.
Don’t use this pin. IC maker’s test pins.
Fix this pin at VSS level if the pin is not used.
Don’t use this pin. IC maker’s test pins.
Fix this pin at VSS level if the pin is not used.
Tearing effect output pin.
In normal operation, leave this pin open.
Output pins used only for test purpose at vendor-side.
In normal operation, leave this pin open.
20
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
FUNCTIONAL DESCRIPTION
SYSTEM INTERFACE
The S6E63D6 has ten high-speed system interfaces: an 80-system 18-/16-/9-/8-bit bus, a 68-system 18-/16-/9-/8-bit
and two type serial interface (SPI: Serial Peripheral Interface).
The S6E63D6 has three 18-bit registers: an index register (IR), a write data register (WDR), and a read data register
(RDR). The IR stores index information for control register and GRAM. The WDR temporarily stores data to be
written into control register and GRAM. The RDR temporarily stores data read from GRAM. Data written into the
GRAM from CPU is initially written to the WDR and then written to the GRAM automatically. Data is read through the
RDR when reading from the GRAM, and the first read data is invalid and the second and the following data are valid.
Execution time for instruction, except oscillation start, is 0-clock cycle so that instructions can be written in
succession.
SYSTEM
68
80
RW_WRB
0
1
0
1
0
1
0
1
CSB
0
1
R/W bit
0
1
0
1
Table13: Register Selection (18-/16-/9-/8- Parallel Interface)
E_RDB
RS
Operations
1
0
Write index to IR
1
0
Read internal status
1
1
Write to control register and GRAM through WDR
1
1
Read from GRAM through RDR
1
0
Write index to IR
0
0
Read internal status
1
1
Write to control register and GRAM through WDR
0
1
Read from GRAM through RDR
Table14: CSB signal (GRAM update control)
Operation
Data is written to GRAM, GRAM address is updated
Data is not written to GRAM, GRAM address is not updated
Table15: Register Selection (Serial Peripheral Interface)
RS bit
Operation
0
Write index to IR
0
Read internal status
1
Write data to control register and GRAM through WDR
1
Read data from GRAM through RDR
21
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
HIGH SPEED SERIAL INTERFACE (MDDI)
This interface will be introduced, see the section “Description of MDDI Interface”
SUB PANEL CONTROL
Sub panel control block will be introduced, see the section “Description of Sub Panel Control”
EXTERNAL INTERFACE (RGB-I/F)
The S6E63D6 incorporates RGB interface as external interface for motion picture display.
When the RGB interface is selected, the synchronization signals (VSYNC, HSYNC, and DOTCLK) are available for
display. The RGB data for display (DB17-0) are written according to enable signal (ENABLE) in synchronization with
VSYNC, HSYNC, and DOTCLK signal. This allows flicker-free updating of the screen. See the section on the
EXTERNAL DISPLAY INTERFACE.
ADDRESS COUNTER (AC)
The address counter (AC) assigns address to GRAM. When an address-set-instruction is written to the IR, the
address information is sent from IR to AC. After writing to the GRAM, the address value of AC is automatically
increased/ decreased by 1 according to ID1-0 bit of control register. After reading data from GRAM, the AC is
updated automatically.
GRAPHICS RAM (GRAM)
The graphics RAM (GRAM) has 18-bits/pixel and stores the bit-pattern data for 240-RGB x 320-dot display.
TIMING GENERATOR
The Panel Interface Controller generates timing signals for LTPS drive. Also it generates control signals for the
operation of internal circuits such as source driver and GRAM. The GRAM read operations done by this Timing
Generator and GRAM write operations done through system interface are performed independently to avoid the
interference between them.
GRAYSCALE VOLTAGE GENERATOR
The grayscale voltage circuit generates OLED driving voltage that corresponds to the grayscale levels as specified
in the grayscale gamma-adjusting registers. 262,144 possible colors can be displayed at the same time by this LSI.
Gamma is set for R,G, and B individually.
OSCILLATION CIRCUIT (OSC)
The S6E63D6 can provide R-C oscillation simply through the internal oscillation-resistor. The appropriate oscillation
frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the internal register.
Since R-C oscillation stops during the standby mode, current consumption can be reduced. For details, see the
OSCILLATION CIRCUIT section.
22
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SOURCE DRIVER CIRCUIT
The source driving circuit of S6E63D6 consists of a 240 source drivers (SOUT[1] to SOUT[240]). Image data is
latched when 240-pixel data has arrived. The latched data then enables the source drivers to generate drive
waveform outputs.
The SS register can change the shift direction of 240 source driver output data for the device-mount configuration.
LTPS PANEL INTERFACE CIRCUIT
LTPS panel interface circuit does level–shift operation and outputs to control LTPS panel.
23
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
GRAM ADDRESS MAP
The image data stored in GRAM corresponds to pixel data on display as shown below:
Figure4: GRAM address (SS=”0”)
Figure5: GRAM address (SS=”1” )
24
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
INSTRUCTIONS
The S6E63D6 uses the 18-bit bus architecture. Before the internal operation of the S6E63D6 starts, control
information is stored temporarily in the registers described below to allow high-speed interfacing with a
high-performance microcomputer. The internal operation of the S6E63D6 is determined by signals sent from the
microcomputer. These signals, which include the register selection signal (RS), the read/write signal (R/W), and the
data bus signals (DB17 to DB0), make up the S6E63D6 instructions.
There are seven categories of instructions that:
-
Specify the index
Control the display
Control power management
Set internal GRAM addresses
Transfer data to and from the internal GRAM
Set grayscale level for the internal grayscale palette table
Interface with the LTPS driver and power supply IC
Normally, instructions that write data are used the most. However, an auto-update of internal GRAM addresses after
each data write can lighten the microcomputer program load. As instructions are executed in 0 cycles, they can be
written in succession.
The 16-bit instruction assignment differs from interface-setup (18-/16-/9-/8-/SPI), so instructions should be fetched
according to the data format shown below:
68/80-system 18-bit Interface
INPUT DATA
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
DB
0
68/80-system 16-bit Interface/SPI(Serial Peripheral Interface)
INPUT DATA
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
25
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
68/80-system 9-bit Interface
1st Transmission
2nd Transmission
INPUT DATA
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
DB
0
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
68/80-system 8-bit Interface
1st Transmission
2nd Transmission
INPUT DATA
DB
17
8
DB
16
7
DB
15
6
DB
14
5
DB
13
4
DB
12
3
DB
11
2
DB
10
1
DB
DB
17
8
DB
DB
16
7
DB
DB
15
6
DB
DB
14
5
DB
DB
13
4
DB
DB
12
3
DB
DB
11
2
DB
DB
10
1
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
26
DB
0
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
INSTRUCTION TABLE
Table16: Instruction Table
Reg.
Index
I/F
Control
Display
Control
Device
Read
Power
Control
R/W RS
No
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
IR
W
0
Set index register value
X
X
X
X
X
X
X
X
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
SR
R
0
Status Read
X
X
X
X
X
X
X
L8
L7
L6
L5
L4
L3
L2
L1
L0
R0h
W
0
No Operation
R01h
W
1
Display Duty control
R02h
W
1
RGB Interface Control
R03h
W
1
Entry Mode
R04h
W
1
R05h
W
R06h
No operation
FP3
FP2
FP1
FP0
BP3
BP2
BP1
BP0
X
X
NL5
NL4
NL3
NL2
NL1
NL0
X
X
X
X
X
X
X
RM
DM
X
RIM1
RIM0
VSPL
HSPL
EPL
DPL
CLS
MDT1
MDT0
BGR
X
X
X
SS
X
X
I/D1
I/D0
X
X
X
AM
Clock Control
X
X
X
X
X
X
X
X
X
X
DCR1
DCR0
X
X
X
X
1
Display Control1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DISP_O
N
W
1
Display Control2
X
X
X
X
X
X
X
X
X
X
X
CL
X
X
TEMON
REV
R07h
W
1
Panel IF Control1
X
X
X
CLWEA CLWEA CLWEA CLWEA CLWEA
4
3
2
1
0
X
X
X
X
X
X
X
X
R08h
W
1
Panel IF Control2
X
X
X
CLWEB CLWEB CLWEB CLWEB CLWEB
4
3
2
1
0
X
X
X
R09h
W
1
Panel IF Control3
SCTE3 SCTE2 SCTE1 SCTE0 SCWE3 SCWE2 SCWE1 SCWE0
X
SHE2
SHE1
SHE0
X
CLTE2
R0Ah
W
1
Panel IF Control4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R0Fh
R
0
Device code read
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
R10h
W
1
Stand By
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
STB
R12h
W
1
Power Gen1
X
X
X
X
X
X
X
X
X
X
X
X
VC3
VC2
VC1
VC0
R13h
W
Power Gen2
X
X
VINT3
VINT2
VINT1
VINT0
X
VGH3
VGH2
VGH1
VGH0
X
VGL3
VGL2
VGL1
VGL0
R14h
W
1
Power Step Up Control1
X
DC22
DC21
DC0
DC12
DC11
DC10
X
X
X
X
X
X
BT1
BT0
R18h
W
1
Oscillator Control
X
X
X
X
X
X
X
X
X
X
RADJ5 RADJ4 RADJ3 RADJ2 RADJ1 RADJ0
R1Ah
W
1
Source Driver Control
X
X
X
X
X
X
X
X
X
X
GAMM
SDUM_
A_TES
ON
T
R20h
W
1
X
X
X
X
X
X
X
X
AD7
AD6
AD5
R21h
W
1
X
X
X
X
X
X
X
AD16
AD15
AD14
AD13
W
1
GRAM Write
WD17-0 : Pin assignment varies according to the interface method
R
1
GRAM Read
RD17-0 : Pin assignment varies according to the interface method
1
CLWEC CLWEC CLWEC CLWEC CLWeC
4
3
2
1
0
CLTE1
CLTE0
GTCON GTCON
1
0
X
SAP2
SAP1
SAP0
AD4
AD3
AD2
AD1
AD0
AD12
AD11
AD10
AD9
AD8
GRAM address set
AD16-0: Set GRAM
GRAM
IB
15
Access
R22h
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table17: Instruction Table(Continued)
Reg.
Index
R23h
W
IB
14
IB
13
IB
12
IB
11
IB
10
0
I/F
Control
IB
15
R/W RS
No
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Select 18/16-Bit Data Bus Interface
I/F Select
R24h
W
0
R30h
W
1
Select 9/8-Bit Data Bus Interface
X
X
X
X
X
X
X
SSA8
SSA7
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSA0
X
X
X
X
X
X
X
SEA8
SEA7
SEA6
SEA5
SEA4
SEA3
SEA2
SEA1
SEA0
X
X
X
X
X
X
X
SST8
SST7
SST6
SST5
SST4
SST3
SST2
SST1
SST0
X
X
X
X
X
X
X
SS18
SS17
SS16
SS15
SS14
SS13
SS12
SS11
SS10
X
X
X
X
X
X
X
SE18
SE17
SE16
SE15
SE14
SE13
SE12
SE11
SE10
X
X
X
X
X
X
X
VSA8
VSA7
VSA6
VSA5
VSA4
VSA3
VSA2
VSA1
VSA0
X
X
X
X
X
X
X
VEA8
VEA7
VEA6
VEA5
VEA4
VEA3
VEA2
VEA1
VEA0
HSA7
HSA6
HSA5
HSA4
HSA3
HSA2
HSA1
HSA0
HEA7
HEA6
HEA5
HEA4
HEA3
HEA2
HEA1
HEA0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VWAKE
_EN
WKL8
WKL7
WKL6
WKL5
WKL4
WKL3
WKL2
WKL1
WKL0
X
WKF3
WKF2
WKF1
WKF0
X
X
X
X
X
X
X
X
X
X
SUB_S SUB_S SUB_S SUB_S SUB_S SUB_S SUB_S SUB_S
EL7
EL 6
EL 5
EL 4
EL 3
EL 2
EL 1
EL 0
X
X
X
X
X
X
X
X
SUB_W SUB_W SUB_W SUB_W SUB_W SUB_W SUB_W SUB_W
R7
R6
R5
R4
R3
R2
R1
R0
X
X
X
X
X
X
X
X
FCV_E
N
Vertical Scroll Control
Position
Control
MDDI
I/F
R31h
W
1
R32h
W
1
R33h
W
1
R34h
W
1
R35h
W
1
R36h
W
1
R37h
W
1
38h
W
39h
W
3Ah
W
3Bh
W
1
3C
W
1
28
1
Vertical Scroll Control 2
Partial Screen Driving
Position
Vertical RAM Address
Position
Horizontal RAM Address
Position
Client initiated wake-up
1
MDDI Link wake-up start
position
1
Sub panel control
X
X
X
MPU_M STN_E
ODE
N
SUB_I
M1
SUB_I
M0
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table19: Instruction Table(Continued)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Test Key
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
1
MTP Selection
X
X
X
X
X
X
X
MTP_W
RB
X
X
X
MTP_S
EL
X
X
X
MTP_E
RB
W
1
MTP Register Setting R
X
R21_D
K2
R21_D
K1
X
R63_D
K3
R63_D
K2
R63_D
K1
R63h
W
1
MTP Register Setting G
X
G21_D G21_D G21_D
K2
K1
K0
G21_B
T0
X
G63_D G63_D G63_D G63_D
K3
K2
K1
K0
R64h
W
1
MTP Register Setting B
X
B21_D
K2
B21_D
K1
B21_D B21_BT B21_BT B21_BT
K0
2
1
0
X
B63_D
K3
B63_D
K2
B63_D
K1
R65h
W
1
MTP Register Offset
X
X
X
X
X
X
X
X
X
X
X
X
X
R66h
W
1
GPIO value
X
X
X
X
X
X
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
R67h
W
1
in/output control
X
X
X
X
X
X
GPIO_
CON9
GPIO_
CON8
GPIO_
CON7
GPIO_
CON6
GPIO_
CON5
GPIO_
CON4
GPIO_
CON3
GPIO_
CON2
GPIO_
CON1
GPIO_
CON0
R68h
W
1
GPIO Clear
X
X
X
X
X
X
GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR
9
8
7
6
5
4
3
2
1
0
R69h
W
1
GPIO interrupt enable
X
X
X
X
X
X
GPIO_
EN9
R6Ah
W
1
GPIO polarity selection
X
X
X
X
X
X
GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL
9
8
7
6
5
4
3
2
1
0
R70h
W
1
Gamma Top Bottom
Control R
X
X
CR56
CR55
CR54
CR53
CR52
CR51
CR50
X
X
X
CR03
CR02
CR01
CR00
R71h
W
1
Gamma Top Bottom
Control G
X
X
CG56
CG55
CG54
CG53
CG52
CG51
CG50
X
X
X
CG03
CG02
CG01
CG00
R72h
W
1
Gamma Top Bottom
Control B
X
X
CB56
CB55
CB54
CB53
CB52
CB51
CB50
X
X
X
CB03
CB02
CB01
CB00
R73h
W
1
Gamma Control R 1,2
X
X
CR15
CR14
CR13
CR12
CR11
CR10
X
X
CR25
CR24
CR23
CR22
CR21
CR20
R74h
W
1
Gamma Control R 3,4
X
X
CR35
CR34
CR33
CR32
CR31
CR30
X
X
CR45
CR44
CR43
CR42
CR41
CR40
R75h
W
1
Gamma Control G 1,2
X
X
CG15
CG14
CG13
CG12
CG11
CG10
X
X
CG25
CG24
CG23
CG22
CG21
CG20
R76h
W
1
Gamma Control G 3,4
X
X
CG35
CG34
CG33
CG32
CG31
CG30
X
X
CG45
CG44
CG43
CG44
CG41
CG40
R77h
W
1
Gamma Control B 1,2
X
X
CB15
CB14
CB13
CB12
CB11
CB10
X
X
CB25
CB24
CB23
CB22
CB21
CB20
R78h
W
1
Gamma Control B 3,4
X
X
CB35
CB34
CB33
CB32
CB31
CB30
X
X
CB45
CB44
CB43
CB42
CB41
CB40
R80h
W
1
Gamma Select
X
X
X
X
X
X
X
X
X
X
X
X
Reg.
R/W
RS
R60h
W
1
R61h
W
R62h
Index
No
MTP
Control
GPIO
Control
Gamma
Control
R21_D R21_BT R21_BT R21_BT
K0
2
1
0
G21_B
T2
G21_B
T1
GPIO_
EN8
GPIO_
EN7
GPIO_
EN6
GPIO_
EN5
R63_D R63_BT R63_BT R63_BT R63_BT
K0
3
2
1
0
G63_B
T3
G63_B
T2
G63_B
T1
G63_B
T0
B63_D B63_BT B63_BT B63_BT B63_BT
K0
3
2
1
0
GPIO_
EN4
GPIO_
EN3
E_OST E_OST E_OST
2
1
_0
GPIO_
EN2
GPIO_
EN1
GPIO_
EN0
GS_SE GS_SE GS_SE GS_SE
L3
L2
L1
L0
29
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Instruction Descriptions
Index
The index instruction specifies indexes. It sets the register number in the range of 0000000b to 1111111b in binary
form. However, do not access index registers and instruction bits that are not allocated in this document.
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W
0
X
X
X
X
X
X
X
X
X
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Status Read
The status read instruction reads out the internal status of the IC.
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
R
0
0
0
0
0
0
0
0
L8
L7
L6
L5
L4
L3
L2
L1
L0
IB6
IB5
IB4
IB3
IB2
IB1
IB0
L8–0: Indicate the position of horizontal line currently being driven.
No Operation (R00h)
R/W
RS
W
0
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
No Operation
This command does not have any effect on the display module. However it can be used to terminate Memory Write
and Read in 22h command.
30
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
DISPLAY DUTY CONTROL (R01h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W
1
FP3
FP2
FP1
FP0
BP3
BP2
BP1
BP0
X
X
NL5
NL4
NL3
NL2
NL1
NL0
*01h Initial Value = 1000_1000_XX10_1000
FP / BP
Sets the period of Blank Area, which is placed at the beginning and the end of a frame. FP[3:0] is for a Front Porch
and BP[3:0] is for a Back Porch. When Front Porch and Back Porch are set, the settings should meet the following
conditions.
BP+FP ≤TBD lines
FP ≥ TBD lines
BP ≥ TBD lines
When S6E63D6 operates in External Clock Operation mode, the Back Porch (BP) will start on the falling edge of the
VSYNC signal and display operation begins just after the Back Porch period. The Front Porch (FP) will start when
data of the number of lines specified by the NL has been displayed. During the period between the completion of the
Front Porch and the next VSYNC signal, the display will remain blank.
Table20: Blank Period Control with FP and BP
FP[3:0] (BP[3:0])
Number of Raster Periods In Front (Back) Porch
0000
SETTING DISABLE
0001
SETTING DISABLE
0010
2
0011
3
0100
4
---
---
1000
8
---
---
1100
12
1101
13
1110
14
1111
SETTING DISABLE
31
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
NL
Specifies the number of lines driving OLED drive. The number of lines for the OLED drive can be adjusted for every
eight lines. The selected value should be equal to or larger than the size of the panel to be driven. GRAM address
mapping is not affected by the value of the drive duty ratio.
Table21: NL and Drive Duty
Display Size
Drive Line
NL[5:0]
00_0000
01_0011
~
SETTING DISABLE
01_0100
240 X 160
160
01_0101
240 X168
168
01_0110
240X176
176
01_0111
240X184
184
---
---
10_0111
240 X 312
312
10_1000
240 X 320
320
---
10_1001
11_1111
~
SETTING DISABLE
[NOTE] A back porch period and a front porch period will be inserted as a blank period before and after
driving all LTPS lines.
32
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
RGB INTERFACE CONTROL (R02h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
W
1
X
X
X
X
X
X
X
RM
IB7
DM
IB6
IB5
IB4
IB3
IB2
IB1
IB0
X
RIM
RIM
VSP
HSP
EPL
DPL
1
0
L
L
*02h Initial Value = XXXX_XXX0_0X00_0000
RM
Specifies the interface for GRAM accesse as shown below. This register and DM register can be set independently.
DM
Specifies the display operation mode. The interface can be set based on the bit of DM. In Internal Clock Opeartion
mode the source clock for display operation comes from internal oscillator while in External Clock Opeartion mode it
comes from RGB interface(DOTCLK, VSYNC, HSYNC).
RM
Table22: RM, DM, GRAM Access Interface and Display Operation Mode
DM
GRAM Access Interface
Display operation mode
0
0
System interface
Internal clock operation
1
1
RGB interface
External clock operation
[NOTE] [RM, DM]= 01, [RM, DM]=10 setting disable.
RIM
Specifies RGB interface mode when the RGB interface is used. This register is valid when RM is set to “1”. DM and
this register should be set before proper display operation is performed through the RGB interface.
RIM[1:0]
Table23: RIM and RGB Interface Mode
RGB Interface mode
00
18-bit RGB interface (one transfer per pixel)
01
16-bit RGB interface (one transfer per pixel)
10
6-bit RGB interface (three transfers per pixel)
11
SETTING DISABLE
33
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
You should notice that some display functions, which will be described later, cannot be used according to the display
mode shown below.
Table24: Display Functions and Display Modes
Function
External Clock Operation Internal Clock Operation
Mode
Mode
Partial Display
Cannot be used
Can be used
Scroll Function
Cannot be used
Can be used
Rotation
Cannot be used
Can be used
Mirroring
Cannot be used
Can be used
Window Function
Cannot be used
Can be used
Depending on the external display interface setting, various interfaces can be specified to match the display state.
While displaying motion pictures (RGB interface), the data for display can be written in high-speed write mode,
which achieves both low power consumption and high-speed access.
Table25: Display State and Interface
[NOTE]
Display State
Operation Mode
Still Pictures
Internal Clock
Motion Pictures
RGB interface
RAM Access (RM)
System interface
(RM=0)
RGB interface
(RM=1)
Display Operation Mode
(DM)
Internal clock
(DM=0)
RGB interface
(DM=1)
1) The instruction register can only be set through the system interface(SPI).
2) The RGB interface mode should not be set during operation.
For the transition flow for each operation mode, see the External Display Interface section.
Internal Clock Mode
All display operation is controlled by signals generated by the internal clock in internal clock mode.
All inputs through the external display interface are invalid. The internal RAM can be accessed only via the system
interface.
RGB Interface Mode
The display operations are controlled by the frame synchronization clock (VSYNC), raster-row synchronization
signal (HSYNC), and dot clock (DOTCLK) in RGB interface mode. These signals should be supplied during display
operation in this mode.
The display data is transferred to the internal RAM via DB17-0 for each pixel. Combining the function of the
high-speed write mode and the window address enables display of both the motion picture area and the internal
RAM area simultaneously. In this method, data is only transferred when the screen is updated, which reduces the
amount of data transferred.
The periods of the front (FP), back (BP) porch, and the display are automatically generated in the S6E63D6 by
counting the raster-row synchronization signal (HSYNC) based on the frame synchronization signal (VSYNC).
34
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
VSPL
Determines the active polarity of VSYNC.
VSPL
Table26: VSPL and VSYNC
VSYNC
Description
0 (1)
0 (1)
Valid (Valid)
0 (1)
1 (0)
Invalid (Invalid)
HSPL
Determines the active polarity of HSYNC.
HSPL
Table27: HSPL and VSYNC
HSYNC
Description
0 (1)
0 (1)
Valid (Valid)
0 (1)
1 (0)
Invalid (Invalid)
EPL
Determines the active polarity of ENABLE for using RGB interface.
EPL
Table28: EPL, ENABLE and RAM access
ENABLE
RAM Write
RAM Address
0 (1)
0 (1)
Valid (Valid)
Updated (Updated)
0 (1)
1 (0)
Invalid (Invalid)
Hold (Hold)
DPL
Determines the active polarity of DOTCLK.
DPL
Table29: HSPL and VSYNC
DOTCLK
Description
0 (1)
↑(↓)
Valid (Valid)
0 (1)
↓ (↑)
Invalid (Invalid)
35
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
ENTRY MODE (R03h)
R/W
W
RS
1
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
CLS
MDT
1
MDT
0
BGR
X
X
X
SS
X
X
I/D1
I/D0
X
X
X
AM
*03h Initial Value = 0000_XXX0_XX11_XXX0
CLS: This bit is used to define the color and interface bus format, When MDT0-1 = 00
CLS = 0 : 65K-color mode through 8-bit(Index address 24h) or 16-bit bus(Index address 23h)
CLS = 1 : 262K-color mode through 9-bit(Index address 24h) or 18-bit bus(Index address 23h)
MDT1: This bit is active on the 80-system of 8-bit bus, and the data for 1-pixel is transported to the memory for 3
write cycles. This bit is on the 80-system of 16-bit bus, and the data for 1-pixel is transported to the memory for 2
write cycles. When the 80-system interface mode is not set in the 8-bit or16-bit mode, set MDT1 bit to be “0”.
MDT0: When 8-bit or16-bit 80 interface mode and MDT1 bit =1, MDT0 defines color depth for the IC.
8-bit (80-system), MDT0 = 0: 262k-color mode (3 times of 6-bit data transfer to GRAM)
8-bit (80-system), MDT0 = 1: 65k-color mode (5-bit, 6-bit, 5-bit data transfer to GRAM)
16-bit (80-system), MDT0 = 0: 262k-color mode (16-bit, 2-bit data transfer to GRAM)
16-bit (80-system), MDT0 = 1: 262k-color mode (2-bit, 16-bit data transfer to GRAM)
Interface
Mode
*
MDT1
MDT0
Write data to GRAM
0
0
80/68
system
8-bit
0
1
Default value. Multiple Data Transfer(MDT1-0) function is not available. Data
Transfer is controlled by interface mode. (Depends on S_PB, ID_MIB pins, CLS
register and Index address 23h or 24h)
Multiple Data Transfer(MDT1-0) function is not available.
1
0
1st Transmission
INPUT DATA
RGB Arrangement
2nd Transmission
3rd Transmission
DB
8
DB
7
DB
6
DB
5
DB
4
DB DB DB DB DB
3
17
8
16
7
15
6
14
5
DB DB DB DB DB DB DB
13
4
12
3
17
8
16
7
15
6
14
5
13
4
DB
12
3
R5
R4
R3
R2
R1
R0
G1
B0
G5
G4
G3
G2
G0
B5
B4
B3
B2
B1
S(n)
Output
Note: n= 1 to 240
1
1st Transmission
INPUT DATA
RGB Arrangement
Output
2nd Transmission
3rd Transmission
DB
8
17
DB
7
16
DB
6
15
DB
5
14
DB
4
13
DB
3
12
DB
8
17
DB
7
16
DB
6
15
DB
5
14
DB
4
13
DB
3
12
DB
8
17
DB
7
16
DB
6
15
DB
5
14
DB
4
13
DB
3
12
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S(n)
Note: n= 1 to 240
36
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Interface
Mode
80/68
system
16-bit
MDT1
MDT0
0
1
1
0
Data Assignment
2nd Transmission
1st Transmission
INPUT DATA
RGB Arrangement
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
17
DB
16
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S(n)
Output
Note: n= 1 to 240
1
1st Transmission
INPUT DATA
RGB Arrangement
Output
2nd Transmission
DB
2
DB
1
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S(n)
Note: n= 1 to 240
37
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
BGR: About writing 18-bit data to GRAM, it is changed <R><G><B> into <B><G><R>.
- BGR = 0 ; {DB[17:12], DB[11:6], DB[5:0]} is assigned to {R, G, B}. Actually the analog value that corresponds to
DB[17:12] is output firstly at source output
- BGR = 1 ; {DB[17:12], DB[11:6], DB[5:0]} is assigned to {B, G, R}. Actually the analog value that corresponds to
DB[5:0] is output firstly at source output.
SS
Selects the direction of the source driver channel in pixel unit.
When user changes the value of SS, memory should be updated to apply the change.
Table30: Source Output Direction Control with SS (SS = “1”)
S240
S239
S238
S3
S2
S1
G1
“00000”H
“00001”H
“00002”H
••••••••••
“000ED”H
“000EE”H
“000EF”H
G2
“00100”H
“00101”H
“00102”H
••••••••••
“001ED”H
“001EE”H
“001EF”H
G3
“00200”H
“00201”H
“00202”H
••••••••••
“002ED”H
“002EE”H
“002EF”H
G4
“00300”H
“00301”H
“00302”H
••••••••••
“003ED”H
“003EE”H
“003EF”H
G5
“00400”H
“00401”H
“00402”H
••••••••••
“004ED”H
“004EE”H
“004EF”H
G6
“00500”H
“00501”H
“00502”H
••••••••••
“005ED”H
“005EE”H
“005EF”H
G7
“00600”H
“00601”H
“00602”H
••••••••••
“006ED”H
“006EE”H
“006EF”H
G8
“00700”H
“00701”H
“00702”H
••••••••••
“007ED”H
“007EE”H
“007EF”H
M
M
M
M
M
M
M
M
G313
“13800”H
“13801”H
“13802”H
•••••••••
“138ED”H
“138EE”H
“138EF”H
G314
“13900”H
“13901”H
“13902”H
•••••••••
“139ED”H
“139EE”H
“139EF”H
G315
“13A00”H
“13A01”H
“13A02”H
•••••••••
“13AED”H
“13AEE”H
“13AEF”H
G316
“13B00”H
“13B01”H
“13B02”H
•••••••••
“13BED”H
“13BEE”H
“13BEF”H
G317
“13C00”H
“13C01”H
“13C02”H
•••••••••
“13CED”H
“13CEE”H
“13CEF”H
G318
“13D00”H
“13D01”H
“13D02”H
•••••••••
“13DED”H
“13DEE”H
“13DEF”H
G319
“13E00”H
“13E01”H
“13E02”H
•••••••••
“13EED”H
“13EEE”H
“13EEF”H
G320
“13F00”H
“13F01”H
“13F02”H
•••••••••
“13FED”H
“13FEE”H
“13FEF”H
[NOTE] For the case of SS = “0”, refer to “GRAM ADDRESS MAP” presented earlier. You should notice that the order of source
output is reversed.
38
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
ID
When ID[1], ID[0] = 1, the address counter (AC) is automatically increased by 1 after the data is written to the GRAM.
When ID[1], ID[0] = 0, the AC is automatically decreased by 1 after the data is written to the GRAM.
The increment/decrement setting of the address counter using ID[1:0] is done independently for the horizontal
address and vertical address.
AM
Sets the automatic update method of the AC after the data is written to GRAM. When AM = “0”, the data is
continuously written in horizontally. When AM = “1”, the data is continuously written vertically. When window
addresses are specified, the GRAM in the window range can be written to according to the ID[1:0] and AM.
Table31: Address Direction Setting
ID[1:0] = “00”
ID[1:0] = “01”
ID[1:0] = “10”
H: decrement
H: increment
H: decrement
V: decrement
V: decrement
V: increment
00000h
00000h
00000h
ID[1:0] = “11”
H: increment
V: increment
00000h
AM=”0”
Horizontal Update
13FEFh
13FEFh
0000h
0000h
13FEFh
0000h
13FEFh
0000h
AM=”1”
Vertical Update
13FEFh
13FEFh
13FEFh
13FEFh
[NOTE] When window addresses have been set, the GRAM can only be written within the window.
When AM or ID is set, the start address should be written accordingly prior to memory write.
39
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
CLOCK CONTROL (R04h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
W
1
X
X
X
X
X
X
X
X
X
X
IB5
IB4
DCR
DCR
1
0
IB3
IB2
IB1
IB0
X
X
X
X
*04h Initial Value = XXXX_XXXX_XX00_XXXX
DCR
Sets the division ratio of step –up clock, DCCLK, in External Clock Operation mode. In this case, DOTCLK must be
input periodically and continuously.
DCR[1:0]
40
Table32: DCR and Division Ratio of DCCLK
Division ratio of DCCLK
00
DOTCLK / 4
01
DOTCLK / 8
10
DOTCLK / 16
11
DOTCLK / 32
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
DISPLAY CONTROL – 1 (R05h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W
1
X
X
X
X
X
X
X
X
X
X
X
x
X
X
X
DISP_
ON
*05h Initial Value = XXXX_XXXX_XXXX_XXX0
DISP_ON
Output from the Frame Memory is enabled.
This register makes No Change of contents of frame memory
DISP_ON = 0 (Display is black image),
(Example)
Memory
Display
DISP_ON = 1,
(Example)
Memory
Display
For more information, see the Instruction Set Up Sequence.
41
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
DISPLAY CONTROL – 2 (R06h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W
1
X
X
X
X
X
X
X
X
X
X
X
CL
X
X
TEM
ON
REV
*06h Initial Value = XXXX_XXXX_XXX0_XX00
CL
Sets color depth of display.
Table33: Color Control by CL
CL
Description
0
1
262,144 / 65,536 colors [NOTE]
8 colors
[NOTE] It depend on interface mode(18bit or 16bit).
TEMON :
TEMON = 0, Disable the TE output signal from the FLM signal line for preventing Tearing Effect.
TEMON = 1, Enable the TE output signal from the FLM signal line for preventing Tearing Effect.
REV
Displays all characters and graphics display sections with reversal when REV = 1. The grayscale level can be
reversed.
Table34: REV and Source Output Level in Normal Display Area
REV
0
1
42
GRAM Data
Source Output Level in Displayed Area
6’b000000
~
6’b111111
6’b000000
~
6’b111111
V0 (High Voltage)
~
V63(Low Voltage)
V63 (Low Voltage)
~
V0 (High Voltage)
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
PANEL INTERFACE CONTROL – 1 (R07h)
PANEL INTERFACE CONTROL – 2 (R08h)
R/W
W
RS
IB15
X
1
IB14
IB13
X
X
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
CLWE CLW
A4
EA3
IB12
CLW
EA2
CLW
EA1
CLW
EA0
X
X
X
X
X
X
X
X
*07h Initial Value = XXX0_1100_XXXX_XXXX
R/W
RS
IB15
IB14
IB13
W
1
X
X
X
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
CLWE CLW
B4
EB3
CLW
EB2
CLW
EB1
CLW
EB0
X
X
X
CLW
EC4
CLW
EC3
CLW
EC2
CLW
EC1
CLW
EC0
*08h Initial Value = XXX0_1100_XXX0_1100
CLWEA, CLWEB, CLWEC
Specifies the interval time of CLA, CLB, CLC respectively.
Table35: CLWEx and the intervals
CLWEx[4:0]
Description
0_0000
SETTING DISABLE
0_0001
0.5 HCLK
0_0010
1 HCLK
---
---
0_1100
6 HCLK
---
---
1_1110
15 HCLK
1_1111
15.5 HCLK
[NOTE] For the information of HCLK, refer to “FRAME FREQUENCY CACULATION”
43
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
PANEL INTERFACE CONTROL – 3 (R09h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
W
1
SCT
E3
SCT
E2
SCT
SC
SCTE0
E1
WE3
SC
WE2
SC
WE1
SC
WE0
X
SHE
2
SHE
SHE
1
0
IB3
IB2
IB1
IB0
X
CLT
E2
CLT
E1
CLT
E0
*09h Initial Value = 1000_0101_X001_X010
SCTE
Specifies the rising position of SCLK1, SCLK2
Table36: SCTE and the rising position of SCLK1, SCLK2
SCTE[3:0]
Description
0000
16.5 HCLKs
0001
17 HCLKs
0010
17.5 HCLKs
---
----
1000
20.5 HCLKs
---
----
1110
23.5 HCLKs
1111
24 HCLKs
SCWE
Specifies the width of SCLK1, SCLK2
SCWE[3:0]
44
Table37: SCWE and the width of SCLK1, SCLK2
Description
0000
8 HCLKs
0001
8.5 HCLKs
0010
9 HCLKs
---
---
0101
10.5 HCLKs
---
---
1110
15 HCLKs
1111
15.5 HCLKs
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SHE
Specifies the latency of CLB and CLC.
SHE[2:0]
Table38: SHE and the latency of CLB and CLC
Description
000
SETTING DISABLE
001
0.5 HCLK
010
1 HCLK
---
---
110
3 HCLK
111
3.5 HCLK
CLTE
Specifies the falling position of CLA.
CLTE[2:0]
Table39: CLTE and the falling position of CLA
Description
000
SETTING DISABLE
001
0.5 HCLK
010
1 HCLK
011
1.5 HCLKs
---
---
110
3 HCLKs
111
3.5 HCLKs
45
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
PANEL INTERFACE CONTROL – 4 (R0Ah)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
GTC
ON1
GTC
ON0
*0Ah Initial Value = XXXX_XXXX_XXXX_XX00
GTCON
Specifies the panel interface signals.
Output Pin
46
Table40: GTCON and the panel interface signals
Output Signal
GTCON[1:0]=00
GTCON[1:0]=01
GTCON[1:0]=10
GTCON[1:0]=11
BICTL_L
VGH
VGL
VGH
VGL
BICTL_R
VGH
VGL
VGH
VGL
FLM
FLM
FLM
FLM
FLM
SFTCLK
SFTCLK
SFTCLK
VGL
VGL
SFTCLKB
SFTCLKB
SFTCLKB
VGH
VGH
SCLK1
SCLK1
SCLK2
SCLK1
SCLK2
SCLK2
SCLK2
SCLK1
SCLK2
SCLK1
EX_FLM
EX_FLM
EX_FLM
EX_FLM
EX_FLM
EX_CLK
EX_CLK
EX_CLKB
VGL
VGL
EX_CLKB
EX_CLKB
EX_CLK
VGH
VGH
ESR
ESR
ESR
ESR
ESR
CLA
CLA
CLA
CLA
CLA
CLB
CLB
CLB
CLB
CLB
CLC
CLC
CLC
CLC
CLC
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
STAND BY (R10h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
STB
*10h Initial Value = XXXX_XXXX_XXXX_XXX1
STB
When STB = “1”, S6E63D6 enters Standby mode, where display operation completely stops including the internal
R-C oscillation. Furthermore, no external clock pulses are supplied. For details, see the “STANDBY SEQENCE”
described later.
Only the following instructions can be executed during the standby mode.
− Standby mode cancel ; STB = “0”
47
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
POWER GEN1 (R12h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W
1
X
X
X
X
X
X
X
X
X
X
X
X
VC3
VC2
VC1
VC0
*12h Initial Value = XXXX_XXXX_XXXX_1000
V reference voltage of VLOUT1, VLOUT2 and VLOUT3.
VC[3:0]
VCI1 [Without Load]
0000
2.10 V
0001
2.15 V
0010
2.20 V
0011
2.25 V
0100
2.30 V
0101
2.35 V
0110
2.40 V
0111
2.45 V
1000
2.50 V
1001
2.55 V
1010
2.60 V
1011
2.65 V
1100
2.70 V
1101
2.75 V
1110
Setting Disable
1111
Setting Disable
[NOTE] Set VCI1 in the range of VCI > VCI1 + 0.3V
48
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
POWER GEN2 (R13h)
R/W
RS
W
1
IB15
X
IB14
X
IB13
IB12
IB11
IB10
VINT3 VINT2 VINT1 VINT0
IB9
X
IB8
IB7
IB6
IB5
VGH3 VGH2 VGH1 VGH0
IB4
X
IB3
VGL3
IB2
VGL2
IB1
VGL1
IB0
VGL0
*13h Initial Value = XX01_01X0_011X_1010
VINT3[3:0] set VINT (control voltage of OLED Panel). It can be amplified -2.0 to -0.5 times of VCIR.
[NOTE] Set VINIT in the range of V
VINT[3:0]
VINT value
0000
-1.0 V
0001
-1.2 V
0010
-1.4 V
0011
-1.6 V
0100
-1.8 V
0101
-2.0 V
0110
-2.2 V
0111
-2.4 V
1000
-2.6 V
1001
-2.8 V
1010
-3.0 V
1011
-3.2 V
1100
-3.4 V
1101
-3.6 V
1110
-3.8 V
1111
-4.0 V
VINT > VLOUT3 + 1.0V
VGH[3:0] set VGH (High Voltage Level for Gate).
VGH[3:0]
VGH value
0000
4.6 V
0001
4.8 V
0010
5.0 V
0011
5.2 V
0100
5.4 V
0101
5.6 V
0110
5.8 V
0111
6.0 V
49
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
1000
6.2 V
1001
6.4 V
1010
6.6 V
1011
Setting disable
1100
Setting disable
1101
Setting disable
1110
Setting disable
1111
Setting disable
[NOTE] Set VGH in the range of VGH < VLOUT2-1.0V
VGL[3:0] bits set VGL (Low Voltage Level for Gate).
VGL[3:0]
VGL Value
0000
-5.0 V
0001
-5.2 V
0010
-5.4 V
0011
-5.6 V
0100
-5.8 V
0101
-6.0 V
0110
-6.2 V
0111
-6.4 V
1000
-6.6 V
1001
-6.8 V
1010
-7.0 V
1011
-7.2 V
1100
-7.4 V
1101
-7.6 V
1110
-7.8 V
1111
Setting disable
[NOTE] Set VGL in the range of VGL > VLOUT3 + 1.0V
50
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
POWER STEP UP CONTROL 1 (R14h)
R/W
RS
IB15
W
1
X
IB14
DC2
2
IB13
DC2
1
IB12
DC2
0
IB11
IB10
DC1
2
X
IB9
DC1
1
IB8
DC1
0
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
X
X
X
X
X
X
BT1
BT0
*14h Initial Value = X100_X010_XXXX_XX00
DC2[2:0] is the operating frequency in the step-up circuit 2 is selected.
DC1[2:0] is the operating frequency in the step-up circuit 1 is selected.
DC2[2:0]
Step-up Cycle in Step-up
Circuit 2
DM=0
DM=1
000
OSC_CK/16
DCCLK/16
001
OSC_CK/24
010
DC1[2:0]
Step-up Cycle in Step-up
Circuit 1
DM=0
DM=1
000
OSC_CK/16
DCCLK/16
DCCLK/24
001
OSC_CK/24
DCCLK/24
OSC_CK/32
DCCLK/32
010
OSC_CK/32
DCCLK/32
011
OSC_CK/48
DCCLK/48
011
OSC_CK/48
DCCLK/48
100
OSC_CK/64
DCCLK/64
100
OSC_CK/64
DCCLK/64
101
OSC_CK/96
DCCLK/96
101
OSC_CK/96
DCCLK/96
110
OSC_CK/128
DCCLK/128
110
OSC_CK/128
DCCLK/128
111
OSC_CK/256
DCCLK/256
111
OSC_CK/256
[NOTE] DM is Display Method. DCCLK is for External I/F. See instruction R02h, R04h.
DCCLK/256
BT[1:0] switch the output factor of step-up. Adjust scale factor of the step-up circuit by the voltage used.
BT[1:0]
VLOUT1
VLOUT2
VLOUT3
00
VCI1 x 2
VCI1 x 4
-(VCI1 x 4)
01
VCI1 x 2
VCI1 x 4
-(VCI1 x 3)
10
VCI1 x 2
VCI1 x 3
-(VCI1 x 4)
11
VCI1 x 2
VCI1 x 3
-(VCI1 x 3)
51
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
START OSCILLATION (R18h)
R/W
RS
W
1
IB15
X
IB14
X
IB13
X
IB12
X
IB11
X
IB10
X
IB9
X
IB8
X
IB7
X
IB6
X
IB5
IB4
IB3
IB2
IB1
IB0
RADJ5 RADJ4 RADJ3 RADJ2 RADJ1 RADJ0
*18h Initial Value = XXXX_XXXX_XX01_1111
Select the oscillation frequency of internal oscillator.
52
RADJ[5:0]
Oscillation Speed
RADJ[5:0]
Oscillation Speed
000000
x 0.543(Min.)
010101
x 0.782
000001
x 0.551
010110
x 0.800
000010
x 0.560
010111
x 0.818
000011
x 0.568
011000
x 0.835
000100
x 0.578
011001
x 0.855
000101
x 0.586
011010
x 0.877
000110
x 0.596
011011
x 0.899
000111
x 0.606
011100
x 0.921
001000
x 0.615
011101
x 0.946
001001
x 0.626
011110
x 0.972
001010
x 0.637
011111
x 1.000
001011
x 0.647
100000
x 1.037
001100
x 0.660
100001
x 1.067
001101
x 0.671
100010
x 1.101
001110
x 0.685
100011
x 1.135
001111
x 0.697
100100
x 1.172
010000
x 0.707
100101
x 1.212
010001
x 0.721
100110
x 1.256
010010
x 0.736
100111
x 1.302
010011
x 0.751
101000
X1.352(Max.)
010100
x 0.766
101001 ~
111111
Setting disable
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SOURCE DRIVER CONTROL (R1Ah)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
W
1
X
X
X
X
X
X
X
X
X
X
IB5
GAMMA
_TEST
IB4
SDUM
_ON
IB3
X
IB2
SAP
2
IB1
SAP
1
*1Ah Initial Value = XXXX _XXXX_XX00_X101
When GAMMA_TEST=’1’, V0/V63 pins are shorted to each gamma voltage V0/V63 and gamma voltage V0/V63
can be monitored or be forced by external voltage level.
GAMMA_TEST
V0 / V63
0
Hi-z
1
V0 / V63
When SDUM_ON=’1’, SOUT_DUM1 and SOUT_DUM240 pins are shorted to SOUT[1], SOUT[240] output and can
be monitored.
SDUM_ON
SOUT_DUM1 / SOUT_DUM240
0
Hi-z
1
SOUT[1] / SOUT[240]
Adjust the slew-rate of the operational amplifier of the source driver. If higher SAP[2:0] is set, OLED panel having
higher resolution of higher frame frequency can be driven because the slew-rate of the operational amplifier is
increased. But, these bits must be set as adequate value because the amount of fixed current of the operational
amplifier is also adjusted. During non-display, when SAP[2:0]=”000”, operational amplifiers are turned off, so current
consumption can be reduced
SAP[2:0]
Slew-Rate of Operational
Amplifier
Amount of Current in
Operational Amplifier
000
Operation of the operational amplifier stops.
001
Slow
Small
010
Slow or medium
Small or medium
011
Medium
Medium
100
Medium or small fast
Medium or small large
101
Small fast
Small large
110
Fast
large
111
Big fast
Big large
53
IB0
SAP
0
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
GRAM ADDRESS SET (R20h)
GRAM ADDRESS SET (R21h)
R/W
RS
W
1
IB15
X
IB14
X
IB13
X
IB12
X
IB11
X
IB10
X
IB9
X
IB8
X
IB7
AD7
IB6
AD6
IB5
AD5
IB4
AD4
IB3
AD3
IB2
AD2
IB1
AD1
IB0
AD0
*20h Initial Value = XXXX _XXXX_0000_0000
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
W
1
X
X
X
X
X
X
X
IB8
AD1
6
IB7
AD1
5
IB6
AD1
4
IB5
AD1
3
IB4
AD1
2
IB3
AD1
1
IB2
AD1
0
IB1
IB0
AD9
AD8
*21h Initial Value = XXXX _XXX0_0000_0000
AD
You can write initial GRAM address into internal Address Counter (AC). When GRAM data is transferred through
System Interface or RGB Interface, the AC is automatically updated according to AM and ID. This allows
consecutive write without re-setting address in AC. But when GRAM data is read, the AC is not automatically
updated.
GRAM address setting is not allowed in Standby mode. Ensure that the address is set within the specified window
area.
When RGB interface is used (RM=”1”) to access GRAM, AD[16:0] will be set in the address counter at the falling
edge of the VSYNC signal. And when one uses System Interface to access GRAM (RM = “0”), AD[16:0] will be set
upon the execution of an instruction.
AD[16:0]
54
Table41: GRAM Address Range
GRAM setting
“00000h” to “00AFh”
Bitmap data for G1
“00100h” to “01AFh”
Bitmap data for G2
“00200h” to “02AFh”
Bitmap data for G3
“00300h” to “03AFh”
Bitmap data for G4
M
M
M
M
“13C00h” to “13CEFh”
Bitmap data for G317
“13D00h” to “13DEFh”
Bitmap data for G318
“13E00h” to “13EEFh”
Bitmap data for G319
“13F00h” to “13FEFh”
Bitmap data for G320
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
WRITE DATA TO GRAM (R22h)
R/W
RS
W
1
W
1
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
RAM write data (WD17-0): Pin assignment varies according to the interface method. (see the following figure for more information)
WD15
WD14
WD13
WD12
WD11
WD10
WD9
WD8
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
When RGB-interface
WD17-0: Input data for GRAM can be expanded to 18 bits. The expansion format varies according to the interface
method. The input data selects the grayscale level. After a write, the address is automatically updated according to
I/D bit settings. The GRAM cannot be accessed in standby mode. When 16- or 8-bit interface is in use, the write data
is expanded to 18 bits by writing the MSB of the <R><B> data to its LSB.
When data is written to RAM used by RGB interface via the system interface, please make sure that write data
conflicts do not occur.
When the 18-bit RGB interface is in use, 18-bit data is written to RAM via DB17-0 and 262,144-colors are available.
When the 16-bit RGB interface is in use, the MSB is written to its LSB and 65,536-colors are available.
Start
Window Address Set
(index 35h, 36h, 37h)
Start Address Set
(index 20h, 21h)
Index Write (22h)
Write Data
Address is updated by 1
Yes
Write More ?
No
Write Index 00h or another
where, Address hold
( Memory Write )
Figure6: Memory Data Write Sequence
55
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
READ DATA FROM GRAM (R22h)
R/
R
DB1
DB1
DB1
DB1
DB1
DB1
DB1
DB1
W
S
7
6
5
4
3
2
1
0
R
1
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RAM Read data (RD17-0): Pin assignment varies according to the interface method. (see the following figure for more information)
RD17–0: Read 18-bit data from the GRAM. When the data is read to the CPU, the first-word read immediately after
the GRAM address setting is latched from the GRAM to the internal read-data latch. The data on the data bus
(DB17–0) becomes invalid and the second-word read is normal.
In case of 16-/8-bit interface, the LSB of <R><B> color data will not be read.
This function is not available in RGB interface mode.
Start
Start
Set Index 23h and RM = 0
Set Index 24h and RM = 0
Window Address Set
(index 35h, 36h, 37h)
Window Address Set
(index 35h, 36h, 37h)
Start Address Set
(index 20h, 21h)
Start Address Set
(index 20h, 21h)
Index Write (22h)
Index Write (22h)
Read Dummy Data
Read Dummy Data 2 times
Read Valid Data
Read Upper Valid Data
Read Lower Valid Data
Address is updated by 1
Address is updated by 1
Read More ?
Yes
Read More ?
No
No
Write Index 00h or another
Where, Address hold
Write Index 00h or another
Where, Address hold
18-/16- System Interface
9-/8- System Interface
Figure7: Memory Data Read Sequence
56
Yes
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SELECT DATA BUS 1 (R23h)
R/W
RS
W
0
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
IB4
IB3
IB2
IB1
IB0
Select 18-/16-bit Data Bus Interface
SELECT DATA BUS 2 (R24h)
R/W
RS
W
0
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
Select 9-/8-bit Data Bus Interface
We can select system interface mode by pins and instruction as following.
Table42: System Interface mode
Pins
MDDI
_EN
S_PB
Registers
ID_MIB
Index Address
Command
Command
Command
( CLS )
MDT[1]
MDT[0]
0
default & 24h
0 (80 8bit)
(9/8bit)
1( 80 9bit)
0
(80 mode)
Index 23 h
0 (80 16bit)
(18/16bit)
0
1( 80 18bit)
(Parallel
0
)
default & 24h
0 (68 8bit)
(9/8bit)
1 (68 9bit)
1
(68 mode)
Index 23 h
0 (68 16bit)
(Serial)
1
x
x
0
x
80-system 8-bit 65k bus interface
0
80-system 8-bit 260k bus interface
1
80-system 8-bit 65k bus interface
X
80-system 9-bit 260k bus interface
0
80-system 16-bit 65k bus interface
1
80-system 16-bit 260k bus interface
1
X
80-system 16-bit 260k bus interface
x
X
80-system 18-bit 260k bus interface
0
X
68-system 8-bit 65k bus interface
0
68-system 8-bit 260k bus interface
1
x
0
1
68-system 8-bit 65k bus interface
X
68-system 9-bit 260k bus interface
0
68-system 16-bit 65k bus interface
1
68-system 16-bit 260k bus interface
1
x
68-system 16-bit 260k bus interface
1 (68 18bit)
x
x
68-system 18-bit 260k bus interface
Serial peripheral interface (SPI)
(18/16bit)
1
1
Description
ID
x
x
x
x
x
x
x
x
x
[NOTE] For details, see the ENTRY MODE (Instruction R03h).
57
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
VERTICAL SCROLL CONTROL 1 (R30h, R31h)
R/W
RS
W
1
W
1
IB15
IB14
X
IB13
X
X
IB12
X
X
IB11
X
X
IB10
X
X
IB9
X
X
X
X
X
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
SSA
SSA
SSA
SSA
SSA
SSA
SSA
SSA
SSA
8
7
6
5
4
3
2
1
0
SEA
SEA
SEA
SEA
SEA
SEA
SEA
SEA
SEA
8
7
6
5
4
3
2
1
0
*30h Initial Value = XXXX_XXX0_0000_0000
*31h Initial Value = XXXX_XXX1_0011_1111
SSA8-0: Specify scroll start address at the scroll display for vertical smooth scrolling.
SSA8
SSA7
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSA0
Scroll Start Address
0
0
0
0
0
0
0
0
0
0 raster-row
0
0
0
0
0
0
0
0
1
1 raster-row
0
0
0
0
0
0
0
1
0
2 raster-row
0
0
0
0
0
0
0
1
1
3 raster-row
0
0
0
0
0
0
1
0
0
4 raster-row
0
0
1
0
1
5 raster-row
0
:
0
:
0
:
:
0
:
:
:
:
1
0
0
1
1
1
1
0
0
316 raster-row
1
0
0
1
1
1
1
0
1
317 raster-row
1
0
0
1
1
1
1
1
0
318 raster-row
1
0
0
1
1
1
1
1
1
319 raster-row
SEA8-0: Specify scroll end address at the scroll display for vertical smooth scrolling.
SEA8
SEA7
SEA6
SEA5
SEA4
SEA3
SEA2
SEA1
SEA0
Scroll End Address
0
0
0
0
0
0
0
0
0
0 raster-row
0
0
0
0
0
0
0
0
1
1 raster-row
0
0
0
0
0
0
0
1
0
2 raster-row
0
0
0
0
0
0
0
1
1
3 raster-row
0
0
0
0
0
0
1
0
0
4 raster-row
0
0
0
0
0
0
1
0
1
5 raster-row
:
:
:
:
:
:
:
:
1
0
0
1
1
1
1
0
0
316 raster-row
1
0
0
1
1
1
1
0
1
317 raster-row
1
0
0
1
1
1
1
1
0
318 raster-row
1
1
319 raster-row
1
0
0
1
1
1
1
[NOTE] Don’t set any higher raster-row than 319 (“13F”H)
Set SS18-10 ≤ SSA8-0, if set out of range, SSA8-0 = SS18-10.
Set SE18-10 ≥ SEA8-0, if set out of range, SEA8-0 = SE18-10
58
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
VERTICAL SCROLL CONTROL 2 (R32h)
R/W
RS
W
1
IB15
X
IB14
IB13
X
IB12
X
IB11
X
IB10
X
X
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
X
SST
SST
SST
SST
SST
SST
SST
SST
SST
8
7
6
5
4
3
2
1
0
*32h Initial Value = XXXX_XXX0_0000_0000
SST8-0: Specify scroll start and step at the scroll display for vertical smooth scrolling. Any raster-row from the 1st to
320th can be scrolled for the number of the raster-row. After 319th raster-row is displayed, the display restarts from
the first raster-row. When SST8-0 = 00000000, Vertical Scroll Function is disabled.
SST8
SST7
SST6
SST5
SST4
SST3
SST2
SST1
SST0
Scroll Step
0
0
0
0
0
0
0
0
0
Scroll Disabled
0
0
0
0
0
0
0
0
1
1 raster-row
0
0
0
0
0
0
0
1
0
2 raster-row
0
0
0
0
0
0
0
1
1
3 raster-row
0
0
0
0
0
0
1
0
0
4 raster-row
0
0
0
0
0
0
1
0
1
5 raster-row
:
:
:
:
:
:
:
:
1
0
0
1
1
1
1
0
0
316 raster-row
1
0
0
1
1
1
1
0
1
317 raster-row
1
0
0
1
1
1
1
1
0
318 raster-row
1
0
0
1
1
1
1
1
1
319 raster-row
[NOTE] Don’t set any higher raster-row than 319 (“13F”H)
Set SS18-10 < SSA8-0 + SST8-0 ≤ SEA8-0 ≤ SE18-10, if set out of range, Scroll function is disabled
59
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Figure8: Vertical Scroll Display
60
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
PARTIAL SCREEN DRIVING POSITION (R33h, R34h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W
1
X
X
X
X
X
X
X
SS18
SS17
SS16
SS15
SS14
SS13
SS12
SS11
SS10
W
1
X
X
X
X
X
X
X
SE18
SE17
SE16
SE15
SE14
SE13
SE12
SE11
SE10
*33h Initial Value = XXXX_XXX0_0000_0000
*34h Initial Value = XXXX_XXX1_0011_1111
SS18–10: Specify the drive starting position for the first screen in a line unit. The OLED driving starts from the ‘set
value +1’ gate driver.
SE18–10: Specify the driving end position for the screen in a line unit. The OLED driving is performed to the ‘set
value + 1’ gate driver. For instance, when SS18–10 = 019h and SE18–10 = 029h are set, the OLED driving is
performed from G26 to G42, and non-display driving is performed for G1 to G25, G43, and others. Ensure that
SS18–10 ≤ SE18–10 ≤13Fh.
[NOTE] DO NOT set the partial setting when the operation is in the normal display condition. Set this register only
when in the partial display condition.
Ex) SS18-0=007h and SE18-0=010h are performed from G8 to G17.
The S6E63D6 can select and drive partial screens at any position with the screen-driving position registers (R33h,
R34h). Any partial screens required for display are selectively driven and reducing OLED-driving voltage and power
consumption.
Non-display area
G26
G42
OCT 1st 08:00 AM
Partial screen
17 raster-row driving
Non-display area
• Driving raster-row: NL5-0 = 101000 (320 lines)
• Partial screen setting: SS18-10 = 019H, SE18-10 = 029H
Figure9: Driving On Partial Screen
61
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
RESTRICTION ON PARTIAL DISPLAY AREA SETTING
The following restrictions must be satisfied when setting the start line (SS18 to 10) and end line (SE18 to 10) of the
partial screen driving position register (R33h, R34h) for the S6E63D6. Note that incorrect display may occur if the
restrictions are not satisfied.
Table43: Restrictions on the partial Screen Driving Position Register Setting
Register setting
(SE18 to 10) – (SS18 to 10) = NL*8
Full screen display
Normally displays (SS18 to 10) to (SE18 to 10)
(SE18 to 10) – (SS18 to 10) < NL*8
Partial display
Normally displays (SS18 to 10) to (SE18 to 10)
Black display for all other times (RAM data is not related
at all)
(SE18 to 10) – (SS18 to 10) > NL*8
Setting disabled
[NOTE] 000h ≤ SS18 to 10 ≤ SE18 to 10 ≤ 13Fh
62
Display operation
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
VERTICAL RAM ADDRESS POSITION (R35h,R36h)
HORIZONTAL RAM ADDRESS POSITION (R37h)
R/W
W
W
W
RS
1
1
1
IB15
X
IB14
X
IB13
X
IB12
IB11
X
X
IB10
X
IB9
X
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
VSA
VSA
VSA
VSA
VSA
VSA
VSA
VSA
VSA
8
7
6
5
4
3
2
1
0
VEA
VEA
VEA
VEA
VEA
VEA
VEA
VEA
VEA
X
X
X
X
X
X
X
8
7
6
5
4
3
2
1
0
HSA
HSA
HSA
HSA
HSA
HSA
HSA
HSA
HEA
HEA
HEA
HEA
HEA
HEA
HEA
HEA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
*35h Initial Value = XXXX_XXX0_0000_0000
*36h Initial Value = XXXX_XXX1_0011_1111
*37h Initial Value = 0000_0000_1110_1111
VSA8-0/VEA8-0: Specify the vertical start/end positions of a window for access in memory. Data can be written to
the GRAM from the address specified by VSA8-0 to the address specified by VEA8-0. Note that an address must be
set before RAM is written.
HSA7-0/HEA7-0: Specify the horizontal start/end positions of a window for access in memory. Data can be written
to the GRAM from the address specified by HSA7-0 to the address specified by HEA 7-0. Note that an address must
be set before RAM is written..
HSA
HEA
00000h
000EFh
VSA
Window Address Range
-0
HSA
HEA
EFh
VSA
VEA
13Fh
-0
Window
VEA
GRAM
13F00h
13FEFh
Figure10: Window Address Function
[NOTE] Ensure that the Window addresses are within the GRAM address space.
63
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
CLIENT INITIATED WAKE-UP (R38h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
W
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
IB0
VWAK
E_EN
*38h Initial Value = XXXX_XXXX_XXXX_XXX0
VWAKE_EN : When VWAKE_EN is 1, client initiated wake-up is enabled. But parameter data IB[15:1] must be
“0000h”, otherwise, client initiated wake-up is disabled.
MDDI LINK WAKE-UP START POSITION (R39h)
R/W
W
RS
1
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
WKL
WKL
WKL
WKL
WKL
WKL
WKL
WKL
WKL
8
7
6
5
4
3
2
1
0
IB6
X
IB5
IB4
IB3
IB2
WKF
WKF
WKF
WKF
3
2
1
0
IB1
IB0
X
X
*39h Initial Value = 0000_0000_0X00_00XX
WKF3-0 : When client initiated wake-up is used at MDDI, the frame position that data is updated is set by the value
of WKF 3-0. The range of WKF is from ‘0000’ to ‘1111’.
If WKF is ‘0000’, data is updated at the first frame, and if “1111” data update starts after 16th frame.
WKL8-0 : When client initiated wakeup is used at MDDI, data is updated at the line the value of WKL7-0 in the frame
that is set by WKF3-0. The range of WKL is from ‘000h’ to ‘1FFh’.
If WKL is ‘000h’, data is updated at the first line, and if WKL is ‘0FFh’, data update starts at the 256th line.
Setting of WFK and WKL is needed for client-initiated link wake-up.
For example, WKF is “0010” and WKL is “0001”, data is updated at second line of third frame.
SUB PANEL CONTROL 1 (R3Ah / R3Bh)
R/W
RS
W
1
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
X
X
X
X
X
X
X
X
SUB_SEL
IB3
W
1
X
X
X
X
X
X
X
X
SUB_WR
IB2
IB1
IB0
*3Ah Initial Value = XXXX_XXXX_0111_1010
*3Bh Initial Value = XXXX_XXXX_0010_0010
SUB_SEL : SUB_SEL is the index of main/sub panel selection. Initial value of SUB_SEL is ‘7Ah’.
In MDDI mode, If written register address is ‘7Ah’ (initial state: SUB_SEL is ‘7Ah’) and register data is
‘0001h’, then main panel is selected, and if that is “0000h”, then sub panel is selected.
Using SUB_SEL register, Main / Sub panel selection index change is possible.
SUB_WR : SUB_WR is the index of sub panel data write. Initial value of SUB_WR is ‘22h’.
When MDDI host transfer GRAM data to sub panel driver IC via video stream packet, SUB_WR (initially
22h), index for GRAM access is automatically transferred before GRAM data transfer.
When sub panel driver IC uses other address, 22h address have to be changed. Then user can change
SUB_WR value from 22h to other value.
64
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SUB PANEL CONTROL 2 (R3Ch)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
W
1
X
X
X
X
X
X
X
X
IB7
FCV_
EN
IB6
IB5
IB4
X
X
X
IB3
IB2
IB1
IB0
MPU_
STN
SUB
SUB
MODE
_EN
_IM1
_IM0
*3Ch Initial Value = XXXX_XXXX_0XXX_0000
SUB_IM1-0: set the sub-panel interface
SUB_ SUB_
IM1
IM0
Interface
0
0
18bit
0
1
9bit
1
0
16bit
1
1
8bit
STN_EN: set the panel property.
STN_EN = “1”: STN panel.
STN_EN = “0”: TFT panel.
MPU_MODE: set the MPU interfaces
MPU_MODE = “1”: 68 mode
MPU_MODE = “0”: 80 mode
FCV_EN : data format conversion enable signal
FCV_EN = “1”: 16 bit data format conversion (not used)
FCV_EN = “0”: current 16bit data format
65
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
TEST KEY COMMAND (R60h)
MTP CONTROL (R61h)
MTP REGISTER SETTING (R62h, R63h, R64h, R65h)
R/W
RS
W
1
IB15
X
IB14
X
IB13
X
IB12
X
IB11
X
IB10
X
IB9
X
IB8
X
IB7
0
IB6
0
IB5
0
IB4
0
IB3
1
IB2
1
IB1
1
IB0
1
W
1
X
X
X
X
X
X
X
MTP_
WRB
X
X
X
MTP_
SEL
X
X
X
MTP_
ERB
W
1
X
R21_DK2 R21_DK1 R21_DK0 R21_BT2 R21_BT1 R21_BT0
X
R63_DK3 R63_DK2 R63_DK1 R63_DK0 R63_BT3 R63_BT2 R63_BT1 R63_BT0
W
1
X
G21_DK2 G21_DK1 G21_DK0 G21_BT2 G21_BT1 G21_BT0
X
G63_DK3 G63_DK2 G63_DK1 G63_DK0 G63_BT3 G63_BT2 G63_BT1 G63_BT0
W
1
X
B21_DK2 B21_DK1 B21_DK0 B21_BT2 B21_BT1 B21_BT0
X
B63_DK3 B63_DK2 B63_DK1 B63_DK0 B63_BT3 B63_BT2 B63_BT1 B63_BT0
W
1
X
X
X
X
X
X
X
X
X
X
X
X
X
E_OST2
E_OST1 E_OST_0
*Initial Value MTP_WRB: 1’b1, MTP_SEL: 1’b1, MTP_ERB: 1’b1
R21_DK[2:0]: 3’d0, R21_BT[2:0]: 3’d0, R63_DK[3:0]: 4’d0, R63_BT[3:0]: 4’d0
G21_DK[2:0]: 3’d0, G21_BT[2:0]: 3’d0, G63_DK[3:0]: 4’d0, G63_BT[3:0]: 4’d0
B21_DK[2:0]: 3’d0, B21_BT[2:0]: 3’d0, B63_DK[3:0]: 4’d0, B63_BT[3:0]: 4’d0
E_OST[2:0]:3’d0
Test Key Command : Protection command. When Test Key Command =8Ch, MTP_WRB and MTP_ERB are valid
MTP_WRB: MTP Write enable signal. If you want to write data to MTP cell, set MTP_WRB = 0
MTP_SEL: Selects MTP value or register value added to CR5[6:0], CG5[6:0], CB5[6:0], CR3[5:0], CG3[5:0], and
CB3[5:0]
MTP_ERB: Enable for MTP initial or erase. When MTP_ERB = 0, MTP initialization or erase is enabled.
R21_DK[3:0], R21_BT[[3:0]: V21(Red) offset compensation value.
G21_DK[3:0], G21_BT[[3:0]: V21(Green) offset compensation value.
B21_DK[3:0], B21_BT[[3:0]: V21(Blue) offset compensation value.
R63_DK[4:0], R63_BT[[4:0]: V63(Red) offset compensation value.
G63_DK[4:0], G63_BT[[4:0]: V63(Green) offset compensation value.
B63_DK[4:0], B63_BT[[4:0]: V63(Blue) offset compensation value.
E_OST[2:0]: ELVDD offset compensation value
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
67
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
011
complement
offset value
+3
0111
complement
offset value
+7
011
complement
offset value
+3
010
+2
0110
+6
010
+2
001
+1
0101
+5
001
+1
000
111
0
0100
+4
000
0
-1
0011
+3
111
-1
110
-2
0010
+2
110
-2
101
-3
0001
+1
101
-3
100
-4
0000
0
100
-4
1111
-1
1110
-2
1101
-3
1100
-4
1011
-5
1010
-6
1001
-7
1000
-8
R(G,B)_21[2:0]
68
R(G,B)_63[3:0]
E_OST[2:0]
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Start
RESET
Start
Enter Standby Mode
( STB = "1" )
Display On after a RESET
Supply MTPG, MTPD
( MTPG = 21.5V), MTPD = 0V)
Set Test Key
( TEST_KEY parameter = "0Fh" )
Find Desired MTP value with
MTP_SEL = "0"
Enable Initialization
( MTP_ERB = "0" )
Initialization & Erase Flow
Wait 1ms or more
Enter Standby Mode
( STB = "1" )
Enable MTP Write
( MTP_WRB = "0" )
Supply MTPG, MTPD
( MTPG = 0V), MTPD = 16.5V)
Wait 100ms or more
Set Test Key
( TEST_KEY Parameter = "0Fh" )
Disable MTP Write
( MTP_WRB = "1" )
Set Desired MTP Value
Bad
Good
Cut Off MTPG, MTPD
( MTPG = MTPD = floating )
Initialization &
Erase Flow
RESET
End
End
A. Flow of MTP Initialization & Erase
B. Flow of MTP Program
Figure16: MTP Initialization, Erase and program
69
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Figure17: Timing of MTP Program
Figure18: Timing of MTP Load
70
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
GPIO CONTROL (R66h/R67h/R68h/R69h/R6Ah)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
W
1
X
X
X
X
X
X
W
1
X
X
X
X
X
X
W
1
X
X
X
X
X
X
W
1
X
X
X
X
X
X
W
1
X
X
X
X
X
X
IB9
GPI
O9
GPI
O_C
ON9
GPC
LR9
GPI
O_E
N9
GPP
OL9
IB8
GPI
O8
GPI
O_C
ON8
GPC
LR8
GPI
O_E
N8
GPP
OL8
IB7
GPI
O7
GPI
O_C
ON7
GPC
LR7
GPI
O_E
N7
GPP
OL7
IB6
GPI
O6
GPI
O_C
ON6
GPC
LR6
GPI
O_E
N6
GPP
OL6
IB5
GPI
O5
GPI
O_C
ON5
GPC
LR5
GPI
O_E
N5
GPP
OL5
IB4
GPI
O4
GPI
O_C
ON4
GPC
LR4
GPI
O_E
N4
GPP
OL4
IB3
GPI
O3
GPI
O_C
ON3
GPC
LR3
GPI
O_E
N3
GPP
OL3
IB2
GPI
O2
GPI
O_C
ON2
GPC
LR2
GPI
O_E
N2
GPP
OL2
IB1
GPI
O1
GPI
O_C
ON1
GPC
LR1
GPI
O_E
N1
GPP
OL1
IB0
GPI
O0
GPI
O_C
ON0
GPC
LR0
GPI
O_E
N0
GPP
OL0
*66h Initial Value = XXXX_XX00_0000_0000
*67h Initial Value = XXXX_XX00_0000_0000
*68h Initial Value = XXXX_XX00_0000_0000
*69h Initial Value = XXXX_XX00_0000_0000
*6Ah Initial Value = XXXX_XX11_1111_1111
GPIO: GPIO value. When GPIO is input mode, GPIO value is set to the register.
GPIO_CON: Control of GPIO, When GPIO_CON is “0”, then GPIO is input mode, and when “1”, then GPIO is output
mode
GPCLR: After client is wakeup, GPIO
GPIO_EN: When GPIO is set input, if GPIO_EN is “1”, it acts as enable internal interrupt.
GPPOL: If the bit is set to “1”, GPIO interrupt happens at rising edge of GPIN, If set to “0”, it happens at falling edge.
For more information about these registers, refer to GPIO CONTROL section
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
GAMMA CONTROL (R70h to R78h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
W
1
X
X
CR56
CR55
CR54
CR53
CR52
CR51
CR50
X
X
X
CR03
CR02
CR01
CR00
W
1
X
X
CG56
CG55
CG54
CG53
CG52 CG51 CG50
X
X
X
CG03 CG02 CG01 CG00
W
1
X
X
CB56
CB55
CB54
CB53
CB52
CB51
CB50
X
X
X
CB03
CB02
CB01
CB00
W
1
X
X
CR15
CR14
CR13
CR12
CR11
CR10
X
X
CR25
CR24
CR23
CR22
CR21
CR20
W
1
X
X
CR35
CR34
CR33
CR32
CR31
CR30
X
X
CR45
CR44
CR43
CR42
CR41
CR40
W
1
X
X
CG15
CG14
CG13
CG12
CG11 CG10
X
X
CG25 CG24 CG23 CG22 CG21 CG20
W
1
X
X
CG35
CG34
CG33
CG32
CG31 CG30
X
X
CG45 CG44 CG43 CG44 CG41 CG40
W
1
X
X
CB15
CB14
CB13
CB12
CB11
CB10
X
X
CB25
CB24
CB23
CB22
CB21
CB20
W
1
X
X
CB35
CB34
CB33
CB32
CB31
CB30
X
X
CB45
CB44
CB43
CB42
CB41
CB40
These registers set the one of the 9 gamma sets according to GS_SEL[3:0]
CR5[6:0]: The amplitude adjust register
CR4[4:0]: The amplitude adjust register
CR3[4:0]: The amplitude adjust register
CR2[4:0]: The amplitude adjust register
CR1[4:0]: The amplitude adjust register
CR0[3:0]: The amplitude adjust register
CG5[6:0]: The amplitude adjust register
CG4[4:0]: The amplitude adjust register
CG3[4:0]: The amplitude adjust register
CG2[4:0]: The amplitude adjust register
CG1[4:0]: The amplitude adjust register
CG0[3:0]: The amplitude adjust register
CB5[6:0]: The amplitude adjust register
CB4[4:0]: The amplitude adjust register
CB3[4:0]: The amplitude adjust register
CB2[4:0]: The amplitude adjust register
CB1[4:0]: The amplitude adjust register
CB0[3:0]: The amplitude adjust register
For details, see the GAMMA ADJUSTMENT FUNCTION.
GAMMA SELECT (R80h)
R/W
RS
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
W
1
X
X
X
X
X
X
X
X
X
X
X
X
IB3
IB2
IB1
IB0
GS_
GS_
GS_
GS_
SEL3
SEL2
SEL1
SEL0
*80h Initial Value = XXXX_XXXX_XXXX_0100
Selects the gamma set controlled by 70H ~ 78H
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
RESET FUNCTION
The S6E63D6 is initialized internally by RESET input. The reset input should be held ‘L’ for at least 10us. Do not
access the GRAM nor initially set the instructions until the R-C oscillation frequency is stable after power has been
supplied (10 ms).
INSTRUCTION SET INITIALIZATION
1. Display duty control (R01h) : FP3_0=1000, BP3_0=1000, NL5_0=10_1000
2. RGB interface control (R02h) : RM=0, DM=0, RIM1_0=00, VSPL=0, HSPL=0, EPL=0, DPL=0
3. Entry mode (R03h) : CLS=0, MDT1_0=00, BGR=0, SS=0, ID1_0=11, AM=0
4. Clock control (R04h) : DCR1_0=00
5. Display control 1 (R05h) : DISP_ON=0
6. Display control 2 (R06h) : CL=0, TEMON=0, REV=0
7. Panel interface control 1 (R07h) : CLWEA4_0=0_1100
8. Panel interface control 2 (R08h) : CLWEB4_0=0_1100, CLWEC4_0=0_1100
9. Panel interface control 3 (R09h) : SCTE3_0=1000, SCWE3_0=0101, SHE2_0=001, CLTE2_0=010
10. Panel interface control 4 (R0Ah) : GTCON1_0=00
11. Stand by (R10h) : STB=1
12. Power gen 1 (R12h) : VC3_0=1000
13. Power gen 2 (R13h) : VINT3_0=0101, VGH3_0=0011, VGL3_0=1010
14. Power step up control 1 (R14h) : DC22_0=100, DC12_0=010, BT1_0=00
15. Start oscillation (R18h) : RADJ5_0=01_1111
16. Source driver control (R1Ah) : GAMMA_TEST=0, SDUM_ON=0, SAP2_0=101
17. GRAM address set (R20h) : AD7_0=0000_0000
18. GRAM address set (R21h) : AD16_8=0_0000_0000
19. Vertical scroll control 1 (R30h, R31h) : SSA8_0=0_0000_0000, SEA8_0=1_0011_1111
20. Vertical scroll control 2 (R32h) : SST8_0=0_0000_0000
21. Partial screen driving position (R33h, R34h) : SS18_0=0_0000_0000, SE18_0=1_0011_1111
22. Vertical RAM address position (R35h, R36h) : VSA8_0=0_0000_0000, VEA8_0=1_0011_1111
23. Horizontal RAM address position (R37h) : HAS7_0=0000_0000, HEA7_0=1110_1111
24. Client initiated wake up (R38h) : VWAKE_EN=0
25. MDDI link wake up start position (R39h) : WKL8_0=0_0000_0000, WKF3_0=0000
26. Sub panel control 1(R3Ah, R3Bh) : SUB_SEL7_0=0111_1010, SUB_WR7_0=0010_0010
27. Sub panel control 2 (R3Ch) : FCV_EN=0, MPU_MODE=0, STN_EN=0, SUB_IM1_0=00
28. MTP control (R61h) : MTP_WRB=1, MTP_SEL=1, MTP_ERB=1
29. MTP register setting 1 (R62h) : R21_DK2_0=000, R21_BT2_0=000, R63_DK3_0=0000, R63_BT3_0=0000
30. MTP register setting 2 (R63h) : G21_DK2_0=000, G21_BT2_0=000, G63_DK3_0=0000, G63_BT3_0=0000
31. MTP register setting 3 (R64h) : B21_DK2_0=000, B21_BT2_0=000, B63_DK3_0=0000, B63_BT3_0=0000
32. MTP register setting 4 (R65h) : E_OST2_0=000
33. GPIO control (R66h, R67h, R68h. R69h, R6Ah) : GPIO9_0=00_0000_0000, GPIO_CON9_0=00_0000_0000
GPCLR9_0=00_0000_0000, GPIO_EN9_0=00_0000_0000, GPPOL9_0=11_1111_1111
73
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
POWER SUPPLY
PATTERN DIAGRAMS FOR VOLTAGE SETTING
The following figure shows a pattern diagram for the voltage setting and an example of waveforms.
Figure19: Pattern Diagram for Voltage Setting
74
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
VOLTAGE REGULATION FUNCTION
The S6E63D6 has the internal voltage regulator. By the use of this function, unexpected damages on internal logic
circuit can be avoided. Furthermore, power consumption can also be obtained. Detailed function description and
application configuration is described in the following diagram.
Figure20: Voltage Regulation Function
75
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
INTERFACE SPECIFICATION
The S6E63D6 incorporates a system interface, which is used to set instructions, and an external display interface,
which is used to display motion pictures. Selecting these interfaces to match the screen data (motion picture or still
picture) enables efficient transfer of data for display.
The external display interface includes RGB interface. This allows flicker-free screen update.
When RGB interface is selected, the synchronization signals (VSYNC, HSYNC, and DOTCLK) are available for use
in operating the display. The display data (DB17-0) is written according to the values of the data enable signal
(ENABLE) in synchronization with the VSYNC, HSYNC, and DOTCLK signals. In addition, using the window
address function enables rewriting only to the internal RAM area to display motion pictures. Using this function also
enables simultaneously display of the motion picture area and the RAM data that was written.
HOSTs
S6E63D3
S_PB
ID_MIB
CSB
RS
RW_WRB
E_RDB
DB
CPU
Interface
System
Interface
18/16/9/8
Serial
Peripheral
Interface
(CSB)
RW_WRB/SCL
SDI
SDO
RGB
Interface
VSYNC
HSYNC
ENABLE
DOTCLK
(DB)
18/16/6
Figure21: System Interface and RGB Interface
76
RGB
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SYSTEM INTERFACE
S6E63D6 is enabling to set instruction and access to RAM by selecting S_PB, ID_MIB pins and Instruction in the
system interface mode.
Table44: System Interface mode
Pins
MDDI
_EN
S_PB
Registers
ID_MIB
Index Address
default & 24h
Command
Command
Command
( CLS )
MDT[1]
MDT[0]
0
x
80-system 8-bit 65k bus interface
0
80-system 8-bit 260k bus interface
0 (80 8bit)
(9/8bit)
1( 80 9bit)
0
(80 mode)
Index 23 h
0 (80 16bit)
(18/16bit)
0
1( 80 18bit)
(Parallel
0
)
default & 24h
0 (68 8bit)
(9/8bit)
1 (68 9bit)
1
(68 mode)
Index 23 h
0 (68 16bit)
(18/16bit)
1
(Serial)
1
x
1
x
Description
1
80-system 8-bit 65k bus interface
X
80-system 9-bit 260k bus interface
0
80-system 16-bit 65k bus interface
1
80-system 16-bit 260k bus interface
1
X
80-system 16-bit 260k bus interface
x
X
80-system 18-bit 260k bus interface
0
X
68-system 8-bit 65k bus interface
0
68-system 8-bit 260k bus interface
0
1
x
0
1
68-system 8-bit 65k bus interface
X
68-system 9-bit 260k bus interface
0
68-system 16-bit 65k bus interface
1
68-system 16-bit 260k bus interface
1
x
68-system 16-bit 260k bus interface
1 (68 18bit)
x
x
68-system 18-bit 260k bus interface
Serial peripheral interface (SPI)
ID
x
x
x
x
x
x
x
x
x
[NOTE] For details, see the ENTRY MODE (Instruction R03h).
We can select system interface mode by pins and instruction, don’t care 8-/16-bit bus system after power on.
1. In case of 8/9-bit bus system.
Figure21: 8/9-bit bus system
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
2. In case of 18/16-bit bus system
Figure22: 18/16-bit bus system
78
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
68-SYSTEM 18-BIT BUS INTERFACE
Bit Assignment
INPUT DATA
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
DB
0
Figure23: Instruction Format For 18-Bit Interface
GRAM DATA
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure24: RAM Data Write Format For 18-Bit Interface
Timing Diagram
There are 4 timing conditions for 68-system 18-bit CPU interface, which are index write timing condition, data write
timing condition, data read timing condition and status read timing condition.
Figure25: Timing Diagram of 68-System 18-Bit bus interface
79
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
68-SYSTEM 16-BIT BUS INTERFACE
Bit Assignment
INPUT DATA
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Figure26: Instruction Format For 16-Bit Interface
GRAM DATA
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure27: RAM Data Write Format For 16-Bit Interface
Timing Diagram
There are 4 timing conditions for 68-system 16-bit CPU interface, which are index write timing condition, data write
timing condition, data read timing condition and status read timing condition.
Figure28: Timing Diagram of 68-System 16-Bit bus interface
80
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
68-SYSTEM 9-BIT BUS INTERFACE
Bit Assignment
1st Transmission
2nd Transmission
INPUT DATA
DB
8
DB
7
DB
5
DB
5
DB
4
DB
3
DB
2
DB
1
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
DB
0
DB
17
8
DB
16
7
DB
15
5
DB
14
5
DB
13
4
DB
12
3
DB
11
2
DB
10
1
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
DB
9
0
Figure29: Instruction Format For 9-Bit Interface
1st Transmission
2nd Transmission
GRAM DATA
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure30: RAM Data Write Format For 9-Bit Interface
Timing Diagram
There are 4 timing conditions for 68-system 9-bit CPU interface, which are index write timing condition, data write
timing condition, data read timing condition and status read timing condition.
In this mode, 16-bit instructions and GRAM data are divided into two half words and the transfer starts from the
upper half word. Note that the upper byte must also be written when the index register is written.
Figure31: Timing Diagram of 68-System 9-Bit bus interface
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Preliminary
68-SYSTEM 8-BIT BUS INTERFACE
Bit Assignment
1st Transmission
2nd Transmission
INPUT DATA
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
17
8
DB
16
7
DB
15
6
DB
14
5
DB
13
4
DB
12
3
DB
11
2
DB
10
1
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Figure32: Instruction Format For 8-Bit Interface
1st Transmission
2nd Transmission
GRAM DATA
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
DB
17
8
DB
16
7
DB
15
6
DB
14
5
DB
13
4
DB
12
3
DB
11
2
DB
10
1
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure33: RAM Data Write Format For 8-Bit Interface
Timing Diagram
There are 4 timing conditions for 68-system 8-bit CPU interface, which are index write timing condition, data write
timing condition, data read timing condition and status read timing condition.
In this mode, 16-bit instructions and GRAM data are divided into two half words and the transfer starts from the
upper half word. Note that the upper byte must also be written when the index register is written.
Figure34: Timing Diagram of 68-System 8-Bit bus interface
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Preliminary
80-SYSTEM 18-BIT BUS INTERFACE
Bit Assignment
INPUT DATA
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
DB
0
Figure35: Instruction Format For 18-Bit Interface
GRAM DATA
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure36: RAM Data Write Format For 18-Bit Interface
Timing Diagram
There are 4 timing conditions for 80-system 18-bit CPU interface, which are index write timing condition, data write
timing condition, data read timing condition and status read timing condition.
Figure37: Timing Diagram of 80-System 18-Bit bus interface
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
80-SYSTEM 16-BIT BUS INTERFACE
Bit Assignment
INPUT DATA
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Figure38: Instruction Format For 16-Bit Interface
GRAM DATA
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure39: RAM Data Write Format For 16-Bit Interface
Timing Diagram
There are 4 timing conditions for 80-system 16-bit CPU interface, which are index write timing condition, data write
timing condition, data read timing condition and status read timing condition.
Figure40: Timing Diagram of 80-System 16-Bit bus interface
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
80-SYSTEM 9-BIT BUS INTERFACE
Bit Assignment
1st Transmission
2nd Transmission
INPUT DATA
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
DB
0
DB
17
8
DB
16
7
DB
15
6
DB
14
5
DB
13
4
DB
12
3
DB
11
2
DB
10
1
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
DB
0
9
Figure41: Instruction Format For 9-Bit Interface
1st Transmission
2nd Transmission
GRAM DATA
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure42: RAM Data Write Format For 9-Bit Interface
Timing Diagram
There are 4 timing conditions for 80-system 9-bit CPU interface, which are index write timing condition, data write
timing condition, data read timing condition and status read timing condition.
In this mode, 16-bit instructions and GRAM data are divided into two half words and the transfer starts from the
upper half word. Note that the upper byte must also be written when the index register is written.
Figure43: Timing Diagram of 80-System 9-Bit bus interface
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
80-SYSTEM 8-BIT BUS INTERFACE
Bit Assignment
1st Transmission
2nd Transmission
INPUT DATA
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Figure44: Instruction Format For 8-Bit Interface
1st Transmission
2nd Transmission
GRAM DATA
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
RGB Arrangement
R5
R4
R3
R2
R1
R0
G5
G4
G3
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure45: RAM Data Write Format For 8-Bit Interface
Timing Diagram
There are 4 timing conditions for 80-system 8-bit CPU interface, which are index write timing condition, data write
timing condition, data read timing condition and status read timing condition.
In this mode, 16-bit instructions and GRAM data are divided into two half words and the transfer starts from the
upper half word. Note that the upper byte must also be written when the index register is written.
Figure46: Timing Diagram of 80-System 8-Bit bus interface
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
68-/80-SYSTEM 8-/9-BIT INTERFACE SYNCHRONIZATION FUNCTION
The S6E63D6 supports the transfer synchronization function, which resets the upper/lower counter to count
upper/lower 8-/9-bit data transfer in the 8-/9-bit bus interface. Noise causing transfer mismatch between the upper
and lower bits can be corrected by a reset triggered by writing a “22h” instruction. The next transfer starts from the
upper bits. Executing synchronization function periodically can recover any runaway in the display system.
Figure47: 8-/9-bit Interface Transfer Synchronization
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
SERIAL PERIPHERAL INTERFACE
Setting the S_PB pin to the VDD3 level allows serial peripheral interface (SPI) transfer, using the chip select line
(CS*), serial transfer clock line (SCL), serial input data (SDI), and serial output data (SDO). For a serial interface, the
IM0/ID pin function uses an ID pin. If the chip is set up for serial interface, the DB17-0 pins are used only data bus of
RGB Interface.
The S6E63D6 initiates serial data transfer by transferring the start byte at the falling edge of CSB input. It ends serial
data transfer at the rising edge of CSB input.
The S6E63D6 is selected when the 6-bit chip address in the start byte matches the 6-bit device identification code
that is assigned to the S6E63D6. When selected, the S6E63D6 receives the subsequent data string. The least
significant bit (LSB) of the identification code can be determined by the ID pin. The five upper bits must be 01110.
Two different chip addresses must be assigned to a single S6E63D6 because the seventh bit of the start byte is
used as a register select bit (RS). That is, when RS = 0, data can be written to the index register or status can be
read, and when RS = 1, an instruction can be issued or data can be written to or read from RAM. Read or write
operation is selected according to the eighth bit of the start byte (R/W bit). The data is received when the R/W bit is
0, and is transmitted when the R/W bit is 1.
After receiving the start byte, the S6E63D6 receives or transmits the subsequent data byte-by-byte. The data is
transferred with the MSB first. All S6E63D6 instructions are 16 bits. Two bytes are received with the MSB first (DB17
to DB0), then the instructions are internally executed. After the start byte has been received, the first byte is fetched
as the upper eight bits of the instruction and the second byte is fetched as the lower eight bits of the instruction.
Four bytes of RAM read data after the start byte are invalid. The S6E63D6 starts to read correct RAM data from the
fifth byte.
Table45: Start Byte Format
1
2
3
4
Transfer bit
S
Start byte format
Transfer start
5
Device ID code
0
1
1
1
0
NOTE: ID bit is selected by the ID_MIB pin.
RS
0
0
Table46: RS and R/W Bit Function
R/W
Function
0
Set index register
1
Read status
Bit Assignment
Figure48: Bit Assignment of Instructions on SPI
88
6
ID
7
8
RS
R/W
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Timing Diagram
Figure49: Basic Timing Diagram of Register Data Transfer through SPI
Figure50: Timing Diagram of Consecutive Register Data-Write through SPI
Figure51: Timing Diagram of Register Read through SPI
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
INDEX AND PARAMETER RECOGNITION
If more parameter command is being sent, exceed parameters are ignored.
Figure52: Index and parameter recognition with 8-/9-bit interface
Figure53: Index and parameter recognition with 18-/16-bit interface
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
EXTERNAL DISPLAY INTERFACE
The following interfaces are available as external display interface. It is determined by bit setting of RIM1-0. RAM
accesses can be performed via the RGB interface.
RIM1
0
0
1
1
RIM0
0
1
0
1
Table47: RIM Bits
RGB Interface
18-bit RGB interface
16-bit RGB interface
6-bit RGB interface
Setting disabled
DB Pin
DB17 to 0
DB17 to10, 8 to 1
DB8 to3
ENABLE SIGNAL
The relationship between EPL and ENABLE signals is shown below. When ENABLE is not active, the address is not
updates. When ENABLE is active, the address is updated.
EPL
0
0
1
1
Table48: Relationship between EPL and ENABLE
ENABLE
RAM WRITE
RAM ADDRESS
0
Valid
Updated
1
Invalid
Hold
0
Invalid
Hold
1
Valid
Update
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
18-Bit RGB interface
Bit Assignment
Figure54: Bit Assignment of GRAM Data on 18bit RGB Interface
16-Bit RGB interface
Bit Assignment
Figure55: Bit Assignment of GRAM Data on 16bit RGB Interface
Timing Diagram
1 Frame
VSYNC
>= 1H
A
Back Porch
1H
Front Porch
HSYNC
DOTCLK
ENABLE
DB[17:0]
B
HSYNC
>= 256CLK
1CLK
DOTCLK
ENABLE
DB[17:0]
Figure56: Timing Diagram of 18/16bit RGB Interface
[NOTE]
92
1. 1 HSYNC Period must be >= 256 DOTCLK
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
6-Bit RGB interface
In order to transfer data on 6bit RGB Interface there should be three transfers.
Bit Assignment
Figure57: Bit Assignment of GRAM Data on 6bit RGB Interface
Timing Diagram
Figure58: Timing Diagram of 6bit RGB Interface
[NOTE]
1. Three clocks are regarded as one clock for transfer when data is transferred in 6-bit interface.
VSYNC, HSYNC, ENABLE, DOTCLK, and DB[8:3] should be transferred in units of three clocks.
2. 1 HSYNC Period must be >= 256 * 3 DOTCLK
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
Transfer Synchronization
Figure59: Transfer Synchronization Function in 6-bit RGB Interface mode
[NOTE] The figure shows Transfer Synchronization function for 6bit RGB Interface. S6E63D6 has a transfer counter to count 1st,
2nd and 3rd data transfer of 6bit RGB Interface. The transfer counter is reset on the falling edge of HSYNC and enters the 1st data
transmission state. Transfer mismatch can be corrected at every new transfer restarts with HSYNC signal. In this method, when
data is consecutively transferred in such a way as displaying motion pictures, the effect of transfer mismatch will be reduced and
recovered by normal operation.
[NOTE] The internal display is operated in units of three DOTCLKs. When DOTCLK is not input in units of pixels, clock mismatch
occurs and the frame, which is operated, and the next frame are not displayed correctly.
Time chart for RGB interface is shown below. (In case of EPL = 0)
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Preliminary
INTERFACE SWAPPING FOR MEMORY ACCESS
DISPLAY MODES AND GRAM ACCESS CONTROL
Display mode and RAM Access is controlled as shown below. For each display status, display mode control and
RAM Access control are combined properly.
Table49: DISPLAY MODE & RAM ACCESS CONTROL
Display Status
GRAM Access (RM)
Display Mode (DM)
Internal Clock Operation
(Still Picture Display)
System Interface
(RM = 0)
Internal Clock Operation
(DM = 0)
RGB I/F
(Displaying Motion Picture)
RGB Interface
(RM = 1)
External Clock Operation
(DM = 1)
MDDI interface
(Displaying motion Pictures)
System interface
(RM=0)
MDDI interface (D=0)
[NOTE 1] Only system interface can set Instruction register.
[NOTE 2] When the RGB Interface is being operated do not change the RGB Interface mode (RIM).
Internal Clock Operation mode with System Interface
Every operation in Internal Clock Operation mode is done in synchronization with the internal clock which is
generated by internal OSC. The signals input through RGB interface are all meaningless. Access to internal GRAM
is done via system interface.
External Clock Operation mode with RGB Interface
In External Clock Operation mode, frame sync signal (VSYNC), line sync signal (HSYNC) and DOTCLK are used for
display operation. Display data is transferred in the unit of pixel through DB bus and saved to GRAM.
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
USAGE ON EXTERNAL DISPLAY INTERFACE
1. When external display interface is in use, the following functions are not available.
Table50: External Display Interface and Internal Display Operation
Function
External Display Interface
Internal Display Operation
Partial Display
Not Available
Available
Scroll Function
Not Available
Available
Rotation
Not Available
Available
Mirroring
Not Available
Available
Window Function
Not Available
Available
2. VSYNC, HSYNC, and DOTCLK signals should be supplied during display operation via RGB interface.
3. RGB data are transferred for three clock cycles in 6-bit RGB interface. Data transferred, therefore, should be
transferred in units of RGB.
4. Interface signals, VSYNC, HSYNC, DOTCLK, ENABLE and DB17-0 should be set in units of RGB (pixels) to
match RGB transfer.
5. Transitions between internal operation mode and external display interface should follow the mode transition
sequence shown below.
6. During the period between the completion of displaying one frame data and the next VSYNC signal, the display
will remain front porch period.
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
MDDI (MOBILE DISPLAY DIGITAL INTERFACE)
INTRODUCTION OF MDDI
The S6E63D6 supports MDDI. The MDDI is a differential & serial interface with high speed. Both command and
image data transfer can be achieved with MDDI.
MDDI host & client are linked with Data and STB line. Through Data line, command or image data is transferred from
MDDI host to MDDI client, and vice versa. Data is transferred by packet unit.
Through STB line, strobe signal is transferred. When the link is in “FORWARD direction”, data is transferred from
host to client; in “REVERSE direction”, client transfer reverse data to MDDI host.
Forward Direction
Reverse Direction
DATA+
DATA-
DATA+
DATA-
STB+
STB-
STB+
STB-
Host GND
Host Pwr
MDDI HOST
MDDI CLIENT
Figure60: Physical connection of MDDI host and client
DATA-STB ENCODING
Data is encoded using a DATA-STB method. DATA is carried over a bi-directional differential cable, while STB is
carried over a unidirectional differential cable driven only by the host. Figure below illustrates how the data
sequence “1110001011” is transmitted using DATA-STB encoding.
Figure61: Data-STB encoding
The Following figure shows a sample circuit to generate DATA and STB from input data, and then recover the input
data from DATA and STB.
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
Figure62: Data / STB Generation & Recovery circuit
MDDI DATA / STB
The Data (MDP/MDN) and STB(MSP/MSN) signals are always operated in a differential mode to maximize noise
immunity. Each differential pair is parallel-terminated with the characteristic impedance of the cable. All
parallel-terminations are in the client device. Figure below illustrates the configuration of the drivers, receivers, and
terminations. The driver of each signal pair has a differential current output. While receiving MDDI packets the
MDDI_DATA and MDDI_STB pairs use a conventional differential receiver with a differential voltage threshold of
zero volts. In the hibernation state the driver outputs are disabled and the parallel termination resistors pull the
differential voltage on each signal pair to zero volts. During hibernation a special receiver on the MDDI_DATA pairs
has an offset input differential voltage threshold of positive 125 mV, which causes the hibernation line receiver to
interpret the un-driven signal pair as logic-zero level.
HOST
CLIENT
MDDI STB+
STB(host)
Rterm
VT = 0
Rterm
VT = 0
STB(client)
MDDI STBEnable(host)
MDDI DATA+
Data
(host to client)
Data
(host to client)
MDDI DATAEnable(client)
Data
(client to host)
VT = 0
wake-up
(client to host)
VT =
125mV
Data
(client to host)
VT =
125mV
wake-up
(host to client)
Figure63: Differential connection between host and client
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
HIBERNATION / WAKE-UP
S6E63D6 support hibernation mode for reducing interface power consumption.
The MDDI link can enter the hibernation state quickly and wake up from hibernation quickly. This allows the system
to force the MDDI link into hibernation frequently to reduce power consumption.
In hibernation mode, hi-speed transceivers and receivers are disabled and low-speed & low-power receivers are
enabled to detect wake-up sequence.
HOST
CLIENT
OFF
OFF
MDDI STB+
STB(host)
Rterm
VT = 0
STB(client)
MDDI STBEnable(host)
OFF
OFF
MDDI DATA+
Data
(host to client)
Rterm
VT = 0
Data
(host to client)
MDDI DATA-
OFF
Data
(client to host)
VT =
125mV
Enable(client)
Data
(client to host)
VT = 0
ON
wake-up
(client to host)
OFF
ON
VT =
125mV
wake-up
(host to client)
Figure64: MDDI Transceiver / Receiver state in hibernation
When the link wakes up from hibernation the host and client exchange a sequence of pulses. These pulses can be
detect using low-speed, low-power receivers that consume only a fraction of the current of the differential receivers
required to receive the signals at the maximum link operating speed.
Both the client and the host can wake up the link, so 2-types of wake-up are supported in S6E63D6: Host-initiated
link wakeup and Client-initiated link wakeup.
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S6E63D6 PRELIMINARY VER. 0.0
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Preliminary
MDDI LINK WAKE-UP PROCEDURE
Rules for Entering the Hibernation State :
z The host sends 64 MDDI_Stb cycles after the CRC of the Link Shutdown Packet. Also after this CRC the host
shall drive MDDI_Data0 to a logic-zero level and disable the MDDI_Data0 output of the host in the range of after
the rising edge of the 16th to before the rising edge of the 48th MDDI_Stb cycles (including output disable
propagation delays).
z The host shall finish sending the 64 MDDI_Stb cycles after the CRC of the Link Shutdown packet before it
initiates the wake-up sequence.
z The client shall wait until after the rigins edge of the 48th MDDI_Stb cycle after the CRC of the Link Shutdown
Packet or later before it drives MDDI_Data0 to a logic-one level to attempt to wake-up the host.
z The client shall place its high-speed receivers for MDDI_Data0 and MDDI_Stb into hibernation any time after the
rising edge of the 48th MDDI_Stb cycle after the CRC of the Link Shutdown Packet. It is recommended that the
client place its high-speed MDDI_Data0 and MDDI_Stb receivers into hibernation before the rising edge of the
64th MDDI_Stb cycle after the CRC of the Link Shutdown Packet.
Rules for Wake-up from the Hibernation State :
z When the client needs service from the host it generates a request pulse by driving MDDI_Data0 to a logic-one
level for 70 to 1000μsec while MDDI_Stb is inactive and keeps MDDI_Data0 driven to a logic-one level for 70
MDDI_Stb cycles(range of 60 to 80) after MDDI_Stb becomes active. Then the client disables the MDDI_Data0
driver by placing it into a high-impedance state.
z If MDDI_Stb is active during hibernation(which is unlikely, but allowed per the spec) then the client may only drive
MDDI_Data0 to a logic one level for 70 MDDI_Stb cycles (range of 60 to 80). This action causes the host to
restart data traffic on the forward link and to poll the client for its status.
z The host shall detect the presence of the request pulse from the client (using the low-power differential receiver
with a +125mV offset) and begin the startup sequence by first driving MDDI_Stb to a logic-zero level and
MDDI_Data0 to a logic-high level for at least 200nsec, and then while toggling MDDI_Stb it shall continue to drive
MDDI_Data0 to a logic-one level for 150 MDDI_Stb cycles (range of 140 to 160) and to logic-zero for 50
MDDI_Stb cycles. The client shall not send a service request pulse if it detects MDDI_Data0 at a logic-one level
for more than 80 MDDI_Stb cycles. After the client has detected MDDI_Data0 at a logic-one level for 60 to80
MDDI_Stb cycles it shall begin to search for the interval where drives MDDI_Data0 to a logic-zero level for 50
MDDI_Stb cycles then the host starts sending packets on the link. The first packet sent shall be a Sub-frame
Header Packet. The client begins to look for the Sub-frame header Packet after MDDI_Data0 is at a logic-zero
level for 40 MDDI_Stb cycles of the 50 cycle interval.
z The host may initiate the wake-up by first enabling MDDI_Stb and simultaneously drive it to a logic-zero level.
MDDI_Stb shall not be driven to a logic-one level until pulses are output as described below. After MDDI_Stb
reaches a valid logic-zero level the host shall enable MDDI_Data0 and simultaneously drive it to a logic-one level.
MDDI_Data0 shall not be driven to a logic-zero level during the wake-up process until the interval where it is
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driven to a logic-zero level for an interval of 50 MDDI_Stb pulses as described below. The host shall wait at least
200 nsec after MDDI_Data0 reaches a valid logic-one level before driving pulses on MDDI_Stb. This timing
relationship shall always occur while considering the worst-case output enable delays. This guarantees that the
client has sufficient time to fully enable its MDDI_Stb receiver after being woken up by a logic-one level on
MDDI_Data0 that was driven by the host.
Figure65: Process from entering Hibernation To exiting Hibernation
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1) Host-initiated Link Wake-up Procedure
The simple case of a host-initiated wake-up is described below without contention from the client trying to wake up at
the same time. The following sequence of events is illustrated in the following figure.
Figure66: Host-initiated link wakeup sequence
The Detailed descriptions for labeled events are as follows:
A. The host sends a Link Shutdown Packet to inform the client that the link will transition to the low-power
hibernation state.
B. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for 64 cycles to allow processing in
the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in the client device.
Also during this interval the host initially sets MDDI_Data0 to a logic-zero level, and then disables the MDDI_Data0
output in the range of 16 to 48 MDDI_Stb cycles (including output disable propagation delays) after the CRC.
It may be desirable for the client to place its high-speed receivers for MDDI_Data0 and MDDI_Stb into a low power
state any time after 48 MDDI_Stb cycles after the CRC and before point C.
C. The host enters the low-power hibernation state by disabling the MDDI_Data0 and MDDI_Stb drivers and by
placing the host controller into a low-power hibernation state.
It is also allowable for MDDI_Stb to be driven to logic-zero level or to continue toggling during hibernation.
The client is also in the low-power hibernation state.
D. After a while, the host begins the link restart sequence by enabling the MDDI_Data0 and MDDI_Stb driver
outputs. The host drives MDDI_Data0 to a logic-one level and MDDI_Stb to logic-zero level for at least the time it
takes for the drivers to fully enable their outputs.
The host shall wait at least 200 nsec after MDDI_Data0 reaches a valid logic-one level and MDDI_Stb reaches a
valid logic-zero level before driving pulses on MDDI_Stb. This gives the client sufficient time to prepare to receive
high-speed pulses on MDDI_Stb. The client first detects the wake-up pulse using a low-power differential receiver
having a +125mV input offset voltage.
E. The host drivers are fully enabled and MDDI_Data0 is being driven to a logic-one level.
The host begins to toggle MDDI_Stb in a manner consistent with having a logic-zero level on MDDI_Data0 for a
duration of 150 MDDI_Stb cycles.
F. The host drives MDDI_Data0 to logic-zero level for 50 MDDI_Stb cycles. The client begins to look for the
Sub-frame Header Packet after MDDI_Data0 is at logic-zero level for 40 MDDI_Stb cycles.
G. The host begins to transmit data on the forward link by sending a Sub-frame Header Packet.
Beginning at point G the MDDI host generates MDDI_Stb based on the logic level on MDDI_Data0 so that proper
data-strobe encoding commences from point G.
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Figure67: Host-initiated link wakeup sequence
2) Client-initiated Link Wake-up Procedure
An example of a typical client-initiated service request event with no contention is illustrated in the following figure.
Figure68: Client-initiated link wake-up sequence
The Detailed descriptions for labeled events are as follows:
A. The host sends a Link Shutdown Packet to inform the client that the link will transition to the low-power
hibernation state.
B. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for 64 cycles to allow processing in
the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in the client device.
Also during this interval the host initially sets MDDI_Data0 to a logic-zero level, and then disables the MDDI_Data0
output in the range of 16 to 48 MDDI_Stb cycles (including output disable propagation delays) after the CRC.
It may be desirable for the client to place its high-speed receivers for MDDI_Data0 and MDDI_Stb into a low power
state any time after 48 MDDI_Stb cycles after the CRC and before point C.
C. The host enters the low-power hibernation state by disabling its MDDI_Data0 and MDDI_Stb driver outputs.
It is also allowable for MDDI_Stb to be driven to logic-zero level or to continue toggling during hibernation.
The client is also in the low-power hibernation state.
D. After a while, the client begins the link restart sequence by enabling the MDDI_Stb receiver and also enabling an
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offset in its MDDI_Stb receiver to guarantee the state of the received version of MDDI_Stb is a logic-zero level in the
client before the host enables its MDDI_Stb driver.
The client will need to enable the offset in MDDI_Stb immediately before enabling its MDDI_Stb receiver to ensure
that the MDDI_Stb receiver in the client is always receiving a valid differential signal and to prevent erroneous
received signals from propagating into the client.
After that, the client enables its MDDI_Data0 driver while driving MDDI_Data0 to a logic-one level. It is allowed for
MDDI_Data0 and MDDI_Stb to be enabled simultaneously if the time to enable the offset and enable the standard
MDDI_Stb differential receiver is less than 200 nsec.
E. Within 1 msec the host recognizes the service request pulse, and the host begins the link restart sequence by
enabling the MDDI_Data0 and MDDI_Stb driver outputs.
The host drives MDDI_Data0 to a logic-one level and MDDI_Stb to a logic-zero level for at least the time it takes for
the drivers to fully enable their outputs. The host shall wait at least 200 nsec after MDDI_Data0 reaches a valid
logic-one level and MDDI_Stb reaches a valid fully-driven logic-zero level before driving pulses on MDDI_Stb.
This gives the client sufficient time to prepare to receive high-speed pulses on MDDI_Stb.
F. The host begins outputting pulses on MDDI_Stb and shall keep MDDI_Data0 at a logic-one level for a total
duration of 150 MDDI_Stb pulses through point H. The host generates MDDI_Stb in a manner consistent with
sending a logic-zero level on MDDI_Data0. When the client recognizes the first pulse on MDDI_Stb it shall disable
the offset in its MDDI_Stb receiver.
G. The client continues to drive MDDI_Data0 to a logic-one level for 70 MDDI_Stb pulses, and the client disables its
MDDI_Data0 driver at point G. The host continues to drive MDDI_Data0 to a logic-one level for duration of 80
additional MDDI_Stb pulses, and at point H drives MDDI_Data0 to logic-zero level.
H. The host drives MDDI_Data0 to logic-zero level for 50 MDDI_Stb cycles. The client begins to look for the
Sub-frame Header Packet after MDDI_Data0 is at logic-zero level for 40 MDDI_Stb cycles.
I. After asserting MDDI_Data0 to logic-zero level and driving MDDI_Stb for duration of 50 MDDI_Stb pulses the
host begins to transmit data on the forward link at point I by sending a Sub-frame Header Packet.
The client begins to look for the Sub-frame Header Packet after MDDI_Data0 is at logic-zero level for 40 MDDI_Stb
cycles.
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Figure69: Client-initiated link wake-up sequence
S6E63D6 supports 2-types of client-initiated link wake-up: VSYNC based Link Wake-up & GPIO based Link
Wake-up. As client-initiated wake-up action is executed in hibernation state only, register setting for each wake-up
have to be set before link shut-down.
VSYNC Based Link Wake-up
In display-ON state, when the IC finishes displaying all internal GRAM data, data request must be transferred to
MDDI host for new video data. As MDDI link is usually in hibernation for reducing interface power consumption,
MDDI link wake-up must be done before internal GRAM update. In that case, client initiated link wake-up can be
used as data request.
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When VSYNC based link wake-up register (50h: VWAKE_EN) is set, client initiated wake-up is executed in
synchronization with the vertical-sync signal which generated in S6E63D6.
Using VSYNC based link wake-up, tearing-less display can be accomplished if interface speed and wake-up time is
well known.
The following figure shows detailed timing for VSYNC based link wake-up.
SYNC STATE
A
HIBERNATION STATE
B
WAKE-UP STATE
C D
SYNC STATE
E F
VWAKE_EN
link_active
frame_update
client_wakeup
Figure70: VSYNC based link wake-up procedure
The Detailed descriptions for labeled events are as follows:
A. MDDI host writes to the VSYNC based link wakeup register to enable a wake-up based on internal vertical-sync
signal.
B. link_active goes low when the host puts in the link into hibernation after no more data needs to be sent to the
S6E63D6.
C. frame_update, the internal vertical-sync signal goes high indicating that update pointer has wrapped around and
is now reading from the beginning of the frame buffer. Link wake-up point can be set using WKF and WKL (51h)
registers. WKF specifies the number of frame before wake-up; WKL specifies the number of lines before wake-up.
D. client_wakeup input to the MDDI client goes high to start the client initiated link wake-up.
E. link_active goes high after the host brings the link out of hibernation.
F. After link wake-up, client_wakeup signal and the VWAKE_EN register are cleared automatically.
GPIO Based Link Wake-up
In VSYNC-based link wake-up, wake-up enable register setting prior to link shut-down. GPIO based Link wake-up is
enabled by interrupt from outside of the IC. For GPIO based link wake-up, GPIO interrupt enable and GPIO PAD
mode (to input mode) setting must be set. Once S6E63D6 receive interrupt, internal GPIO base link wake-up flag set
to high, and the following procedure is similar to that of VSYNC based link wake-up.
The following figure shows detailed timing for GPIO based link wake-up.
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SYNC STATE
A
HIBERNATION STATE
B
C
WAKE-UP STATE
D E
SYNC STATE
F G
H
GPIO_EN
link_active
GPIO(input)*
GPIO_INT*
frame_update
client_wakeup
Figure71: GPIO based link wake-up procedure
The Detailed descriptions for labeled events are as follows:
A. Host sets the GPIO interrupt enable register (69h: GPIO_EN) for a particular GPIO through register access
packet.
B. Link goes into hibernation (and link_active)goes low) when the host has no more data to send to the IC.
C. GPIO input goes high, and the GPIO interrupt (GPIO_INT) is latched.
D. Frame_update signal goes high indicating that the display has wrapped around. Link wake-up point can be set
using WKF and WKL (51h) registers.
E. Client_wakeup input to the MDDI client goes high to start the client initiated link wake-up.
F. Link_active goes high after the host brings the link out of hibernation.
G. After link wake-up, client_wakeup signal is reset to low.
H. MDDI host clears the interrupt by writing to the interrupt clear register with the bit set for that particular interrupt
(GPCLR: 68h). Between point G and H the host will have read the GPIO_INT values to see what interrupts are
active.
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GPIO CONTROL
S6E63D6 offers 10(maximum) GPIO that can be used as input or output independently.
Some application or device on the upper clamshell needs several control signals which are supplied by base band
modem or application processor directly. If number of application on the upper clamshell increases, also control
signals increase, causing the interface more costly.
In S6E63D6, GPIO can be the solution for that problem. User may control the 10 GPIOs as input or output by use of
simple register setting. So additional connection between base band modem / AP (application processor) and
components on upper clamshell are not needed.
The following table shows several set of register for GPIO.
Register
GPIO
(66h)
GPIO_CON
(67h)
width
Write
[9:0]
For GPIO output mode: output GPIO register(66h) value to GPIO
PAD
Read
GPIO PAD status
Write
GPIO PAD input/output mode control : (0 : input / 1 : output)
[9:0]
GPCLR
(68h)
[9:0]
GPIO_EN
(69h)
[9:0]
GPPOL
(6Ah)
Description
Reset value
10’h000
10’h000
Read
GPIO_CON (67h) register value
Write
For GPIO input mode: clear specified GPIO interrupt (set by
GPIO PAD input).
Read
GPIO interrupt state (set by GPIO PAD input).
Write
For GPIO input mode: enable specified GPIO interrupt
10’h000
10’h000
Read
GPIO_EN (69h) register value.
Write
For GPIO input mode: GPIO interrupt polarity setting
[9:0]
10’h3FF
Read
GPPOL (6Ah) register value.
In GPIO output mode, the IC output GPIO (66h) register value to the defined PAD.
Set GPIO_CON register as output mode before use GPIO output.
10 different GPIO output can be controlled simultaneously using 1-register access packet (66h register access) so
that minimum access time for each GPIO output will be 1-register access time.
GPIO input mode can only be used as client-initiated link wake-up.
For more information, refer to GPIO based link wake-up section.
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3) Host-initiated Wake-up from Hibernation with Connection from client
This is actually a host-initiated wake-up, but we have included the case where the client also wants to wake up the
link with the latest possible request. The labeled events are :
A. The host sends a Link Shutdown Packet to inform the client that the link will transition to the low-power
hibernation state.
B. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for 64 cycles to allow
processing in the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in
the client device. Also during this interval the host disables the MDDI_Data0 output in the range of 16 to 48
MDDI_Stb cycles(including output disable propagation delays) after the CRC. It may be desirable for the
client to place its high-speed receivers for MDDI_Data0 and MDDI_Stb into a low power state any time after
48 MDDI_Stb cycles after the CRC and before point C.
C. The host enters the low-power hibernation state by disabling its MDDI_Data0 and MDDI_Stb driver outputs.
It is also allowable for MDDI_Stb to be driven to a logic-zero level or to continue toggling during hibernation.
The client is also in the low-power hibernation state.
D. After a while, the host begins the link restart sequence by enabling the MDDI_Data0 and MDDI_Stb driver
outputs. The host drives MDDI_Data0 to a logic-one level and MDDI_Stb to a logic-zero level for at least the
time it takes for the drivers to fully enable their outputs. The host shall wait at least 200 nsec after
MDDI_Data0 reaches a valid logic-one level and MDDI_Stb reaches a valid logic-zero level before driving
pulses on MDDI_Stb. This gives the client sufficient time to prepare to receive high-speed pulses on
MDDI_Stb.
E. The host drivers are fully enabled and MDDI_Data0 is being driven to a logic-one level. The host begins to
toggle MDDI_Stb in a manner consistent with having a logic-zero level on MDDI_Data0 for a duration of 150
MDDI_Stb cycles.
F. At up to 70 MDDI_Stb cycles after point E the client has not yet recognized that the host is driving
MDDI_Data0 to a logic-one level so the client also drives MDDI_Data0 to a logic-one level. This occurs
because the client has a need to request service from the host and does not recognize that the host has
already begun the link restart sequence.
G. The client ceases to drive MDDI_Data0, and places its driver into a high-impedance state by disabling its
output. The host continues to drive MDDI_Data0 to a logic-one level for 80 additional MDDI_Stb cycles.
H. The host drives MDDI_Data0 to a logic-zero level for 50 MDDI_Stb cycles. The client begins to look for the
Sub-frame Header Packet after MDDI_Data0 is at a logic-zero level for 40 MDDI_Stb cycles.
I. The host begins to transmit data on the forward link by sending a Sub-frame Header Packet. Beginning at
point I the MDDI host generates MDDI_Stb based on the logic level on MDDI_Data0 so that proper
data-strobe encoding commences from point I.
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Figure72: Host-initiated Wake-up process from Hibernation with Connection from client
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MDDI PACKET
MDDI transfer data by packet format. MDDI host can make many packets and transfer them.
In S6E63D6, several packets format is supported. Most packets are transferred from MDDI host to client (forward
direction); but reverse encapsulation packet is transferred from MDDI client to host (reverse direction).
A number of packets, started by sub-frame header packet, construct 1 sub frame.
Figure73: MDDI packet structure
Refer to MDDI packet structure, sub-frame header packet is placed in front of a sub-frame, and some sub-frame
construct media-frame together.
The following table describes 9 types of packet which is supported in S6E63D6.
PACKET
Sub-frame header packet
Register access packet
Video stream packet
Filler packet
Reverse link encapsulation packet
Round-trip delay measurement packet
Client capability packet
Clinet request and status packet
FUNCTION
Header of each sub frame
Register setting
Video data transfer
Fill empty packet space
Reverse data packet
Host->client->host delay check
Capability of client check
Information about client status
DIRECTION
Forward
Forward
Forward
Forward
Reverse
Forward/Reverse
Reverse
Reverse
Link shutdown packet
End of frame
Forward
Sub-frame header packet
Figure74: Sub-frame header packet structure
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Register access packet
Figure75: Register access packet structure
Video Stream packet
Figure76: Video stream packet structure
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Filler packet
Figure77: Filler packet structure
Link shutdown packet
Figure78: Link shutdown packet structure
: fixed value
For More information about MDDI packet, please refer to VESA MDDI spec.
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MDDI OPERATING STATE
In MDDI, six operation modes are available. The following table describes six modes.
STATE
OSC
Step-up
Circuit
SLEEP
ON
Disabled
WAIT
ON
Disabled
Normal
ON
Enabled
NAP
ON
IDLE
STOP
Internal Logic status
Display OFF
MDDI Link hibernation
Display OFF
MDDI Link in SYNC
MDDI I/O
Hibernation driver ON
Wake-up by
Host –
Initiated
standard driver ON
-
Display ON
MDDI Link in SYNC
standard driver ON
-
Disabled
Display OFF
MDDI Link in SYNC
standard driver ON
-
ON
Enabled
Display ON
MDDI Link hibernation
Hibernation driver ON
Host – Initiated
Client – Initiated
(Vsync, GPIO)
OFF
Disabled
Display OFF
MDDI Link OFF
Driver All OFF
RESET
SLEEP: Initial status when external power is connected to the IC.
In this state, internal oscillator is operating, and MDDI link is in hibernation state.
As no command or signal is applied to the IC except RESET input, internal logic or step-up circuit is OFF.
WAIT: After the wake-up sequence, the IC is in WAIT state. MDDI link is in SYNC, and internal logic or step-up
is still OFF because no other register access or video stream packet is transferred to the IC.
NORMAL: MDDI link, step-up circuit, and internal logic circuit is ON. Register access or Video data transfer is
available in NORMAL state.
IDLE: When no more video data update is needed, MDDI link is in hibernation so that interface power can be
reduced. Internal step-up & logic circuits are still operating. MDDI link wakeup will be accomplished when
vsync wakeup register is set before hibernation or GPIO interrupt is set.
NAP: This state is set by register access. Step-up and Internal logic is OFF, but MDDI link is ON.
MDDI link have to be in SYNC because the IC must receive commands for power save or normal operation
STOP: STOP state is set by register access (R10h). In this state, MDDI link, internal oscillator, step-up, and logic
circuit are all OFF. To release STOP state, input reset signal. After reset, status is SLEEP state.
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System power ON
POWER ON
System Reset input
- OSC : OSC ON
- Step-up : Disabled
- MDDI link : Hibernation
- Logic : Display OFF
SLEEP
MDDI link synchronization procedure
- OSC : OSC ON
- Step-up : Disabled
- MDDI link : in SYNC
- Logic : Display OFF
WAIT
1) Power setting using register packet
2) Step-up enable sequence using register packet
3) Frame buffer access using video packet
4) Display ON sequence using register packet
- OSC : OSC ON
- Step-up : Enabled
- MDDI link : in SYNC
- Logic : Display ON
NORMAL
D
M
3
k
in
2
IL
D
1
1
NAP state set sequence
1) Display OFF sequence using register packet
2) NAP state setting(SLP=1) using register packet
2
NAP state release sequence
1) NAP state register disable
2) Step-up enable sequence
3) Frame buffer update (optional)
4) Display ON sequence
3
ak
w
IDLE state (when frame buffer update not needed)
1) Vsync wakeup enable register setting (optional)
2) Link shut-down using link shut-down packet
(MDDI link is in hibernation state)
!
up
e-
NAP
IDLE
- OSC: OSC ON
- Step-up: Disabled
- MDDI link: in SYNC
- Logic: Display OFF
- OSC: OSC ON
- Step-up: Enabled
- MDDI link:Hibernation
- Logic: Display ON
- VSYNC wakeup
- GPIO wakeup
- Host initiated wakeup
- STOP state setting using register packet
(both standard & offset receiver disabled)
STOP
- OSC: OSC OFF
- Step-up: Disabled
- MDDI link:Link disabled
- Logic: Display OFF
Only RESET signal is
admitted for wake-up
from STOP state !
Figure79: Operating state in MDDI mode
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TEARING-LESS DISPLAY
In S6E63D6, the matching between data write timing and written data display timing is important. If timing is
mismatched, tearing effect can occur.
To avoid display tearing effect, two possible ways are suggested.
First case is that data write is slower than speed of displaying written data. In this case, data write speed is not
critical, but current consumption in interface will be increased because data transfer time is long. Data write time is
selected widely (?) in this case.
Other case is that data write is faster than speed of displaying written data. In this case, data update speed is very
high so that transfer time is short. So current consumption in interface can be minimized, but it requires fast data
transfer. The most important thing is to avoid data scan conflicts with data update.
The following figures describe some examples to avoid display tearing phenomenon.
.
1. Display speed is faster than data write.
Figure80: Tearing-less display: display speed is faster than data write
2. Display speed is slower than data write.
Figure81: Tearing-less display: data write speed is faster than display
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SUB PANEL CONTROL
S6E63D6 support sub panel control function which controls sub panel driver IC using 80-mode protocol (CSB, RS,
WRB & DB). When MDDI host (Base band modem) sends several packets to S6E63D6, if the packet is for sub panel,
the IC converts the packet to 80-mode protocol & sends them to sub panel driver IC. So separated line for sub panel
control are not needed. After all, S6E63D6 enables the sub panel driver IC which doesn’t support MDDI to be
applied to the system. S6E63D6 supports only 80-mode 18/16 bit format for sub panel control.
Main Panel (MDDl-Supported LDI)
Sub Panel (Normal LDI)
TFT-LCD Module
(SUB display)
OLED Module
(MAIN display)
LCD driver IC
LCD driver IC
MDDI
80 mode Parallel I/F
MDDI HOST
MDDI TRX/ RX
MSM (Baseband Modem)
Figure82: Schematic diagram of sub panel control function
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Preliminary
MAIN / SUB PANEL SELECTION
Using 7Ah register (7Ah address can be changed using SUB_SEL register), main / sub panel data path can be selected.
When S6E63D6 receives register access packet (Initially 7Ah index) from MDDI host, it decodes the packet and checks
the last bit of the register data field is ‘1’ or ‘0’. If the last bit is ‘0’, the following register access packet or video stream
packet is transferred to the sub panel control signal generation block.
Sub panel selection address (Initially 7Ah) can be changed using SUB_SEL register. Do not change the SUB_SEL value
to previously occupied address.
Register Address = SUB_SEL
Register Data = 0000h
SUB panel Selection Procedure
Command Transfer
(Register Access packet)
Command / Data transfer to Sub
Panel driver IC (80-mode protocol)
Video Data Transfer
(Video Stream packet)
Register Address = SUB_SEL
Register Data = 0001h
MAIN panel Selection Procedure
Note: Initial value of SUB_SEL = 7Ah
Figure83: Main / Sub panel selection procedure
When video data is transferred to the sub panel driver IC via S6E63D6, additional GRAM access command
(normally 22h) is automatically generated in S6E63D6.
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Preliminary
SUB PANEL CONTROL TIMING
1. TFT type sub panel timing
1.1 Register data transfer timing
If sub panel is selected, and sub panel type is TFT, register setting is executed like below figure.
Register data is transferred through S_DB[17:10] & S_DB[8:1] in 18/16 bit type. If 9/8 bit type is used, data is transferred
thorough S_DB[17:10]. Refer to sub panel control(15h index) section.
1 Register Access Packet
MDDI
Data
Stream
Register
Address
Header
C
R
C
(0007h)
S_DB[17:0]
Register
Data
(030Fh)
C
R
C
0000Eh
00C1Eh
(index 07h)
(030Fh 16bit data)
S_CSB
S_RS
S_WRB
index write
parameter write
Figure84: 18/16 bit type register access data transfer
In 9/8 bit mode, S_DB[17:10] is used. In this mode, data is transferred at two times. First transfer is MSB 8bit and
second transfer is LSB 8bit.
1 Register Access Packet
MDDI
Data
Stream
Header
Register
Address
(0007h)
S_DB[17:10]
C
R
C
Register
Data
(030Fh)
C
R
C
00h
07h
03h
0Fh
(MSB 8bit)
(LSB 8bit)
(MSB 8bit)
(LSB 8bit)
S_CSB
S_RS
S_WRB
index write
parameter write
Figure85: 9/8 bit type register access data transfer
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Preliminary
This figure shows register setting in 18/16 bit & 68 mode. In 68 mode, S_WRB must be connected to E_RDB of sub
panel module. RW_WRB of sub panel module must be tied to VSS. Because S6E63D6 only writes data to sub panel
module.
1 Register Access Packet
MDDI
Data
Stream
Register
Address
Header
(0007h)
S_DB[17:0]
C
R
C
Register
Data
(030Fh)
C
R
C
0000Eh
00C1Eh
(index 07h)
(030Fh 16bit data)
S_CSB
S_RS
S_WRB
index write
parameter write
Figure86: 68 mode 18 bit register data transfer
1.2 Video data transfer timing
In TFT type sub panel, STN_EN register in 15h index is “0”, and if user wants to use 68-mode interface protocol, then
MPU_MODE is set to “1”. 18/16/9/8 mode is selected as setting SUB_IM register. Refer to 15h index description.
This figure shows 80 mode 18 bit Video data transfer.
1 Video Stream Packet(18-bpp)
MDDI
Data Stream
DB[17:0]
(data output to sub LDI)
Header
C
R
C
C
R
C
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(01ABCh)
(100FFh)
(0FF00h)
(000FFh)
(00001h)
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
01ABCh
100FFh
0FF00h
000FFh
00001h
pixel write
pixel write
pixel write
pixel write
pixel write
00044h
GRAM write enable
(index 22h)
S_CSB
(chip select for sub LDI)
S_RS
(command / data select)
S_WRB
(write enable for sub LDI)
GRAM Write Enable (22h
index)
Figure87: 80 mode 18 bit video data transfer
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Preliminary
This fugure shows 68 mode 18 bit. In 68 mode, S_WRB must be connected to E_RDB of sub panel module. RW_WRB of
sub panel module must be tied to VSS. Because S6E63D6 only writes data to sub panel module.
Figure88: 68 mode 18 bit video data transfer
This figure shows 80-mode 16 bit Video data transfer.
1 Video Stream Packet(16-bpp)
MDDI
Data Stream
DB[17:10],[8:1]
(data output to sub LDI)
Header
C
R
C
C
R
C
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(1ABCh)
(00FFh)
(FF00h)
(01FFh)
(0001h)
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
1ABCh
00FFh
FF00h
01FFh
0001h
00022h
GRAM write enable
(index 22h)
S_CSB
(chip select for sub LDI)
S_RS
(command / data select)
S_WRB
(write enable for sub LDI)
GRAM Write Enable (22h
index)
pixel write
pixel write
pixel write
pixel write
pixel write
Figure89: 80 mode 16 bit video data transfer
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Preliminary
This figure shows 80-mode 9 bit Video data transfer.
1 Video Stream Packet(18-bpp)
MDDI
Data Stream
Header
DB[17:9]
C
R
C
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(01ABCh)
(100FFh)
(0FF00h)
(000FFh)
(00001h)
044h
(data output to sub LDI)
044h
GRAM write enable
C
R
C
00Dh
0BCh
080h
0FFh
07Fh
100h
000h
0FFh
000h
001h
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
S_CSB
(chip select for sub LDI)
S_RS
(command / data select)
S_WRB
(write enable for sub LDI)
GRAM Write Enable (22h
index)
pixel write
pixel write
pixel write
pixel write
pixel write
Figure90: 80 mode 9 bit video data transfer
This figure shows 80-mode 8 bit Video data transfer.
1 Video Stream Packet(16-bpp)
MDDI
Data Stream
DB[17:10]
(data output to sub LDI)
Header
C
R
C
22h
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(1ABCh)
(00FFh)
(FF00h)
(01FFh)
(0001h)
22h
GRAM write enable
C
R
C
1Ah
BCh
00h
FFh
FFh
00h
01h
FFh
00h
01h
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
S_CSB
(chip select for sub LDI)
S_RS
(command / data select)
S_WRB
(write enable for sub LDI)
GRAM Write Enable
(22h index)
pixel write
pixel write
pixel write
Figure91: 80 mode 8 bit video data transfer
122
pixel write
pixel write
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
2. STN type sub panel timing
2.1 Register data transfer timing
This figure shows conventional type STN mode register data setting. Conventional type does not include parameter.
Instruction type is only 8bit. To use STN type, STN_EN is set to “1”. In STN type, S6E63D6 controls S_RS pin using
register address[0] in register access packet. Register address[0] is “0”, then S_RS is set to “0”, and register address[0] is
“1”, S_RS is set to “1”. Refer to sub panel control(15h index) section.
1 Register Access Packet
MDDI
Data
Stream
Register
Address
Header
(0000h)
C
R
C
Register
Data
(0055h)
C
R
C
Register
Address
Header
(0000h)
C
R
C
Register
Data
(0001h)
000AAh
(55h index)
S_DB[17:0]
C
R
C
00002h
(0001h parameter)
S_CSB
S_RS
S_WRB
index write
parameter write
Figure92: 80 mode STN type convetional register instruction
This type is used to include parameter. When instruction is transferred, S_RS is zero, and when parameter is transferred,
S_RS is “1”. S_RS is controlled using register address[0] of register access packet.
1 Register Access Packet
MDDI
Data
Stream
Header
Register
Address
(0000h)
S_DB[17:0]
C
R
C
Register
Data
(0055h)
C
R
C
Register
Address
Header
(0001h)
000AAh
(55h index)
C
R
C
Register
Data
C
R
C
(0001h)
00002h
(0001h parameter)
S_CSB
S_RS
S_WRB
index write
parameter write (RS = 1)
Figure93: 80 mode STN type included parameter
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Preliminary
2.2 Video data transfer timing
In STN mode, video data start register (like 22H is TFT mode) does not need generally. But some STN type needs video
data start register. If those type STN DDI is used, user has to set the register index.
This figure shows STN 16 bit mode video data transfer.
1 Video Stream Packet(18-bpp)
MDDI
Data Stream
Header
C
R
C
DB[17:0]
(data output to sub LDI)
C
R
C
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(01ABCh)
(100FFh)
(0FF00h)
(000FFh)
(00001h)
00044h
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(write disabled)
01ABCh
100FFh
0FF00h
000FFh
00001h
pixel write
pixel write
pixel write
pixel write
pixel write
S_CSB
(chip select for sub LDI)
S_RS
(command / data select)
S_WRB
(write enable for sub LDI)
Figure94: 80 mode STN type 16 bit video data transfer
This figure shows STN 8bit mode video data transfer. If STN video data is 16bit mode, data transfer is executed during 2
times. Fist transfer is MSB 8bits, and second is LSB 8bits.
1 Video Stream Packet(16-bpp)
MDDI
Data Stream
DB[17:10]
(data output to sub LDI)
Header
C
R
C
22h
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
(1ABCh)
(00FFh)
(FF00h)
(01FFh)
(0001h)
22h
22h write disabled
C
R
C
1Ah
BCh
00h
FFh
FFh
00h
01h
FFh
00h
01h
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Pixel data #1
Pixel data #2
Pixel data #3
Pixel data #4
Pixel data #5
S_CSB
(chip select for sub LDI)
S_RS
(command / data select)
S_WRB
(write enable for sub LDI)
pixel write
pixel write
pixel write
Figure95: 80 mode STN type video data transfer
124
pixel write
pixel write
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SUB PANEL CONTROL TIMING
1. Index/parameter write for sub panel LDI
2. Image data write for sub panel LDI
3. Change data path from sub panel to main panel
mddi_rxbyte_ena
data3
pixel_data(internal)
data4
data5
data6
data7
data8
data9
S_CSB
S_RS
S_WRB
DB
data1
data2
data3
data4
data5
data6
data7
data8
data9
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Preliminary
AMOLED PANEL CONTROL INTERFACE
S6E63D6 outputs some timing signals (FLM, SFTCLK, SFTCLKB, SCLK1, SCLK2, CLA, CLB, CLC, BICTL_L,
BICTL_R, EX_FLM, EX_CLK, EX_CLKB, ESR) for controlling an AMOLED panel with built-in gates. S6E63D6 has
built-in level shifter for AMOLED panel. Output voltage level for high is VGH voltage, for low is VGL voltage.
Figure96: An Exemplary Combination
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Preliminary
PANEL INTERFACE TIMING
Figure97: Timing Diagram of Panel Interface Signals (GTCON=00)
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Preliminary
In Internal Clock Operation mode, the panel interface signals are generated based on internally generated oscillator
clock. But in External Clock Operation mode, those are generated based on RGB I/F Signals. The Figure below
shows the relation between them for External Clock Operation mode.
Figure98: VSYNC and Panel Interface Signals in External Clock Operation mode
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Preliminary
R, G, B INDEPENDENT GAMMA ADJUSTMENT FUNCTION
S6E63D6 provides the gamma adjustment function to display 262,144 colors simultaneously.
The gamma adjustment is executed by the amplitude adjusting registers and curve adjusting registers.
Since, those control registers incorporate independent adjustment of the gamma function for R, G, B independently,
it is highly possible that user determine the best appropriate configuration according to the trait of the display panel.
Figure99: Grayscale Control
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Preliminary
STRUCTURE of GRAYSCALER
Grayscale level can be determined by registers that adjust both amplitude and curve. Also, the period of each level
is split by the internal ladder resistor and generates level between V0 to V63.
Amplitude adjusting part determines upper (V0) and lower (V63) bound voltage and curve adjusting part determines
each 4 point (V4, V10, V21, V42) voltages independently for flexible curve control.
Figure100: Structure of gray scaler
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Preliminary
R, G, B INDEPENDENT GAMMA ADJUSTMENT REGISTERS
Gray Scale Voltage
Gray Scale Voltage
Grqy Scale Voltage
These are registers to set up the grayscale voltage in accordance with the gamma specification of the AMOLED
panel. The registers can set up both amplitude and curve character of grayscale voltage respectively with
corresponding bits as the function of grayscale number. Each configuration can be made for R, G, B independently.
There shows the operation of each register below.
V0
Gray Scale Data
V63
V0
a) Top level control
(4bit : 16step)
Gray Scale Data
b) Bottom level control
(7bit : 128step)
V63
VREG1OUT
Gray Scale Data
V63
Flexible curve by 4 point control
(6bits: 64step)
Amplitude adjustment
Curve adjustment
Figure101: The Operation of Adjusting Register
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Preliminary
AMPLITUDE ADJUSTING REGISTERS
These are the registers for adjusting the amplitude of grayscale voltage. The registers for adjusting amplitude
consists of two parts, one of which is for top level voltage (V0) and the other of which is for bottom level voltage (V63).
CR0[3:0], CG0[3:0] and CB0[3:0] registers control the top level voltage. CR5[6:0], CG5[6:0] and CB5[6:0] registers
control the bottom level voltage. V0 and V63 are selected in divided voltage from ladder resistor strings between
VGS and VREG1OUT. Separate registers are prepared for R, G, B respectively.
Register
R40H ~ R41H
for R
Table52: Amplitude adjusting register
Content of configuration
for G
for B
CR0[3:0]
CG0[3:0]
CB0[3:0]
Grayscale voltage adjusting for top level voltage
CR5[6:0]
CG5[6:0]
CB5[6:0]
Grayscale voltage adjusting for bottom level voltage
Table53: Relationship between amplitude adjusting register and V0
Register value
Formula
CR0[3:0], CG0[3:], CB0[3:0]
0000
VREG1OUT – VREG1OUT x ( 0 /105)
132
0001
VREG1OUT – VREG1OUT x ( 1 / 105)
0010
0011
VREG1OUT – VREG1OUT x ( 2 / 105)
VREG1OUT – VREG1OUT x ( 3 / 105)
0100
VREG1OUT – VREG1OUT x ( 4 / 105)
0101
VREG1OUT – VREG1OUT x ( 5 / 105)
0110
VREG1OUT – VREG1OUT x ( 6 / 105)
0111
1000
VREG1OUT – VREG1OUT x ( 7 / 105)
VREG1OUT – VREG1OUT x ( 8 / 105)
1001
VREG1OUT – VREG1OUT x ( 9 / 105)
1010
VREG1OUT – VREG1OUT x ( 10 / 105)
1011
VREG1OUT – VREG1OUT x ( 11 / 105)
1100
VREG1OUT – VREG1OUT x ( 12 / 105)
1101
1110
VREG1OUT – VREG1OUT x ( 13 / 105)
VREG1OUT – VREG1OUT x ( 14 / 105)
1111
VREG1OUT – VREG1OUT x ( 15 / 105)
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table54: Relation between amplitude adjusting register and V63
Register value
Formula
CR5[6:0] CG5[[6:0], CB5[6:0]
0000000
VREG1OUT – VREG1OUT x ( 35 / 210)
0000001
VREG1OUT – VREG1OUT x ( 36 / 210)
0000010
VREG1OUT – VREG1OUT x ( 37 / 210)
0000011
VREG1OUT – VREG1OUT x ( 38 / 210)
0000100
VREG1OUT – VREG1OUT x ( 39 / 210)
0000101
VREG1OUT – VREG1OUT x ( 40 / 210)
0000110
VREG1OUT – VREG1OUT x ( 41 / 210)
0000111
VREG1OUT – VREG1OUT x ( 42 / 210)
0001000
VREG1OUT – VREG1OUT x ( 43 / 210)
.
.
.
.
.
.
1110000
VREG1OUT – VREG1OUT x (147 / 210)
1110001
VREG1OUT – VREG1OUT x (148 / 210)
1110010
VREG1OUT – VREG1OUT x (149 / 210)
1110011
VREG1OUT – VREG1OUT x (150 / 210)
1110100
VREG1OUT – VREG1OUT x (151 / 210)
1110101
VREG1OUT – VREG1OUT x (152 / 210)
1110110
VREG1OUT – VREG1OUT x (153 / 210)
1110111
VREG1OUT – VREG1OUT x (154 / 210)
1111000
VREG1OUT – VREG1OUT x (155 / 210)
1111001
VREG1OUT – VREG1OUT x (156 / 210)
1111010
VREG1OUT – VREG1OUT x (157 / 210)
1111011
VREG1OUT – VREG1OUT x (158 / 210)
1111100
VREG1OUT – VREG1OUT x (159 / 210)
1111101
VREG1OUT – VREG1OUT x (160 / 210)
1111110
VREG1OUT – VREG1OUT x (161 / 210)
1111111
VREG1OUT – VREG1OUT x (162 / 210)
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Preliminary
CURVE ADJUSTING REGISTERS
The curve adjusting registers are used for adjusting the characteristic curve of the grayscale voltage as the function
of grayscale number. The registers also control R, G, B independently like the amplitude adjusting register. To
accomplish the adjustment, these registers control the each 4 reference voltage by three 47 to 1 selector and a 64
to 1 selector. The 47 or 64 leveled reference voltage generated from the ladder resistor strings between V0 and
V63. The registers for adjusting curve consist of 4 reference point – V4, V10, V21 and V42.
Register
R43H ~ R46H
For R
Table55: Gamma Curve Adjusting Register
Content of configuration
for G
for B
CR1[5:0]
CG1[5:0]
CB1[5:0]
Grayscale voltage adjusting for V4
CR2[5:0]
CG2[5:0]
CB2[5:0]
Grayscale voltage adjusting for V10
CR3[5:0]
CG3[5:0]
CB3[5:0]
Grayscale voltage adjusting for V21
CR4[5:0]
CG4[5:0]
CB4[5:0]
Grayscale voltage adjusting for V42
CR2[5:0], CG2[5:0], CB2[5:0] Regis ter Control for
V 10
Grayscale voltage
Grayscale voltage
CR1[5:0], CG1[5:0], CB1[5:0] Regis ter Control for V 4
Gray s cale data
Gray s cale data
CR4[5:0], CG4[5:0], CB4[5:0] Regis ter Control for
V 42
Grayscale voltage
Grayscale voltage
CR3[5:0], CG3[5:0], CB3[5:0] Regis ter Control for
V 21
Gray s cale data
Figure102: Gamma curve adjustment
134
Gray s cale data
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
CURVE ADJUSTING BLOCK
Below appears the table indicating the relation between the value of these registers and voltage-dividing ratio.
Table56: Relationship between value of curve adjusting register and voltage-dividing ratio
Register value
CR1[5:0]
CG1[5:0]
CB1[5:0]
000000
000001
000010
000011
000100
.
.
.
111011
Voltage dividing resistor value
Register value
Voltage dividing resistor value
V0 - (V0 – V10) x 98/210
V0 - (V0 – V10) x 99/210
V0 - (V0 – V10) x 100/210
V0 - (V0 – V10) x 101/210
V0 - (V0 – V10) x 102/210
.
.
.
V0 - (V0 – V10) x 157/210
CR2[5:0]
CG2[5:0]
CB2[5:0]
000000
000001
000010
000011
000100
.
.
.
101010
V0 - (V0 – V21) x 193/300
V0 - (V0 – V21) x 194/300
V0 - (V0 – V21) x 195/300
V0 - (V0 – V21) x 196/300
V0 - (V0 – V21) x 197/300
.
.
.
V0 - (V0 – V21) x 235/300
111100
V0 - (V0 – V10) x 158/210
101011
V0 - (V0 – V21) x 236/300
111101
V0 - (V0 – V10) x 159/210
101100
V0 - (V0 – V21) x 237/300
111110
V0 - (V0 – V21) x 160/210
V0 - (V0 – V21) x 238/300
111111
V0 - (V0 – V21) x 161/210
V4 formula
V10 formula
CR3[5:0]
CG3[5:0]
CB3[5:0]
000000
V0 - (V0 – V42) x 85/150
101101
101110
~ 111111
CR4[5:0]
CG4[5:0]
CB4[5:0]
000000
000001
V0 - (V0 – V42) x 86/150
000001
V0 - (V0 – V63) x 96/150
000010
V0 - (V0 – V42) x 87/150
000010
V0 - (V0 – V63) x 97/150
000011
V0 - (V0 – V42) x 88/150
000011
V0 - (V0 – V63) x 98/150
000100
.
.
.
101010
V0 - (V0 – V42) x 89/150
.
.
.
V0 - (V0 – V42) x 127/150
000100
.
.
.
101010
V0 - (V0 – V63) x 99/150
.
.
.
V0 - (V0 – V63) x 137/150
101011
V0 - (V0 – V42) x 128/150
101011
V0 - (V0 – V63) x 138/150
101100
V0 - (V0 – V42) x 129/150
101100
V0 - (V0 – V63) x 139/150
101101
V0 - (V0 – V42) x 130/150
101101
V0 - (V0 – V63) x 140/150
101110
~ 111111
V0 - (V0 – V42) x 131/150
101110
~ 111111
V0 - (V0 – V63) x 141/150
V21 formula
V0 - (V0 – V21) x 239/300
V42 formula
V0 - (V0 – V63) x 95/150
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
64 GRAY SCALE OUTPUT VOLTAGE
Below appears the table indicating the relation between the GRAM data value and output voltage value.
Gray date
136
Table57: Grayscale Output Voltage Formula
Output value
Gray data
Output value
0
V0
32
V42 + ( V21 – V42 ) x 10/21
1
V4 + ( V0 – V4 ) x 28/48
33
V42 + ( V21 – V42 ) x 9/21
2
V4 + ( V0 – V4 ) x 12/48
34
V42 + ( V21 – V42 ) x 8/21
3
V4 + ( V0 – V4 ) x 6/48
35
V42 + ( V21 – V42 ) x 7/21
4
V4
36
V42 + ( V21 – V42 ) x 6/21
5
V10 + ( V4 – V10 ) x 20/25
37
V42 + ( V21 – V42 ) x 5/21
6
V10 + ( V4 – V10 ) x 15/25
38
V42 + ( V21 – V42 ) x 4/21
7
V10 + ( V4 – V10 ) x 10/25
39
V42 + ( V21 – V42 ) x 3/21
8
V10 + ( V4 – V10 ) x 7/25
40
V42 + ( V21 – V42 ) x 2/21
9
V10 + ( V4 – V10 ) x 3/25
41
V42 + ( V21 – V42 ) x 1/21
10
V10
42
V42
11
V21 + ( V10 – V21 ) x 21/24
43
V63 + ( V42 – V63) x 20/21
12
V21 + ( V10 – V21 ) x 19/24
44
V63 + ( V42 – V63) x 19/21
13
V21 + ( V10 – V21 ) x 17/24
45
V63 + ( V42 – V63) x 18/21
14
V21 + ( V10 – V21 ) x 14/24
46
V63 + ( V42 – V63) x 17/21
15
V21 + ( V10 – V21 ) x 12/24
47
V63 + ( V42 – V63) x 16/21
16
V21 + ( V10 – V21 ) x 10/24
48
V63 + ( V42 – V63) x 15/21
17
V21 + ( V10 – V21 ) x 8/24
49
V63 + ( V42 – V63) x 14/21
18
V21 + ( V10 – V21 ) x 6/24
50
V63 + ( V42 – V63) x 13/21
19
V21 + ( V10 – V21 ) x 4/24
51
V63 + ( V42 – V63) x 12/21
20
V21 + ( V10 – V21 ) x 2/24
52
V63 + ( V42 – V63) x 11/21
21
V21
53
V63 + ( V42 – V63) x 10/21
22
V42 + ( V21 – V42 ) x 20/21
54
V63 + ( V42 – V63) x 9/21
23
V42 + ( V21 – V42 ) x 19/21
55
V63 + ( V42 – V63) x 8/21
24
V42 + ( V21 – V42 ) x 18/21
56
V63 + ( V42 – V63) x 7/21
25
V42 + ( V21 – V42 ) x 17/21
57
V63 + ( V42 – V63) x 6/21
26
V42 + ( V21 – V42 ) x 16/21
58
V63 + ( V42 – V63) x 5/21
27
V42 + ( V21 – V42 ) x 15/21
59
V63 + ( V42 – V63) x 4/21
28
V42 + ( V21 – V42 ) x 14/21
60
V63 + ( V42 – V63) x 3/21
29
V42 + ( V21 – V42 ) x 13/21
61
V63 + ( V42 – V63) x 2/21
30
V42 + ( V21 – V42 ) x 12/21
62
V63 + ( V42 – V63) x 1/21
31
V42 + ( V21 – V42 ) x 11/21
63
V63
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
OUTPUT LEVEL AS THE FUNCTION OF GRAM DATA
Output level could be described as the function of GRAM DATA like below.
REV = 1
Output Level
V0
000000
RAM data
(Independently controlable characteristics to RGB)
111111
REV = 0
V63
Figure103: Relationship between RAM Data and Output Voltage
137
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
GRAM data
Grayscale
RGB
REV=0 REV=1
Table58: GRAM Data and Grayscale Level
GRAM data Grayscale
GRAM data Grayscale
RGB
REV=0 REV=1
RGB
REV=0 REV=1
GRAM data
Grayscale
RGB
REV=0 REV=1
000000
V0
V63
010000
V16
V47
100000
V32
V31
110000
V48
V15
000001
V1
V62
010001
V17
V46
100001
V33
V30
110001
V49
V14
000010
V2
V61
010010
V18
V45
100010
V34
V29
110010
V50
V13
000011
V3
V60
010011
V19
V44
100011
V35
V28
110011
V51
V12
000100
V4
V59
010100
V20
V43
100100
V36
V27
110100
V52
V11
000101
V5
V58
010101
V21
V42
100101
V37
V26
110101
V53
V10
000110
V6
V57
010110
V22
V41
100110
V38
V25
110110
V54
V9
000111
V7
V56
010111
V23
V40
100111
V39
V24
110111
V55
V8
001000
V8
V55
011000
V24
V39
101000
V40
V23
111000
V56
V7
001001
V9
V54
011001
V25
V38
101001
V41
V22
111001
V57
V6
001010
V10
V53
011010
V26
V37
101010
V42
V21
111010
V58
V5
001011
V11
V52
011011
V27
V36
101011
V43
V20
111011
V59
V4
001100
V12
V51
011100
V28
V35
101100
V44
V19
111100
V60
V3
001101
V13
V50
011101
V29
V34
101101
V45
V18
111101
V61
V2
001110
V14
V49
011110
V30
V33
101110
V46
V17
111110
V62
V1
001111
V15
V48
011111
V31
V32
101111
V47
V16
111111
V63
V0
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
THE 8-COLOR DISPLAY MODE
The S6E63D6 incorporates 8-color display mode. The voltage levels to be used are VREG1OUT and V63 and all the
other grayscale levels V0~V62are halt. So that it attempts to lower power consumption.
During the 8-color mode, the Gamma micro adjustment register, C1R~C4R, C1G~C4G and C1B~C4B are invalid.
The level power supply (V0-V62) is in OFF condition during the 8-color mode in order to select VREG1OUT/V63.
Figure104: 8-color display control
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SET UP FLOW OF STANDBY
Figure105: Setup flow of STNADBY
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
OSCILLATION CIRCUIT
The S6E63D6 can provide R-C oscillation. S6E63D6 internal oscillator does not need to attach the external resistor.
The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by
adjusting the oscillator frequency control register setting. Since R-C oscillation stops during the standby mode,
power consumption can be reduced.
FRAME FREQUENCY CALCULATION
The relation between the AMOLED driver duty and the frame frequency can be found by the following expression.
Figure106: Formula for the Frame Frequency
EXAMPLE CALCULATION
Parameters
Line Number
Frame Frequency
BP
FP
fosc
„
Description
320
60
8
8
1,290,240 Hz
Display Clock Frequency
Table59: DISPLAY CLOCK FREQUENCY
1 HCLK
1 Horizontal Period
Internal Clock Operation
Fosc / 2
32 HCLKs
External Clock Operation
Fdotclk / 8(RIM=00,01)
Fdotclk/24(RIM = 10)
32 HCLKs
141
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
APPLICATION CIRCUIT
The following figure indicates a typical application circuit for S6E63D6.
Figure107: S6E63D6 Application (80 System CPU Parallel Interface)
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table60: Absolute Maximum Rating
(VSS = 0V)
Item
Symbol
Rating
Unit
Supply voltage
VDD3
-0.3 ~ 5.0
V
Supply voltage for step-up circuit
VCI
-0.3 ~ 5.0
V
Supply Voltage range
|VLIN2 – VLIN3|
20
V
Input Voltage range
Vin
-0.3 to VDD + 0.5
V
Notes:
1. Absolute maximum rating is the limit value. When the IC is exposed operating environment beyond this range, the IC do not
assure operations and may be damaged permanently, not be able to be recovered.
2. Absolute maximum rating is guaranteed only when our company’s package used.
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
DC CHARACTERISTICS
Table61: DC Characteristics
(VSS = 0V)
Characteristic
Symbol
VGH
Driving voltage
VGL
VINT
CONDITION
MIN
-
TYP
MAX
Unit
4.6
-
6.6
V
-7.8
-
-5.0
V
-4.0
-
-1.0
V
Note
Photo Sensor Power
VSP
-
2.9
3.0
3.1
V
Logic Operating Voltage
RVDD
-
1.45
1.5
1.55
V
Operating frequency
fosc
Frame frequency = 60Hz
Display line = 320 line
1192.3
1324.8
1457.2
kHz
1st step-up input voltage
VCI1
-
2.1
-
2.75
V
1st step-up output voltage
VLOUT1
Without load
+4.2
-
+5.5
V
1st step-up output
efficiency
VLOUT1
I_VLOUT1_LOAD = 2.3mA
90
95
-
%
2nd step-up output voltage
VLOUT2
Without load
+6.3
-
+11.0
V
2nd step-up output
efficiency
VLOUT2
I_VLOUT2_LOAD = 0.1mA
90
93
-
%
3rd step-up output voltage
VLOUT3
Without load
-11.0
-
-6.3
V
3 step-up output
efficiency
VLOUT3
I_VLOUT3_LOAD = 0.1mA
90
93
-
%
Source Output voltage
deviation
(channel to channel)
-
-
-
±TBD
-
mV
Output voltage deviation
(Chip to Chip)
-
-
-
±TBD
-
mV
Source driver output
voltage range
Vso
-
0.96
-
4.2
V
LTPS driver output voltage
deviation
-
-
-
-
TBD
V
Driving voltage
dVGH
voltage deviation
-
-
TBD
V
-
-
TBD
V
-
-
TBD
uA
-
-
-
TBD
mA
-
rd
dVGL
Current consumption
during normal operation
144
IVDD3
IVCI
No load,
Ta = 25 °C
VCI=2.8V
Frame(f)=60Hz
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Characteristic
Symbol
CONDITION
MIN
TYP
MAX
Unit
Power Supply Voltage
VCI
Operating Voltage
2.5
2.8
3.3
V
Power Supply Voltage
VDD3
I/O supply Voltage
1.65
1.8
3.3
V
Logic High level input
voltage
VIH
0.7*VDD3
VDD3
V
Logic Low level input
voltage
VIL
0.0
0.3*VDD3
V
Logic High level output
voltage
VOH
IOUT = -1mA
0.8*VDD3
VDD3
V
Logic Low level output
voltage
VOL
IOUT = +1mA
0.0
0.2*VDD3
V
Analog High level output
voltage
EL_ONOH
8uA
1.6
Analog Low level output
voltage
EL_ONOL
8uA
0
Note
V
0.4
V
(VDD3 = 1.65~3.3V, VCI = 2.5~3.3V, Ta = 25℃)
Characteristic
VREG1OUT
Symbol
CONDITION
MIN
TYP
MAX
Unit
.
4.185
4.2
4.215
V
Note
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
PANEL INTERFACE
GATE IC LESS LEVEL SHIFTER OUTPUT CHARACTERISTICS
Figure108: AC Characteristics of Level Shifter Output
Figure109: LTPS Signal Load Test Point
146
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table62: AC Parameters of Level Shifter Outputs
Total Load
Level Shifter Output
R(ohm)
C(pF)
High
Level
Low
Level
BICTL
1320
78
VGH
VGL
CLA,
CLB,
CLC
3500
39
VGH
VGL
FLM
900
42
VGH
VGL
SFTCLK,
SFTCLKB
895
61
VGH
VGL
SCLK1,
SCLK2
895
61
VGH
VGL
EX_FLM
910
42
VGH
VGL
EX_CLK,
EX_CLKB
910
68
VGH
VGL
ESR
1320
60
VGH
VGL
Item
Symbol
Min
Typ
Max
Unit
Rising Time
tr
-
-
2000
ns
Falling Time
Rising Time
tf
tr
-
-
2000
500
ns
ns
Falling Time
tf
-
-
500
ns
Rising Time
Falling Time
Rising Time
Falling Time
Cross Point
Rising Time
Falling Time
Rising Time
Falling Time
Rising Time
Falling Time
Cross Point
Rising Time
Falling Time
tr
tf
tr
tf
rCross
tr
tf
tr
tf
tr
tf
rCross
tr
tf
40
40
-
50
50
-
1000
1000
300
300
60
300
300
1000
1000
350
350
60
2000
2000
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
%
ns
ns
SOURCE OUTPUT
tDD
Certain Grayscale Voltage
mV
S1 ~ S240
Certain Grayscale Voltage
mV
Figure110: AC Characteristics of Source Driver Output
Symbol
tDD
Table63: AC Parameters of Source Driver Output
Test Condition
Value
VCI1 = 2.75 V
Fosc = 1324.8 kHz
9 usec / 4V max.
Grayscale to be reached = ±10mV
(with demux)
Load Resistance R = 32 Kohm
Load Capacitance C = 20pF
SAP[2:0]=101
147
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
VINT Source
- Functions and conditions of VINT output
- During 1H(=51.2us, 1 horizontal line) time, turn on Tr to reset Cst for about 10us
- Peak current = 3.15mA
- VINT ripple(at saturation position) < 100mV
- VINT Saturation time < 7us
Figure111: Current Wave of VINT
148
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
AC CHARACTERISTICS
Table64: Parallel Write Interface Characteristics (68 Mode)
(VDD = 1.5V, VDD3 = 1.65 to 3.3V, TA = -40 to +85oC)
Specification
Characteristic
Symbol
Unit
Min.
Max.
tCYCW68
tCYCR68
TBD
TBD
-
tR, tF
-
TBD
tWHW68
tWHR68
tWLW68
tWLR68
tAS68
TBD
TBD
TBD
TBD
TBD
-
tAH68
TBD
-
CSB to E time
tCW68
TBD
-
Write data setup time
tWDS68
TBD
-
Write data hold time
tWDH68
TBD
-
Read data delay time
tRDD68
-
TBD
Read data hold time
tRDH68
TBD
TBD
Cycle time
Write
Read
Pulse rise / fall time
Write
Read
Write
Pulse width high
Read
RS,RW to CSB, E setup time
Pulse width low
RS,RW to CSB, E hold time
ns
Figure112: AC Characteristics (68 Mode)
149
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table65: Parallel Write Interface Characteristics (80 Mode)
(VDD = 1.5V, VDD3 = 1.65 to 3.3V, TA = -40 to +85oC)
Specification
Characteristic
Symbol
Unit
Min.
Max.
tCYCW80
tCYCR80
TBD
TBD
-
tR, tF
-
TBD
tWLW80
tWLR80
tWHW80
tWHR80
TBD
TBD
TBD
TBD
-
RS to CSB, WRB(RDB) setup time
tAS80
TBD
-
RS to CSB, WRB(RDB) hold time
tAH80
TBD
-
CSB to WRB(RDB) time
tcw80
TBD
-
Write data setup time
tWDS80
TBD
-
Write data hold time
tWDH80
TBD
-
Write
Read
Cycle time
Pulse rise / fall time
Write
Read
Write
Read
Pulse width low
Pulse width high
Read data delay time
tRDD80
-
TBD
Read data hold time
tRDH80
TBD
TBD
Figure113: AC Characteristics (80 Mode)
150
ns
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table66: Clock Synchronized Serial Write Mode Characteristics
(VDD = 1.5V, VDD3 = 1.65 to 3.3V, TA = -40 to +85oC)
specification
Characteristic
Symbol
Unit
Min.
Max.
Serial clock write cycle time
tscyc
TBD
-
ns
Serial clock read cycle time
tscyc
TBD
-
ns
Serial clock rise / fall time
tR, tF
-
TBD
ns
Pulse width high for write
tSCHW
TBD
-
ns
Pulse width high for read
tSCHR
TBD
-
ns
Pulse width low for write
tSCLW
TBD
-
ns
Pulse width low for read
tSCLR
TBD
-
ns
Chip Select setup time
tCSS
TBD
-
ns
Chip Select hold time
tCSH
TBD
-
ns
Serial input data setup time
tSIDS
TBD
-
ns
Serial input data hold time
tSIDH
TBD
-
ns
Serial output data delay time
tSODD
-
TBD
ns
Serial output data hold time
tSODH
TBD
-
ns
Transfer Start
Transfer End
VIH
CSB
VIL
tscyc
tSCHW /
tSCHR
tR
tCSS
VIH
VIH
tF
tSCLW /
tSCLR
VIH
tCSH
VIH
SCL
VIL
VIL
VIL
tSIDS
tSIDH
VIH
SDI
VIH
INPUT DATA
VIL
VIL
VIL
INPUT
DATA
tSODH
tSODD
VOH1
SDO
OUTPUT DATA
VOL1
OUTPUT
DATA
VOH1
VOL1
Figure114: AC Characteristics (SPI Mode)
151
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
Table67: RGB Data Interface Characteristics
(VDD = 1.5V, VDD3 = 1.65 to 3.3V, TA = -40 to +85oC)
18/16bit RGB interface
Characteristic
6bit RGB interface
Min.
Max.
Min.
Max.
DOTCLK cycle time
tDCYC
TBD
-
TBD
-
DOTCLK rise / fall time
tR, tF
-
TBD
-
TBD
DOTCLK Pulse width high
tDCHW
TBD
-
TBD
-
DOTCLK Pulse width low
tDCLW
TBD
-
TBD
-
Vertical Sync Setup Time
tvsys
TBD
-
TBD
-
Vertical Sync Hold Time
tvsyh
TBD
-
TBD
-
Horizontal Sync Setup Time
thsys
TBD
TBD
Horizontal Sync Hold Time
thsyh
TBD
TBD
ENABLE setup time
tENS
TBD
-
TBD
-
ENABLE hold time
tENH
TBD
-
TBD
-
PD data setup time
tPDS
TBD
-
TBD
-
PD data hold time
tPDH
TBD
-
TBD
-
tHE
TBD
HBP
TBD
HBP
thv
TBD
TBD
TBD
TBD
HSYNC-ENABLE Time
VSYNC-HSYNC Time
Unit
Symbol
ns
tDCYC
Note : HBP is Horizontal Back-porch.
(When VSPL=0, HSPL=0, DPL=0, EPL=1)
Figure115: AC Characteristics (RGB Interface Mode)
152
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
RESET TIMING
tRES
RESETB
VIL
VIL
Note : Reset low pulse width shorter than 10us do not make reset. It means undesired short pulse such as glitch,
bouncing noise or electrostatic discharge do not cause irregular system reset. Please refer to the table
below.
Figure116: AC characteristics (RESET timing)
Parameter
tRES
Description
Min
Max
Unit
10
-
us
Reset low pulse width
Table68: Reset Operation regarding tRES Pulse Width
tRES Pulse
Action
Shorter than 5 us
No reset
Longer than 10 us
Reset
Between 5 us and 10 us
Not determined
1. User may or may not use RESETB pin. In order to use it, user should satisfy the conditions described in the above
tables. But when not wants to use RESETB, user may fix this pin to VDD3 level because internally generated POR
(Power-On-Reset) is used.
2. Spike Rejection also applies during a valid reset pulse as shown below:
10us
Reset is accepted
20ns
Less than 20ns width positive spike will be rejected.
153
S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
EXTERNAL POWER ON / OFF SEQUENCE
VDD3 must be applied earlier than VCI or at least applied simultaneously with VCI. When regulator cap is 1μF,
RESETB must be applied after VCI have been applied. The applied time gap between VCI and RESETB is
minimum 1ms. As regulator cap becomes larger, this time gap must be increased. Otherwise function is not
guaranteed.
Figure117: External power on sequence
b) EXTERNAL POWER OFF SEQUENCE
VDD3 must be powered down later than VCI or at least powered down simultaneously with VCI. VCI must be
powered down after RESETB have been powered down. The time gap of powered down between RESETB and
VCI is minimum 1ms. Otherwise function is not guaranteed.
Figure118: External Power Off sequence
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S6E63D6 PRELIMINARY VER. 0.0
240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED
Preliminary
NOTICE
Precautions for Light
Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change
the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages
which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to
block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip.
Follow the precautions below when using the products.
1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design
stage.
2. Always test and inspect products under the environment with no penetration of light.
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