SN74LS377 Octal D Flip-Flop with Enable The SN74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. • • • • • http://onsemi.com 8-Bit High Speed Parallel Registers Positive Edge-Triggered D-Type Flip Flops Fully Buffered Common Clock and Enable Inputs True and Complement Outputs Input Clamp Diodes Limit High Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current – High – 0.4 mA IOL Output Current – Low 8.0 mA 20 1 PLASTIC N SUFFIX CASE 738 20 1 SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device SN74LS377N SN74LS377DW Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Package Shipping 16 Pin DIP 1440 Units/Box 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS377/D SN74LS377 CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP 20 19 18 17 16 15 14 13 12 11 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 E 2 Q0 3 D0 4 D1 5 Q1 6 Q2 8 D3 7 D2 9 Q3 10 GND LOADING (Note a) PIN NAMES E D0 – D3 CP Q0 – Q3 Q0 – Q3 Enable (Active LOW) Input Data Inputs Clock (Active HIGH Going Edge) Input True Outputs Complemented Outputs HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. LOGIC DIAGRAM 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 E ENABLE 1 CP CLOCK 11 http://onsemi.com 2 SN74LS377 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Min Typ Max 2.0 0.8 – 0.65 2.7 – 1.5 3.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA – 20 VCC = VCC MIN, VIN = VIL or VIH per Truth Table 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 28 mA VCC = MAX, NOTE 1 NOTE: With all inputs open and GND applied to all data and enable inputs, ICC is measured after a momentary GND, then 4.5 V is applied to clock. Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter fMAX Maximum Clock Frequency tPLH tPHL Propagation Delay, Clock to Output Min Typ 30 40 Max Unit Test Conditions MHz 17 18 27 27 VCC = 5 5.0 0V CL = 15 pF ns AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit tW Any Pulse Width 20 ns ts Data Setup Time 20 ns 10 ns 25 ns 5.0 ns ts Enable Setup Time th Any Hold Time Inactive — State Active — State Test Conditions VCC = 5.0 V DEFINITION OF TERMS logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the http://onsemi.com 3 SN74LS377 TRUTH TABLE E CP Dn Qn Qn H X No Change No Change L H H L L L L H L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial AC WAVEFORM 1/fmax 1.3 V ts(L) ts(H) D OR E tW 1.3 V CP * th(H) th(L) 1.3 V 1.3 V Q tPLH tPHL 1.3 V 1.3 V *The shaded areas indicate when the input is permitted to change for predictable output performance. http://onsemi.com 4 SN74LS377 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE E –A– 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C –T– K SEATING PLANE M N E G F J D 0.25 (0.010) 20 PL 0.25 (0.010) 20 PL M T A M http://onsemi.com 5 M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 SN74LS377 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751D–05 ISSUE F q A 20 X 45 _ h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE DIM A A1 B C D E e H h L q C T http://onsemi.com 6 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ SN74LS377 Notes http://onsemi.com 7 SN74LS377 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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