IDT IDT54FCT299CPB Fast cmos 8-input universal shift register Datasheet


IDT54/74FCT299
IDT54/74FCT299A
IDT54/74FCT299C
FAST CMOS
8-INPUT UNIVERSAL
SHIFT REGISTER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT54/74FCT299 and IDT54/74FCT299A/C are built
using an advanced dual metal CMOS technology. The IDT54/
74FCT299 and IDT54/74FCT299A/C are 8-input universal
shift/storage registers with 3-state outputs. Four modes of
operation are possible: hold (store), shift left, shift right and
load data. The parallel load inputs and flip-flop outputs are
multiplexed to reduce the total number of package pins.
Additional outputs are provided for flip-flops Q0 and Q7 to
allow easy serial cascading. A separate active LOW Master
Reset is used to reset the register.
•
•
•
•
•
•
•
•
•
•
IDT54/74FCT299 equivalent to FAST speed
IDT54/74FCT299A 25% faster than FAST
IDT54/74FCT299C 35% faster than FAST
Equivalent to FAST output drive over full temperature
and voltage supply extremes
IOL = 48mA (commercial) and 32mA (military)
CMOS power levels (1mW typ. static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than FAST
(5µA max.)
8-input universal shift register
JEDEC standard pinout for DIP and LCC
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing# 5962-86862 is listed on this
function. Refer to section 2.
FUNCTIONAL BLOCK DIAGRAM
S1
S0
DS 7
DS 0
CP
CD
D CP
Q
CD
D CP
Q
CD
D CP
Q
CD
D CP
Q
CD
D CP
Q
CD
D CP
Q
CD
D CP
Q
CD
D CP
Q
Q0
Q7
MR
OE 1
OE 2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
2561 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1994 Integrated Device Technology, Inc.
7.11
MAY 1992
DSC-4604/3
1
IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OE 2
OE 1
S0
Vcc
S1
PIN CONFIGURATIONS
INDEX
1
20
2
19
3
4
5
6
P20-1
D20-1
S020-2
&
E20-1
18
17
16
15
7
14
8
13
9
12
10
11
Vcc
S1
DS 7
Q7
I/O 7
I/O 5
I/O 3
I/O 1
CP
DS 0
3 2
I/O 6
I/O 4
I/O 2
I/O 0
Q0
4
1
5
17
L20-2
6
15
8
14
9 10 11 12 13
LCC
TOP VIEW
DS 7
Q7
I/O 7
I/O 5
I/O 3
2561 drw 02
FUNCTION TABLE(1)
PIN DESCRIPTION
CP
16
7
DIP/SOIC/CERPACK
TOP VIEW
Pin Names
20 19
18
MR
GND
DS0
CP
I/O 1
S0
OE 1
OE 2
I/O 6
I/O 4
I/O 2
I/O 0
Q0
MR
GND
Inputs
Description
MR S1
Clock Pulse Input (Active Edge Rising)
S0
CP
Response
X
X
X
Asynchronous Reset Q0–Q7 = LOW
H
H
↑
Parallel Load; I/On → Qn
DS0
Serial Data Input for Right Shift
L
DS7
Serial Data Input for Left Shift
H
S0, S1
Mode Select Inputs
H
L
H
↑
Shift Right; DS0 → Q0, Q0 → Q1, etc.
MR
OE1, OE2
Asynchronous Master Reset Input (Active LOW)
H
H
L
↑
Shift Left; DS7 → Q7, Q7→ Q6, etc.
3-State Output Enable Inputs (Active LOW)
H
L
L
X
Hold
I/O0–I/O7
Parallel Data Inputs or 3-State Parallel Outputs
Q0, Q7
Serial Outputs
2561 tbl 01
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
(2)
Terminal Voltage
VTERM
with Respect
to GND
VTERM(3) Terminal Voltage
with Respect
to GND
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipation
DC Output Current
IOUT
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW-to-HIGH clock transition
2561 tbl 02
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Commercial
Military
Unit
–0.5 to +7.0 –0.5 to +7.0
V
–0.5 to VCC
–0.5 to VCC
V
0 to +70
–55 to +125
°C
–55 to +125
–65 to +135
°C
–55 to +125
–65 to +150
°C
0.5
120
0.5
120
W
mA
Symbol
Parameter(1)
Conditions
Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
6
10
pF
CI/O
I/O Capacitance
VOUT = 0V
8
12
pF
NOTE:
2561 tbl 04
1. This parameter is guaranteed by characterization data and not tested.
NOTES:
2561 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +0.5 unless otherwise noted.
2. Inputs and VCC terminals only.
3. Outputs and I/O terminals only.
7.11
2
IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
Input HIGH Current
VCC = Max.
µA
IIH
IIL
IIH
IIL
Parameter
VI = VCC
—
—
5
(Except I/O Pins)
VI = 2.7V
—
—
5(4)
Input LOW Current
VI = 0.5V
—
—
–5(4)
(Except I/O Pins)
VI = GND
—
—
–5
VI = VCC
—
—
15
(I/O Pins Only)
Input HIGH Current
VCC = Max.
VI = 2.7V
—
—
15(4)
Input LOW Current
VI = 0.5V
—
—
–15(4)
(I/O Pins Only)
VI = GND
—
—
–15
VIK
Clamp Diode Voltage
Vcc = Min., IN = –18mA
IOS
Short Circuit Current
Vcc = Max.(3), VO = GND
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
µA
—
–0.7
–1.2
V
–60
–120
—
mA
Vcc = 3V, VIN = VLC or VHC, IOH = –32µA
VHC
VCC
—
V
Vcc = Min.
IOH = –300µA
VHC
VCC
—
VIN = VIH or VIL
IOH = –12mA MIL.
2.4
4.3
—
IOH = –15mA COM’L.
2.4
4.3
—
Vcc = 3V, VIN = VLC or VHC, IOL = 300µA
—
GND
VLC
Vcc = Min.
—
GND
VLC(4)
IOL = 300µA
VIN = VIH or VIL
IOL = 32mA MIL.
—
0.3
0.5
IOL = 48mA COM’L.
—
0.3
0.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.11
V
2561 tbl 05
3
IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
ICC
Quiescent Power Supply
Current
Vcc = Max.
VIN ≥ VHC; VIN ≤ VLC
—
0.2
1.5
mA
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
—
0.5
2.0
mA
ICCD
Dynamic Power Supply
Current(4)
Vcc = Max.
Outputs Open
OE1 = OE2 = GND
MR = VCC
S0 = S1 = VCC
DS0 = DS1 = GND
One Input Toggling
50% Duty Cycle
VIN ≥ VHC
VIN ≤ VLC
—
0.15
0.25
mA/MHz
IC
Total Power Supply
Current(6)
Vcc = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
OE1 = OE2 = GND
MR = VCC
S0 = S1 = VCC
DS0 = DS7 = GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
1.7
4.0
mA
VIN = 3.4V
VIN = GND
—
2.2
6.0
Vcc = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
OE1 = OE2 = GND
MR = VCC
S0 = S1 = VCC
DS0 = DS7 = GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
4.0
7.8(5)
VIN = 3.4V
VIN = GND
—
6.2
16.8(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7.11
2561 tbl 06
4
IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT299
Com’l.
Symbol
Parameter
Propagation Delay
tPLH
tPHL
CP to Q0 or Q7
IDT54/74FCT299A
Mil.
Com’l.
IDT54/74FCT299C
Mil.
Com’l.
Mil.
Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
CL = 50pF 2.0
10.0 2.0 14.0 2.0
7.2
2.0
9.5
2.0
6.5
2.0
7.5
ns
RL = 500Ω
tPLH
tPHL
Propagation Delay
CP to I/On
2.0
12.0
2.0
12.0
2.0
7.2
2.0
9.5
2.0
6.5
2.0
7.5
ns
tPHL
Propagation Delay
MR to Q0 or Q7
2.0
10.0
2.0
10.5
2.0
7.2
2.0
9.5
2.0
6.5
2.0
7.5
ns
tPHL
Propagation Delay
MR to I/On
2.0
15.0
2.0
15.0
2.0
8.7
2.0
11.5
2.0
6.5
2.0
7.5
ns
tPZH
tPZL
Output Enable Time
OEn to I/On
1.5
11.0
1.5
15.0
1.5
6.5
1.5
7.5
1.5
6.5
1.5
7.5
ns
tPHZ
tPLZ
Output Disable Time
OEn to I/On
1.5
7.0
1.5
9.0
1.5
6.0
1.5
6.5
1.5
6.0
1.5
6.5
ns
tSU
Set-up Time HIGH
or LOW
S0 or S1 to CP
7.5
—
7.5
—
3.5
—
4.0
—
3.5
—
4.0
—
ns
tH
Hold Time HIGH
or LOW
S0 or S1 to CP
1.0
—
1.0
—
1.0
—
1.0
—
1.0
—
1.0
—
ns
tSU
Set-up Time HIGH
or LOW I/On, DS0
or DS7 to CP
5.5
—
5.5
—
4.0
—
4.5
—
4.0
—
4.5
—
ns
tH
Hold Time HIGH
or LOW I/On, DS0
or DS7 to CP
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tW
CP Pulse width
HIGH or LOW
7.0
—
7.0
—
5.0
—
6.0
—
5.0
—
6.0
—
ns
tW
MR Pulse Width
7.0
—
7.0
—
5.0
—
6.0
—
5.0
—
6.0
—
ns
7.0
—
7.0
—
5.0
—
6.0
—
5.0
—
6.0
—
ns
LOW
tREM
Recovery Time
MR to CP
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2561 tbl 07
7.11
5
IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
VCC
7.0V
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
RT
500Ω
SET-UP, HOLD AND RELEASE TIMES
Closed
All Other Tests
Open
3V
1.5V
0V
tH
TIMING
INPUT
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
tW
t REM
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
Open Drain
Disable Low
Enable Low
PULSE WIDTH
DATA
INPUT
ASYNCHRONOUS CONTROL
Switch
DEFINITIONS:
2561 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
CL
t SU
Test
t SU
1.5V
3V
1.5V
0V
tH
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
1.5V
SAME PHASE
INPUT TRANSITION
t PLH
t PHL
CONTROL
INPUT
t PZL
0V
OUTPUT
NORMALLY SWITCH
LOW CLOSED
t PZH
VOH
1.5V
OUTPUT
VOL
t PLH
t PHL
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
1.5V
0V
t PLZ
3.5V
3.5V
1.5V
0.3V
V OL
t PHZ
0.3V
1.5V
0V
V OH
0V
0V
NOTES
2561 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.11
6
IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
Temperature
Range
FCT
X
X
X
Device Type
Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
D
SO
L
E
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
299
299A
299C
8-Input Universal Shift Register
Fast 8-Input Universal Shift Register
Super Fast 8-Input Universal Shift Register
54
74
–55°C to +125°C
0°C to +70°C
2561 drw 03
7.11
7
Similar pages