ON NB7V586MMNR4G 1.8v differential 2:1 mux input to 1.2v/1.8v 1:6 cml clock/data fanout buffer / translator Datasheet

NB7V586M
1.8V Differential 2:1 Mux
Input to 1.2V/1.8V 1:6 CML
Clock/Data Fanout Buffer /
Translator
Multi−Level Inputs w/ Internal Termination
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Description
The NB7V586M is a differential 1−to−6 CML Clock/Data
Distribution chip featuring a 2:1 Clock/Data input multiplexer with an
input select pin. The INx/INx inputs incorporate internal 50 W
termination resistors and will accept differential LVPECL, CML, or
LVDS logic levels (see Figure 12). The INx/INx inputs and core logic
are powered with a 1.8 V supply. The NB7V586M produces six
identical differential CML output copies of Clock or Data. The outputs
are configured as three banks of two differential pair. Each bank (or all
three banks) have the flexibility of being powered by any combination
of either a 1.8 V or 1.2 V supply.
The 16 mA differential CML output structure provides matching
internal 50 W source terminations and 400 mV output swings when
externally terminated with a 50 W resistor to VCCOx (see Figure 11).
The 1:6 fanout design was optimized for low output skew and
minimal jitter and is ideal for SONET, GigE, Fiber Channel,
Backplane and other Clock/Data distribution applications operating
up to 6 GHz or 10 Gb/s typical. The VREFAC reference outputs can be
used to rebias capacitor−coupled differential or single−ended input
signals.
The NB7V586M is offered in a low profile 5x5 mm 32−pin Pb−Free
QFN package. Application notes, models, and support documentation
are available at www.onsemi.com.
The NB7V586M is a member of the GigaComm™ family of high
performance clock products.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Data Rate > 10 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 6 GHz Typical
Random Clock Jitter < 0.8 ps RMS, Max
Low Skew 1:6 CML Outputs, 20 ps Max
2:1 Multi−Level Mux Inputs
175 ps Typical Propagation Delay
50 ps Typical Rise and Fall Times
Differential CML Outputs, 330 mV Peak−to−Peak, Typical
Operating Range: VCC = 1.71 V to 1.89 V
Operating Range: VCCOx = 1.14 V to 1.89 V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
QFN32 Package, 5 mm x 5 mm
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2008
September, 2008 − Rev. 0
1
MARKING
DIAGRAM*
1
QFN32
MN SUFFIX
CASE 488AM
32
1
A
WL
YY
WW
G or G
NB7V
586M
AWLYYWW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
SIMPLIFIED LOGIC DIAGRAM
VCC
Q0
Q0
VCCO1
Q1
Q1
SEL
VREFAC0
IN0
VT0
IN0
0
Q2
Q2
VCCO2
IN1
VT1
1
IN1
VREFAC1
Q3
Q3
Q4
Q4
VCC
GND
VCCO3
Q5
Q5
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Publication Order Number:
NB7V586M/D
32
31
30
Table 1. INPUT SELECT FUNCTION TABLE
29
28
27
26
VCC01
Q1
Q1
Q0
Exposed Pad
(EP)
Q0
VCC
SEL
GND
NB7V586M
25
IN0
1
24
GND
VT0
2
23
VCC02
VREFAC0
3
22
Q2
IN0
4
21
Q2
IN1
5
20
Q3
VT1
6
19
Q3
VREFAC1
7
18
VCC02
IN1
8
17
SEL*
CLK Input Selected
0
IN0
1
IN1
*Defaults HIGH when left open.
14
15
16
VCC03
Q5
13
Q4
12
Q4
11
Q5
10
VCC03
GND
9
NC
NB7V586M
GND
Figure 1. 32−Lead QFN Pinout (Top View)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1,4
5,8
IN0, IN0
IN1, IN1
LVPECL, CML,
LVDS Input
2,6
VT0, VT1
31
SEL
LVTTL/LVCMOS
Input
10
NC
−
No Connect
30
VCC
−
1.8 V Positive Supply Voltage for the Inputs and Core Logic.
25
VCCO1
18, 23
VCCO2
11, 16
VCCO3
29, 28
27, 26
Q0, Q0
Q1, Q1
1.2 V or 1.8 V
CML Output
Non−inverted, Inverted Differential Outputs; powered by VCCO1 (Notes 1 and 2).
22, 21
20, 19
Q2, Q2
Q3, Q3
1.2 V or 1.8 V
CML Output
Non−inverted, Inverted Differential Outputs; powered by VCCO2 (Notes 1 and 2).
15, 14
13, 12
Q4, Q4
Q5, Q5
1.2 V or 1.8 V
CML Output
Non−inverted, Inverted Differential Outputs; powered by VCCO3 (Notes 1 and 2).
9, 17,
24, 32
GND
3
7
VREFAC0
VREFAC1
−
Output Voltage Reference for Capacitor−Coupled Inputs, only
−
EP
−
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board.
Non−inverted, Inverted, Differential Inputs
Internal 100 Ω Center−tapped Termination Pin for IN0/IN0 and IN1/IN1
Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left open
1.2 V or 1.8 V Positive Supply Voltage for the Q0, Q0, Q1, Q1 CML Outputs
−
1.2 V or 1.8 V Positive Supply Voltage for the Q2, Q2, Q3, Q3 CML Outputs
1.2 V or 1.8 V Positive Supply Voltage for the Q4, Q4, Q5, Q5 CML Outputs
Negative Supply Voltage, connected to Ground
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on INn/INn input, then, the device will be susceptible to self−oscillation. Qn/Qn outputs have internal 50 W source
termination resistors.
2. All VCC, VCC0x and GND pins must be externally connected to a power supply for proper operation.
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NB7V586M
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Value
Human Body Model
Machine Model
> 2 kV
> 200 V
Input Pullup Resistor (RPU)
75 kW
Moisture Sensitivity (Note 3)
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
308
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
Positive Power Supply
GND = 0 V
3.0
V
VCCOx
Positive Power Supply
GND = 0 V
3.0
V
VIO
Input/Output Voltage
GND = 0 V
−0.5 to VCC + 0.5
V
VINPP
Differential Input Voltage |INx − INx|
1.89
V
IIN
Input Current Through RT (50 Ω Resistor)
$40
mA
IOUT
Output Current
34
40
mA
IVFREFAC
VREFAC Sink/Source Current
$1.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 4)
0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note 4)
Standard Board
QFN−32
12
°C/W
Tsol
Wave Solder
265
°C
−0.5 v VIO v VCC + 0.5
Continuous
Surge
Pb−Free
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7V586M
Table 5. DC CHARACTERISTICS − CML OUTPUT VCC = 1.8 V $5%, VCCO1 = 1.2 V $5% or 1.8 V $5%, VCCO2 = 1.2 V $5%
or 1.8 V $5%, VCCO3 = 1.2 V $5% or 1.8 V $5%, GND = 0 V, TA = −40°C to 85°C (Note 5)
Characteristic
Symbol
Min
Typ
Max
Unit
75
95
125
105
mA
POWER SUPPLY CURRENT (Inputs and Outputs open)
ICC
ICCO
Power Supply Current for VCC
Power Supply Current for VCCOx
(Inputs and Outputs Open)
(Inputs and Outputs Open)
CML OUTPUTS (Note 6)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VCC = 1.8 V, VCCOx = 1.8 V
VCC = 1.8 V, VCCOx = 1.2 V
VCCOx – 40
1760
1160
VCCOx – 20
1780
1180
VCCOx
1800
1200
mV
VCC = 1.8 V, VCCOx = 1.8 V
VCC = 1.8 V, VCCOx = 1.2 V
VCCOx – 500
1300
700
VCCOx – 400
1400
800
VCCOx – 275
1525
925
mV
VCC − 100
mV
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figure 6)
Vth
Input Threshold Reference Voltage Range (Note 8)
1050
VIH
Single−Ended Input HIGH Voltage
Vth + 100
VCC
mV
VIL
Single−Ended Input LOW Voltage
GND
Vth − 100
mV
VISE
Single−Ended Input Voltage (VIH − VIL)
200
1200
mV
VCC − 300
mV
VREFAC
VREFAC
Output Reference Voltage @ 100 mA for Capacitor − Coupled
Inputs, Only
VCC − 550
VCC − 450
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 9) (Figures 4 and 7)
VIHD
Differential Input HIGH Voltage (IN, IN)
1100
VCC
mV
VILD
Differential Input LOW Voltage (IN, IN)
GND
VCC − 100
mV
VID
Differential Input Voltage (IN, IN) (VIHD − VILD)
100
1200
mV
VCMR
Input Common Mode Range (Differential Configuration, Note 10)
(Figure 9)
1050
VCC − 50
mV
IIH
Input HIGH Current IN/IN (VTO / VT1 Open)
−150
150
mA
IIL
Input LOW Current IN/IN (VTO / VT1 Open)
−150
150
mA
CONTROL INPUT (SEL Pin)
VIH
Input HIGH Voltage for Control Pin
VCC x 0.65
VCC
mV
VIL
Input LOW Voltage for Control Pin
GND
VCC x 0.35
mV
IIH
Input HIGH Current
−150
20
+150
mA
IIL
Input LOW Current
−150
5
+150
mA
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor (Measured from INx to VTx)
45
50
55
W
RTOUT
Internal Output Termination Resistor
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input parameters vary 1:1 with VCC. and output parameters vary 1:1 with VCCOx.
6. CML outputs (Qn/Qn) have internal 50 W source termination resistors and must be externally terminated with 50 W to VCCOx for proper
operation.
7. Vth, VIH, VIL and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
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NB7V586M
Table 6. AC CHARACTERISTICS VCC = 1.8 V $5%, VCCO1 = 1.2 V $5% or 1.8 V $5%, VCCO2 = 1.2 V $5% or 1.8 V $5%,
VCCO3 = 1.2 V $5% or 1.8 V $5%, GND = 0 V, TA = −40°C to 85°C (Note 11)
Characteristic
Symbol
Min
Typ
6.0
fMAX
Maximum Input Clock Frequency, VOUTPP w 200 mV
4.0
fDATAMAX
Maximum Operating Input Data Rate (PRBS23)
10
VOUTPP
Output Voltage Amplitude (See Figures 4, Note 15)
fin v 4.0 GHz
200
330
tPLH, tPHL
Propagation Delay to Output Differential @ 1 GHz,
Measured at Differential Crosspoint
INx/INx to Qn/Qn
SEL to Qn
125
125
175
tPLH TC
Propagation Delay Temperature Coefficient
tSKEW
Output − Output Skew (Within Device) (Note 12)
Device − Device Skew (tpd Max − tpdmin)
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 4.0 GHz
tJITTER
Output Random Jitter (RJ) (Note 13)
Deterministic Jitter (DJ) (Note 14)
VINPP
Input Voltage Swing (Differential Configuration) (Note 15)
tr, tf
Output Rise/Fall Times @ 1 GHz (20% − 80%)
Max
GHz
Gbps
mV
250
300
100
45
fin v 4.0 GHz
10 Gbps
ps
fs/°C
30
50
ps
50
55
%
0.2
0.8
10
ps rms
ps pk−pk
1200
mV
65
ps
100
Qn, Qn
Unit
50
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV source, 50% duty cycle clock source. All outputs must be loaded with external 50 W to VCCOx. Input edge rates
40 ps (20% − 80%).
12. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the crosspoint of the outputs.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
15. Input and output voltage swing is a single−ended measurement operating in differential mode.
OUTPUT VOLTAGE AMPLITUDE
(mV)
400
350
VCC
300
250
INx
200
50 W
VTx
150
100
50 W
INx
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
fout, CLOCK OUTPUT FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP) vs. Input
Frequency (fin) at Ambient Temperature (Typical)
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Figure 3. Input Structure
NB7V586M
INx
VID = |VIHD(IN) − VILD(IN)|
INx
Q
VIHD
INx
VINPP = VIH(INx) − VIL(INx)
INx
VILD
VOUTPP = VOH(Qn) − VOL(Qn)
Q
tPHL
tPLH
Figure 4. Differential Inputs Driven Differentially
Figure 5. AC Reference Measurement
INx
INx
INx
INx
Vth
Vth
Figure 6. Differential Input Driven Single−Ended
VCC
Vthmax
Vth
VCC
VIHmax
VILmax
IN
Vthmin
GND
Figure 7. Differential Inputs Driven Differentially
VIHDmax
VCMmax
VILDmax
VID = VIHD − VILD
VIHDtyp
INx
VIH
Vth
VIL
VCMR
VIHmin
VILmin
INx
VILDtyp
VIHDmin
VILDmin
VCMmin
GND
Figure 8. Vth Diagram
Figure 9. VCMR Diagram
NB7V586M
VCCOx
VCC (Receiver)
50 W
50 W
Q
50 W
50 W
Q
16 mA
GND
Figure 10. Typical CML Output Structure and Termination
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NB7V586M
VCC
VCC
VCC
ZO = 50 W
LVPECL
Driver
VCC
NB7V586M
ZO = 50 W
INx
50 W
VT = VCC − 2 V
ZO = 50 W
LVDS
Driver
50 W
50 W
GND
GND
Figure 11. LVPECL Interface
GND
Figure 12. LVDS Interface
VCC
VCC
VCC
VCC
NB7V586M
ZO = 50 W
INx
50 W
VT = VCC
ZO = 50 W
Differential
Driver
50 W
NB7V586M
INx
50 W
VT = VREFAC*
ZO = 50 W
INx
GND
50 W
INx
GND
CML
Driver
INx
VT = Open
ZO = 50 W
INx
ZO = 50 W
NB7V586M
50 W
INx
GND
GND
Figure 14. Capacitor−Coupled
Differential Interface
(VT Connected to VREFAC)
Figure 13. Standard 50 W Load CML Interface
GND
*VREFAC bypassed to ground with a 0.01 mF capacitor
ORDERING INFORMATION
Package
Shipping†
NB7V586MMNG
QFN32
(Pb−Free)
74 Units / Rail
NB7V586MMNR4G
QFN32
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB7V586M
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
PIN ONE
LOCATION
2X
ÉÉ
0.15 C
2X
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32 X
0.08 C
C
L
32 X
9
D2
SEATING
PLANE
A1
SIDE VIEW
SOLDERING FOOTPRINT*
5.30
EXPOSED PAD
16
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
2.950 3.100 3.250
5.00 BSC
2.950 3.100 3.250
0.500 BSC
0.200
−−−
−−−
0.300 0.400 0.500
K
32 X
17
3.20
8
32 X
0.63
E2
1
24
32
3.20
25
b
0.10 C A B
32 X
5.30
e
0.05 C
32 X
0.28
BOTTOM VIEW
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NB7V586M/D
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