Cypress CY7C1049CV33-12VC 512k x 8 static ram Datasheet

CY7C1049CV33
4-Mbit (512K x 8) Static RAM
Functional Description[1]
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• High speed
— tAA = 10 ns
• Low active power
— 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The CY7C1049CV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1049CV33 is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
Top View
I/O0
INPUT BUFFER
CE
I/O1
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
512K x 8
ARRAY
I/O3
I/O4
I/O5
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
VSS
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
A 11
A 12
A 13
A 14
A 15
A 16
A17
A18
WE
OE
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
TSOP II
Top View
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05006 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised July 19, 2004
CY7C1049CV33
Selection Guide
Maximum Access Time
Maximum Operating Current
-10
-12
-15
Unit
8
10
12
15
ns
Commercial
100
90
85
80
mA
Industrial
110
100
95
90
mA
-
-
-
95
mA
10
10
10
10
mA
-
-
-
15
mA
Automotive
Maximum CMOS Standby Current
-8[]
Commercial / Industrial
Automotive
Shaded areas contain advance information.
Pin Definitions
Pin Name
36-SOJ
Pin Number
44 TSOP-II
Pin Number
I/O Type
A0-A18
1-5,14-18,
3-7,16-20,
Input
20-24,32-35
26-30,38-41
I/O0 - I/O7
7,8,11,12,25,
26,29,30
9,10,13,14,
NC[2]
19,36
Input/Output
Bidirectional Data I/O lines. Used as input or output lines
depending on operation
No Connect
No Connects. This pin is not connected to the die
31,32,35,36
1,2,21,22,23,
24,25,42,43,
Description
Address Inputs used to select one of the address locations.
44
WE
13
15
Input/Control
Write Enable Input, active LOW. When selected LOW, a WRITE
is conducted. When selected HIGH, a READ is conducted.
CE
6
8
Input/Control
Chip Enable Input, active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
OE
31
37
Input/Control
Output Enable, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data
pins.
VSS, GND
10,28
12,34
Ground
Ground for the device. Should be connected to ground of the
system.
VCC
9,27
11,33
Power Supply Power Supply inputs to the device.
Notes:
2. NC pins are not connected on the die.
Document #: 38-05006 Rev. *C
Page 2 of 9
CY7C1049CV33
Maximum Ratings
DC Voltage Applied to Outputs
in High-Z State[3].................................... –0.5V to VCC + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Range
Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V
Ambient Temperature
VCC
0°C to +70°C
3.3V ± 0.3V
Commercial
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Electrical Characteristics Over the Operating Range
-8[]
Parameter
Description
-10
-12
-15
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Test Conditions
VOH
Output HIGH Voltage
VCC = Min.; IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min.,; IOL = 8.0 mA
0.4
V
VIH
Input HIGH Voltage
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
V
VIL
Input LOW Voltage[3]
–0.3
0.8
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
IIX
Input Load Current
GND < VI < VCC
–1
+1
–1
+1
–1
+1
–1
+1
µA
Automotive
-
-
-
-
-
-
–20
+20
µA
IOZ
Output Leakage
Current
GND < VOUT <
VCC,
Output Disabled
Com’l / Ind’l
–1
+1
–1
+1
–1
+1
–1
+1
µA
Automotive
-
-
-
-
-
-
–20
+20
µA
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Com’l
100
90
85
80
mA
Ind’l
110
100
95
90
mA
-
-
-
95
mA
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > Com’l / Ind’l
VIH; VIN > VIH or Automotive
VIN < VIL, f = fMAX
40
40
40
40
mA
-
-
-
45
mA
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
Com’l/Ind’l
CE > VCC – 0.3V, Automotive
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10
10
10
10
mA
-
-
-
15
mA
ICC
2.4
2.4
0.4
Com’l / Ind’l
Automotive
ISB1
ISB2
2.4
2.4
0.4
0.4
V
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
Max.
Unit
8
pF
8
pF
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Thermal Resistance[4]
Parameter
ΘJA
ΘJC
Description
Test Conditions
Thermal Resistance Test conditions follow
standard test methods
(Junction to
and procedures for
Ambient)
Thermal Resistance measuring thermal
(Junction to Case) impedance, per EIA /
JESD51.
36-pin SOJ
(Non
Pb-Free)
36-pin SOJ
( Pb-Free)
44-TSOP-II
(Non
Pb-Free)
44-TSOP-II
( Pb-Free)
Unit
46.51
46.51
41.66
41.66
°C/W
18.8
18.8
10.56
10.56
°C/W
Notes:
3. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05006 Rev. *C
Page 3 of 9
CY7C1049CV33
AC Test Loads and Waveforms[5]
12-, 15-ns devices:
8-, 10-ns devices:
Z = 50Ω
50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R 317Ω
3.3V
OUTPUT
OUTPUT
30 pF*
R2
351Ω
30 pF
1.5V
(b)
(a)
High-Z characteristics:
90%
GND
R 317Ω
ALL INPUT PULSES
3.0V
90%
OUTPUT
10%
10%
(c)
Rise Time: 1 V/ns
3.3V
R2
351Ω
5 pF
(d)
Fall Time: 1 V/ns
AC Switching Characteristics[6] Over the Operating Range
-8[]
Parameter
Description
Min.
-10
Max.
Min.
-12
Max.
Min.
-15
Max.
Min.
Max.
Unit
Read Cycle
tpower[7]
VCC(typical) to the first access
1
1
1
1
µs
tRC
Read Cycle Time
8
10
12
15
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
8
3
10
3
12
3
15
ns
3
ns
tACE
CE LOW to Data Valid
8
10
12
15
ns
tDOE
OE LOW to Data Valid
4
5
6
7
ns
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z[8, 9]
7
ns
tLZCE
CE LOW to Low-Z[9]
tHZCE
CE HIGH to High-Z[8, 9]
7
ns
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
15
ns
0
0
4
3
0
5
3
4
0
3
5
0
8
0
6
3
6
0
10
ns
ns
0
12
ns
Write Cycle[10, 11]
tWC
Write Cycle Time
8
10
12
15
ns
tSCE
CE LOW to Write End
6
7
8
10
ns
tAW
Address Set-up to Write End
6
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
6
7
8
10
ns
tSD
Data Set-up to Write End
4
5
6
7
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low-Z[9]
3
3
3
3
ns
High-Z[8, 9]
tHZWE
WE LOW to
4
5
6
7
ns
Notes:
5. AC characteristics (except High-Z) for all 8-ns and 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the
Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document #: 38-05006 Rev. *C
Page 4 of 9
CY7C1049CV33
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
ICC
50%
ISB
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for Read cycle.
Document #: 38-05006 Rev. *C
Page 5 of 9
CY7C1049CV33
Switching Waveforms (continued)
Write Cycle No. 1(WE Controlled, OE HIGH During Write)[15, 16]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 17
tHZOE
Write Cycle No. 2 (WE Controlled, OE LOW)[16]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 17
tHD
DATA VALID
tHZWE
tLZWE
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high-impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05006 Rev. *C
Page 6 of 9
CY7C1049CV33
Truth Table
CE
OE
WE
H
X
X
High-Z
I/O0–I/O7
Power-down
Mode
Standby (ISB)
Power
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High-Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
10
12
15
Ordering Code
Package
Name
Package Type
CY7C1049CV33-10VC
V36
36-lead (400-Mil) Molded SOJ
CY7C1049CV33-10ZC
Z44
44-pin TSOP II
CY7C1049CV33-10VI
V36
36-lead (400-Mil) Molded SOJ
CY7C1049CV33-10ZI
Z44
44-pin TSOP II
CY7C1049CV33-12VC
V36
36-lead (400-Mil) Molded SOJ
CY7C1049CV33-12ZC
Z44
44-pin TSOP II
CY7C1049CV33-12VI
V36
36-lead (400-Mil) Molded SOJ
CY7C1049CV33-12ZI
Z44
44-pin TSOP II
CY7C1049CV33-15VXC
V36
36-lead (400-Mil) Molded SOJ (Pb-Free)
CY7C1049CV33-15VC
V36
36-lead (400-Mil) Molded SOJ
CY7C1049CV33-15ZXC
Z44
44-pin TSOP II (Pb-Free)
CY7C1049CV33-15ZC
Z44
44-pin TSOP II
CY7C1049CV33-15VI
V36
36-lead (400-Mil) Molded SOJ
CY7C1049CV33-15ZI
Z44
44-pin TSOP II
CY7C1049CV33-15VE
V36
36-lead (400-Mil) Molded SOJ
CY7C1049CV33-15ZE
Z44
44-pin TSOP II
Document #: 38-05006 Rev. *C
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Automotive
Page 7 of 9
CY7C1049CV33
Package Diagrams
36-Lead (400-Mil) Molded SOJ V36
51-85090-B
44-pin TSOP II Z44
51-85087-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05006 Rev. *C
Page 8 of 9
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1049CV33
Document History Page
Document Title: CY7C1049CV33 4-Mbit (512K x 8) Static RAM
Document Number: 38-05006
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
112569
03/06/02
HGK
New Data Sheet
*A
114091
04/25/02
DFP
Changed Tpower unit from ns to µs
*B
116479
09/16/02
CEA
Add applications foot note to data sheet, page 1.
*C
262949
See ECN
RKF
Added Automotive Specs to Datasheet
Added ΘJA and ΘJC values on Page #3.
Document #: 38-05006 Rev. *C
Page 9 of 9
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