STMicroelectronics L9341V Quad low side driver Datasheet

L9341
QUAD LOW SIDE DRIVER
AVANCE DATA
DU/DT AND DI/DT CONTROL
PWM CONTROLLED OUTPUT CURRENT
SHORT CURRENT PROTECTION AND DIAGNOSTIC
INTEGRATED FLYBACK DIODE
UNDERVOLTAGE SHUTDOWN
OVERVOLTAGE AND UNDERVOLTAGE DIAGNOSTIC
OVERTEMPERATURE DIAGNOSTIC
MULTIPOWER BCD TECHNOLOGY
Multiwatt 15
ORDERING NUMBERS: L9341V
L9341H
DESCRIPTION
The L9341 is a monolithic integrated circuit realized in Multipower BCD-II mixed technology. The
driver is intended for inductive loads in synchronous PWM applications, especially for valve driv-
ers. The output voltage and current rise and fall
slopes du/dt and di/dt are controlled.
BLOCK & APPLICATION DIAGRAM
V
s
Is
220nF
VS
7
C
D
BAT
COMP1
VCC
Vcc
BAT
V
UNDERVOLTAGE
4
flyth
SHUTDOWN
I cc
DIAGNOSTIC
10uF
COMP2
OUT1
V
offth
2
I
THERMAL
FLAG
OUT1
10nF
di / dt & du / dt
CONTROL
C
O1
I outs
DRIVER
REXT
SHORT
12
10nF
CURRENT
PROTECTION
R ext
12.4k Ω
RES1
9
RES2
CHANNEL 1
BIAS
SERIAL
10
INTERFACE
&
CS
OUT2
CHANNEL 2
1
I
PWM
CONTROLL
3
C
SCLK
OUT2
O2
10nF
11
OUT3
SDI
CHANNEL 3
5
15
I
SDO
C
OUT3
O3
13
10nF
OSC
OUT4
6
CHANNEL 4
14
IOUT4
C
8
C
March 1994
OSC
O4
10nF
GND
I
GND
1/10
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L9341
PIN CONNECTION (Top view)
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
VCC
VCC Voltage Range
Parameter
-0.3 to 6
V
VS
VS Voltage Range
-0.3 to 24
V
Vspmax
VS Voltage Range for t ≤ 400ms
-2 to 40
V
Vst
Schaffner Transient Pulses on VS
see note 1
V
Vin
Input Voltage Range for SDI; SCLK;CS;RES1;RES2
Vout
Output Voltage Range for all Outputs:
Negative
Positive
Iout
-0.3to VCC+0.3
– 0.3
intern. clamped to VS
V
V
Output Current for all Outputs:
Negative
Positive
–2
+2
A
A
for Transient with t < 10ms
Negative
Positive
–5
5
A
A
Schaffner Transient Pulses on Output
VESD
ESD Voltage Capability (MIL 883 C)
see note 2
1500
V
THERMAL DATA
Symbol
Parameter
Value
Unit
Rth j-case
Thermal Resistance Junction to Case
3
°C/W
Rth j-amb
°C/W
Thermal Resistance Junction to Ambient mounted on PC Board
35
Tsdh
Thermal Hysteresis
20
°C
Tsd
Thermal Diagnostic
Tj > 150
°C
Notes:
1. Schaffner transient specification: DIN 40839 test waveforms of the following type: 1, 2, 3a, 3b, 5 and 6.
The pulses are applied to the application circuit according to fig. 3.
2. The maximum output current results from the Schaffner pulses specified in note 1.
2/10
L9341
ELECTRICAL CHARACTERISTICS (Unless otherwise specified: 8V ≤ VS ≤ 24V; 4.7V ≤ VCC ≤ 5.3V; –
40 °C ≤ Tj ≤ 150°C; IO ≤ 1A (note 3); IO ≤ 1.5A; Vsp = VS for t ≤ 400ms; VOUTP = VOUT for t ≤ 400ms;
Rext = 12.4KΩ ± 1%).
Symbol
Parameter
Iccq
Vcc Quiescent Current
Isq
Test Condition
Vs Quiescent Current
All Outputs Off
Vccu
Vcc Undervoltage Threshold
See Note 4
Vcc r
Vcc Range for RES1 and RES2
Operation
Ron
On Resistance
Io = 1A
Io off
Off State Output Current
Outputs Off
1.4V ≤ Vo ≤ Vs
Voutp = Vsp = 40V
Voutf
Igndf
Output Voltage During Flyback
Min.
All Outputs Off
3
Typ.
Max.
Unit
1
3
mA
14
25
mA
4
4.7
V
3
V
Tj = 125°C
Tj = 25°C
1
1
2.5
Io = 1A Output Off
Tj = 25°C
Tj = 125°C
Current to GND during Flyback
(see note 5)
Io = 1A Output Off
Vs = 24V
Vsp = 40V
Vsp - Vo = 40V
17
20
750
450
mΩ
mΩ
4
10
mA
mA
Vs +1.3
Vs +1.1
V
V
44
52
mA
mA
Iout r
Reverse Leakage Current
500
µA
VinH
High Input Level of SCLK,
SDI, CS, RES1, RES2
0.7*Vcc
Vcc +0.3
V
VinL
Low Input Level of SCLK,
SDI, CS, RES1, RES2
– 0.3
0.3*Vcc
V
VREShys
Hysteresis of Reset Inputs
RES1, RES2
0.3
1
V
IinRESH
Input Current on RES1,RES2
– 10
5
10
10
µA
µA
µA
RES i = H; -2V ≤ Vsp ≤ 8V
RES i = H; 8V ≤ Vsp ≤ 40V
Iin
Input Current on SCLK,SDI,CS
– 2V ≤ Vsp ≤ 40V
– 10
10
VSDOH
High Level SDO Output Voltage
ISDO = -1mA -2V ≤ Vsp ≤ 40V
0.9*Vcc
Vcc
V
VSDOL
Low Level SDO Output Voltage
ISDO = 1mA -2V ≤ Vsp ≤ 40V
0
0.4
V
ISDOZ
SDO Tristate High-Z Leakage
Current
0 ≤ VSDO ≤ Vcc
– 2V ≤ Vsp ≤ 40V
– 10
10
µA
1/16
15/16
PWMduty
PWM Duty Cycle
Kf
Frequency Accuracy Constant
See Note 6
Vflyth
Flyback Diagnostic Comparator
Threshold
40 ≥ Vsp ≥ 8V
Vs ≤ 8V
Voffth
Off State Diagnostic
Comparator Threshold
0.93*Kfn
Kfn
1.07*Kfn
Vs – 1
1.5
Vs – 0.4
V
V
1.5
2
V
1.5
2.5
A
5
15
µs
Ioutl
Output Current Limitation Threshold
tdpo
Delay Time PWM Signal to Out.
Sov
Output Voltage Rise and Fall
Slope | du/dt |
(from 10 to 90% of Vo) Fig. 2
1.0
10
V/µs
Soc
Output Current Rise and Fall
Slope |di/dt|
0.1 ≤ Io ≤ 1.5A
(from 10 to 90% of Io)
25
125
mA/µs
see Note 7
Notes:
1 T
∫ Io (t) dt ;
T 0
4. The outputs are switced off for Vcc ≤ Vccu. The logic is not reseted. For a reset, RES1 or RES2 must be used.
5. This current is measured in the GND - terminal when one single output is in flyback and consists of the supply current added to the value
of the output current source and the leakage current of the flyback diode. This leakage current is less than 1% of the nominal flyback current.
fosc
Kf
with fosc =
6. The PWM frequency is defined by an external capacitor. The PWM oscillator frequency is: fpwm =
⋅ 1A/V and kin = 15 ⋅ 10-6;
32
Cosc
the range is: 300Hz ≤ fpwm ≤ 3000Hz. The OSC Pin can be alternatively driven by an external TTL / CMOS signal.
7. For Iout ≥ Ioutl an internal comparator switches the corresponding output off for the current PWM cycle.
3. The mean value is Io =
3/10
L9341
Figure 1: Logic Diagram of PWM Generation.
INTERNAL
CLOCK
CLK
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWM1
PWM2
PWM3
PWM4
Figure 2: Output Switching Diagram.
+12V
Is
220 nF
Internal PWM Signal
f
Vs
5
20 mH
D
If
DMOS
12V
t dpo
Output Voltage V
OUT
du/dt
out
ID
du/dt
0
5%
I out
1A
t dpo
Current through
Low Side Switch
10 nF
V out
ID
di/dt
di/dt
0
5%
1A
GND
Current through
Flyback Diode
Is
I
di/dt
f
di/dt
0
Figure 3: Test Circuit for Schaffner Pulses.
+12V
220 nF
D1
-2V to 40 V
Schaffner
Vs
VCC
+5V
10 uF
Generator
OUT1
OUT2
OUT3
OUT4
GND
4 x 1 nF
4 x 10 nF
4/10
L9341
Figure 4: Synchronous Serial Interface Protocol.
CS
SCLK
SDI
MSB
14
13
12
11
3
2
1
LSB
SDO
MSB
14
13
12
11
3
2
1
LSB
CS
tclcl t chcl
t ch
t clch
tcl
t chch
SCLK
t su
SDI
th
15
t clz
SDO
fclock
0
td
t zch
t oh
15
14
0
Clock Frequency
min. DC
tch
Width of Clock Input High Puls
min. 200ns
tcl
Widh of Clock Input Low Puls
min. 200ns
tcicl
Clock Low Before CS Low
min. 200ns
tchcl
Clock High After CS Low
min. 200ns
tclch
Clock Low Before CS High
min. 200ns
tchch
Clock High After CS High
min. 200ns
tciz
SDO Low-Z CS Low
min. 0ns
tzch
SDO High-Z CS High
tsu
SDI Input Setup Time
min. 80ns
th
SDI Input Hold Time
min. 80ns
td
SDO Output Delay Time (CL = 50pF)
toh
SDO Output Hold Time
max. 2MHz
max. 400ns
max. 400ns
max. 100ns
min. 0ns
5/10
L9341
Figure 5: PWM Generation Function Table.
Bit 3 - 0
PWM1
PWM2
PWM3
PWM4
OUTPUT
0000
15/16
15/16
15/16
15/16
OFF
0001
1/16
15/16
1/16
15/16
ON
0010
2/16
14/16
2/16
14/16
ON
0011
3/16
13/16
3/16
13/16
ON
0100
4/16
12/16
4/16
12/16
ON
0101
5/16
11/16
5/16
11/16
ON
0110
6/16
10/16
6/16
10/16
ON
0111
7/16
9/16
7/16
9/16
ON
1000
8/16
8/16
8/16
8/16
ON
1001
9/16
7/16
9/16
7/16
ON
1010
10/16
6/16
10/16
6/16
ON
1011
11/16
5/16
11/16
5/16
ON
1100
12/16
4/16
12/16
4/16
ON
1101
13/16
3/16
13/16
3/16
ON
1110
14/16
2/16
14/16
2/16
ON
1111
15/16
1/16
15/16
1/16
ON
Figure 6: PWM Information From Microcontroller to QLSD.
6/10
Bit. Nr.
Name
0
P10
PWM Duty Cycle for Channel 1 / Bit 0: LSB
Contents
1
P11
PWM Duty Cycle for Channel 1 / Bit 1
2
P12
PWM Duty Cycle for Channel 1 / Bit 2
3
P13
PWM Duty Cycle for Channel 1 / Bit 3 : MSB
4
P20
PWM Duty Cycle for Channel 2 / Bit 0 : LSB
5
P21
PWM Duty Cycle for Channel 2 / Bit 1 :
6
P22
PWM Duty Cycle for Channel 2 / Bit 2 :
7
P23
PWM Duty Cycle for Channel 2 / Bit 3 : MSB
8
P30
PWM Duty Cycle for Channel 3 / Bit 0 : LSB
9
P31
PWM Duty Cycle for Channel 3 / Bit 1 :
10
P32
PWM Duty Cycle for Channel 3 / Bit 2 :
11
P33
PWM Duty Cycle for Channel 3 / Bit 3 : MSB
12
P40
PWM Duty Cycle for Channel 4 / Bit 0 : LSB
13
P41
PWM Duty Cycle for Channel 4 / Bit 1:
14
P42
PWM Duty Cycle for Channel 4 / Bit 2 :
15
P43
PWM Duty Cycle for Channel 4 / Bit 3 : MSB
L9341
Figure 7: Diagnostic Information from QLSD to Microcontroller.
Bit Nr.
Name
0
F11
COMP1 State at Positive Edge of PWM1 (0: Vout1 > Vflyth; 1: Vout1 < Vflyth)
Contents
1
F12
COMP2 State at Negative Edge of PWM1 (1: Vout1 > Voff th; 0 : Vout1 < Vofth)
2
F21
COMP1 State at Positive Edge of PWM2 (0: Vout2 > Vflyth; 1: Vout2 < Vflyth)
3
F22
COMP2 State at Negative Edge of PWM2 (1: Vout2 > Voft h; 0 : Vout2 < Vofth)
4
F31
COMP1 State at Positive Edge of PWM3 (0: Vout3 > Vflyth; 1: Vout3 < Vflyth)
5
F32
COMP2 State at Negative Edge of PWM3 (1: Vout3 > Voff th; 0 : Vout3 < Vofth)
6
F41
COMP1 State at Positive Edge of PWM4 (0: Vout4 > Vflyth; 1: Vout4 < Vflyth)
7
F42
8
RES1
Logic State of RES1 Input (0: RES1 = L ; 1: RES1 = H)
Logic State of RES2 Input (0: RES2 = L ; 1: RES2 = H)
COMP2 State at Negative Edge of PWM4 (1: Vout4 > Voffth; 0 : Vout4 < Vofth)
9
RES2
10
TSDF
11
C1
Current at Negative Edge of PWM1 ( 0: Iout > Ioutl ; 1: Iout < Ioutl)
12
C2
Current at Negative Edge of PWM2 ( 0: Iout > Ioutl ; 1: Iout < Ioutl)
13
C3
Current at Negative Edge of PWM3 ( 0: Iout > Ioutl ; 1: Iout < Ioutl)
14
C4
Current at Negative Edge of PWM4 ( 0: Iout > Ioutl ; 1: Iout < Ioutl)
15
1
Thermal Diagnostic Flag ( 0: Overtemperature ; 1:Normal )
Framing Information (always 1)
Figure 8.
PWM
PWM
ID
V OUT
tC
V OUT
t dPO
t dPO
tV
t
tV
t
PWMON
min
PWMOFF
min
Sample point COMP2
Sample point COMP1
Sample point COMP1
Sample point COMP2
Fig.1
Fig.
A
Fig.2
Fig.
B
Note:
For safty diagnostic take notice of the following conditions:
tPWMON ≥ tdPOMAX + tC + tV (see Fig. A)
tPWMOFF ≥ tdPOMAX + tV (see Fig. B)
tC =
ID
SOCMIN
tV =
Voutfmax
SOVMIN
7/10
L9341
FUNCTIONAL DESCRIPTION
The U511 is a PWM quad low side driver for inductive loads. The duty cycle of the internal generated PWM signal is set by a microcontroller via
a serial interface for each output. An output slope
limitation for both dv/dt and di /dt is implemented
to reduce RFI. The PWM generation is realized
avoiding a simultaneous output switching. As a
result, di/dt becomes smaller. Integrated flyback
diodes clamp the output voltage during the flyback phase of the low side switches.
The driver is protected against short circuit. An
undervoltage shutdown circuit switches off all outputs if Vcc is less then Vccu. Below the shutdown
voltage all outputs remain in off state regardless
of the input state. After each malfunction which
resets the driver, only the serial link interface can
reactivate the normal function. In case of overcurrent (Iout = I out1), an internal comparator switches
the output off. The overcurrent information can be
read via the serial link for each driver separately
at the negative edge of the corresponding PWM
signal.
The interface to the microcontroller is realized
with a 16 bit synchronous serial peripheral interface (SPI). If CS is switched low, the serial link
becomes active and SDO goes to low impedance.
At the rising edge of the SCLK signal, one of the
16 bit of data stored in a shift register appear sequencely at SDO. These data contain the 8 error
flags, the status of thermal diagnostic flag and the
external reset sources RES1, RES2 and the overcurrent flgs c1...c4. The last bit is framing information (see fig. 7). At each falling edge of SCLK,
one of the 16 bits of data sent by the microcontroller is transferred via the SDI input to the driver.
These data contain the duty-cycle information for
the internal PWM generation (4 times 4 bit).
8/10
On the rising edge of CS the previously stored information is transferred to the circuits. SDO become now high impedance and SDI is inactive.
The serial interface of the QLSD is cascadable
with the serial link interface of another QLSD,
thus obtaining a 32 bit serial link information wich
can control eight inductive loads. For a safety
data transfer the takeover of data bits is only realized when the number of SCLK - clocks is n x 16
(n ≥ 1).
The PWM duty cycle is set by 4 bit for each output independently via the serial link. If all four bits
for an output are zero, the output is turned off, but
the error diagnosis will work correctly (see fig. 5
and 6). The PWM frequency is defined by an external capacitor on the OSC pin. Rext defines
through the reference current the output current
slope, the diagnostic current sink and the internal
oscillator frequency (together with Cosc).
For error diagnosis the voltage on the output is
measured during the on and off state of the particular output driver. Upon the rising edge of the
PWM signal (at this moment the power output is
off and will be switched on) the status of COMP1
is stored into an internal latch. On the falling edge
of the PWM signal ( the power output is on and
will be switched off) the status of COMP2 is
stored into another internal latch. This information
can be read via the serial link for each output
driver separately (see fig. 7).
The thermal diagnostic switch the thermal flag to
0 in case of overtemperature T ≥ Tsd. It will be
switched to 1 with the hysteresis Tsdth in case of
T < Tsd - Tsdh.
To avoid male functions due to extensive noise or
spikes at the supply pins VCC, VS and Rext must
be blocked externally via capacitors.
L9341
MULTIWATT15 PACKAGE MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
5
0.197
B
2.65
0.104
C
1.6
0.063
D
1
0.039
E
0.49
0.55
0.019
0.022
F
0.66
0.75
0.026
0.030
G
1.02
1.27
1.52
0.040
0.050
0.060
G1
17.53
17.78
18.03
0.690
0.700
0.710
H1
19.6
0.772
H2
L
20.2
0.795
21.9
22.2
22.5
0.862
0.874
0.886
L1
21.7
22.1
22.5
0.854
0.870
L2
17.65
18.1
0.695
L3
17.25
17.5
17.75
0.679
0.689
L4
10.3
10.7
10.9
0.406
0.421
L7
2.65
2.9
0.104
M
4.25
4.55
4.85
0.167
0.179
M1
4.63
5.08
5.53
0.182
0.200
S
1.9
2.6
0.075
0.102
S1
1.9
2.6
0.075
0.102
Dia1
3.65
3.85
0.144
0.152
0.886
0.713
0.699
0.429
0.114
0.191
0.218
9/10
L9341
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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10/10
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