Hynix HYMP512R72L4-E3 Ddr2 sdram registered dimm Datasheet

128Mx72 bits
DDR2 SDRAM Registered DIMM
HYMP512R72(L)4
Revision History
No.
History
Draft Date
0.1
1) Defined Target Spec.
Feb. 2004
0.2
1) Added Pin Capacitance Spec. & IDD Spec.
2) Corrected SPD typo(byte #22,#42)
Apr. 2004
Corrected Pin assignment table
July 2004
Remark
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / July 2004
1
128Mx72 bits
DDR2 SDRAM Registered DIMM
HYMP512R72(L)4
DESCRIPTION
Hynix HYMP512R72(L)4 series is registered 240-pin double data rate 2 Synchronous DRAM Dual In-Line Memory
Modules(DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix HYMP512R72(L)4 series consists of eighteen 128Mx4 DDR2 SDRAMs in 60-Lead FBGA chipsize packages. Hynix HYMP512R72(L)4 series provide a high performance 8-byte interface in 133.35mm width form factor of industry stanard. It is suitable for easy
interchange and addition. Hynix HYMP512R72(L)4 series is designed for high speed of up to 333MHz and offers fully
synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and
control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4-bit prefetched to achieve very
high bandwidth. All input and output voltage levels are compatible with SSTL_1.8. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMP512R72(L)4 series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
1GB (128M x 72) Registered DDR2 DIMM based on
128Mx4 DDR2 SDRAMs
•
JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
•
JEDEC Standard 240-pin dual in-line memory module (DIMM)
•
Error Check Correction (ECC) Capability
•
All inputs and outputs are compatible with SSTL_1.8
interface
•
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
•
Fully differential clock operations (CK & /CK)
•
Programmable CAS Latency 3 / 4 /5 supported
•
Programmable Burst Length 4 / 8 with both sequential and interleave mode
•
All inputs and outputs SSTL_1.8 compatible
•
Auto refresh and self refresh supported
•
7.8us refresh period at Lower than TCASE 85℃,
3.9us( 85 ℃ < TCASE ≤ 95℃)
•
Serial Presence Detect(SPD) with EEPROM
•
DDR2 SDRAM Package: 60ball FBGA
ORDERING INFORMATION
Type
Part No.
Description
CL-tRCD-tRP
HYMP512R72(L)4-E4
4-4-4
HYMP512R72(L)4-E3
3-3-3
Form Factor
PC2-3200 (DDR2-400)
HYMP512R72(L)4-C5
PC2-4300 (DDR2-533)
HYMP512R72(L)4-C4
one rank 1GB
Reg. DIMM
5-5-5
4-4-4
HYMP512R72(L)4-Y6
6-6-6
HYMP512R72(L)4-Y5
5-5-5
240pin Registered DIMM
133.35 mm x 30,00 mm
(MO-237)
PC2-5300 (DDR2-667)
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / July 2004
2
HYMP512R72(L)4
Input/Output Functional Description
Symbol
Type
Polarity
Pin Description
CK0~CK1
IN
Positive
Edge
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CK0~CK1
IN
Negative
Edge
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CKE0~CKE1
IN
Active High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
S0~S1
IN
Active Low
Enables the associated DDR2 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but previous
operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
ODT0~ODT1
IN
Active High
On-Die Termination signals.
RAS, CAS, WE
IN
Active Low
When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the
command being entered.
Vref
Supply
Reference voltage for SSTL18 inputs
VDDQ
Supply
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current
DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
BA0~BA1
IN
-
Selects which DDR2 SDRAM internal bank of four is activated.
During a Bank Activate command cycle, Address input difines the row address(RA0~RA13)
A0~A9,A10/AP
A11~A13
IN
-
DQ0~DQ63,
CB0~CB7
IN
-
DM0~DM8
IN
Active High
VDD,VSS
During a Read or Write command cycle, Address input defines the column address when sampled at the
cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used
to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn
inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with
that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading.
Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to
VDD/VDDQ planes on these modules.
Supply
DQS0~DQS17
I/O
Positive
Edge
Positive line of the differential data strobe for input and output data
DQS0~DQS17
I/O
Negative
Edge
Negative line of the differential data strobe for input and output data
SA0~SA1
IN
-
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD
EEPROM address range.
SDA
I/O
-
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up.
SCL
IN
-
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from
SCL to VDDSPD to act as a pull up on the system board.
Supply
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM
supply is operable from 1.7V to 3.6V.
RESET
IN
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all
register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low
level (the PLL will remain synchronized with the input clock)
Par_In
IN
Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
Err_Out
OUT
VDDSPD
TEST
Rev. 0.2 / July 2004
Parity error found in the Address and Control bus
Used by memory bus analysis tools(unused on memory DIMMs)
3
HYMP512R72(L)4
PIN DESCRIPTION
Pin
Pin Description
Pin
Pin Description
CK0
Clock Input,positive line
ODT[1:0]
CK0
Clock input,negative line
VDDQ
DQs Power Supply
DQ0~DQ63
Data Input/Output
CKE0~CKE1
Clock Enable Input
On Die Termination Inputs
RAS
Row Address Strobe
CB0~CB7
Data check bits Input/Output
CAS
Column Address Strobe
DQS(0~8)
Data strobes
WE
Write Enable
DQS(0~8)
Data strobes,negative line
S0
Chip Select Input
DM(0~8),DQS(9~17)
Data Maskes/Data strobes
DQS(9~17)
Data strobes,negative line
RFU
Reserved for Future Use
A0~A9,A11~A13
A10/AP
BA0, BA1
Address input
Address input/Autoprecharge
SDRAM Bank Address
NC
No Connect
SCL
Serial Presence Detect(SPD) Clock Input
TEST
Memory bus test tool(Not Connected and Not
Usable on DIMMs)
SDA
SPD Data Input/Output
VDD
Core Power
SA0~SA2
E2PROM Address Inputs
Par_In
Parity bit for the Address and Control bus
Err_Out
Parity error found on the Addre
RESET
Reset Enable
CB0~CB7
VDDQ
VSS
VREF
VDDSPD
I/O Power Supply
Ground
Reference Power Supply
Power Supply for SPD
Data Strobe Inputs/Outputs
PIN Location
1 pin
121 pin
Rev. 0.2 / July 2004
Front Side
Back Side
64 pin 65 pin
184 pin 185 pin
120 pin
240 pin
4
HYMP512R72(L)4
PIN ASSIGNMENT
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
41
VSS
81
DQ33
121
VSS
161
CB4
201
VSS
2
VSS
42
CB0
82
VSS
122
DQ4
162
CB5
202
DM4/DQS13
3
DQ0
43
CB1
83
DQS4
123
DQ5
163
VSS
203
DQS13
4
DQ1
44
VSS
84
DQS4
124
VSS
164
DM8,DQS17
204
VSS
5
VSS
45
DQS8
85
VSS
125
DM0/DQS9
165
DQS17
205
DQ38
6
DQS0
46
DQS8
86
DQ34
126
DQS9
166
VSS
206
DQ39
7
DQS0
47
VSS
87
DQ35
127
VSS
167
CB6
207
VSS
8
VSS
48
CB2
88
VSS
128
DQ6
168
CB7
208
DQ44
9
DQ2
49
CB3
89
DQ40
129
DQ7
169
VSS
209
DQ45
10
DQ3
50
VSS
90
DQ41
130
VSS
170
VDDQ
210
VSS
11
VSS
51
VDDQ
91
VSS
131
DQ12
171
NC,CKE1
211
DM5/DQS14
12
DQ8
52
CKE0
92
DQS5
132
DQ13
172
VDD
212
DQS14
13
DQ9
53
VDD
93
DQS5
133
VSS
173
A15,NC
213
VSS
14
VSS
54
BA2,NC
94
VSS
134
DM1/DQS10
174
A14,NC
214
DQ46
15
DQS1
55
NC,Err_Out
95
DQ42
135
DQS10
175
VDDQ
215
DQ47
16
DQS1
56
VDDQ
96
DQ43
136
VSS
176
A12
216
VSS
17
VSS
57
A11
97
VSS
137
RFU
177
A9
217
DQ52
18
RESET
58
A7
98
DQ48
138
RFU
178
VDD
218
DQ53
19
NC
59
VDD
99
DQ49
139
VSS
179
A8
219
VSS
20
VSS
60
A5
100
VSS
140
DQ14
180
A6
220
RFU
21
DQ10
61
A4
101
SA2
141
DQ15
181
VDDQ
221
RFU
22
DQ11
62
VDDQ
102
NC(TEST)
142
VSS
182
A3
222
VSS
23
VSS
63
A2
103
VSS
143
DQ20
183
A1
223
DM6/DQS15
24
DQ16
64
VDD
104
DQS6
144
DQ21
184
VDD
224
NC,DQS15
25
DQ17
105
DQS6
145
VSS
225
VSS
26
VSS
VSS
106
VSS
146
DM2/DQS11
226
DQ54
Key
65
Key
185
CK0
27
DQS2
66
VSS
107
DQ50
147
DQS11
186
CK0
227
DQ55
28
DQS2
67
VDD
108
DQ51
148
VSS
187
VDD
228
VSS
29
VSS
68
NC,Err_Out
109
VSS
149
DQ22
188
A0
229
DQ60
30
DQ18
69
VDD
110
DQ56
150
DQ23
189
VDD
230
DQ61
31
DQ19
70
A10/AP
111
DQ57
151
VSS
190
BA1
231
VSS
32
VSS
71
BA0
112
VSS
152
DQ28
191
VDDQ
232
DM7/DQS16
33
DQ24
72
VDDQ
113
DQS7
153
DQ29
192
RAS
233
NC,DQS16
34
DQ25
73
WE
114
DQS7
154
VSS
193
S0
234
VSS
35
VSS
74
CAS
115
VSS
155
DM3/DQS12
194
VDDQ
235
DQ62
36
DQS3
75
VDDQ
116
DQ58
156
DQS12
195
ODT0
236
DQ63
37
DQS3
76
NC, S1
117
DQ59
157
VSS
196
A13,NC
237
VSS
38
VSS
77
NC, ODT1
118
VSS
158
DQ30
197
VDD
238
VDDSPD
39
DQ26
78
VDDQ
119
SDA
159
DQ31
198
VSS
239
SA0
40
DQ27
79
VSS
120
SCL
160
VSS
199
DQ36
240
SA1
80
DQ32
200
DQ37
NC= No Connect, RFU= Reserved for Future Use.
Note:
Rev. 0.2 / July 2004
5
HYMP512R72(L)4
FUNCTIONAL BLOCK DIAGRAM
VSS
/RS0
/DQS9
DQS9
/DQS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQS /DQS /CS
I/O0
I/O1
D0
I/O2
I/O3
DM
DQ4
DQ5
DQ6
DQ7
DQS /DQS /CS
I/O0
I/O1
D1
I/O2
I/O3
DM
DQ12
DQ13
DQ14
DQ15
DQS /DQS /CS
I/O0
I/O1
D2
I/O2
I/O3
DM
DQ20
DQ21
DQ22
DQ23
DQS /DQS /CS
I/O0
I/O1
D3
I/O2
I/O3
DM
DQ28
DQ29
DQ30
DQ31
DQS /DQS /CS
I/O0
I/O1
D4
I/O2
I/O3
DM
DQ36
DQ37
DQ38
DQ39
DQS /DQS /CS
I/O0
I/O1
D5
I/O2
I/O3
DM
DQ44
DQ45
DQ46
DQ47
DQS /DQS /CS
I/O0
I/O1
D6
I/O2
I/O3
DM
DQ52
DQ53
DQ54
DQ55
DQS /DQS /CS
I/O0
I/O1
D7
I/O2
I/O3
DM
DQ60
DQ61
DQ62
DQ63
/S0*
BA0 to BA1
A0 to A13
/RAS
/CAS
/WE
CKE0
ODT0
/RESET**
PCK7**
Rev. 0.2 / July 2004
DM
DQS /DQS /CS
I/O0
I/O1
D11
I/O2
I/O3
DM
DQS /DQS /CS
I/O0
I/O1
D12
I/O2
I/O3
DM
DQS /DQS /CS
I/O0
I/O1
D13
I/O2
I/O3
DM
DQS /DQS /CS
I/O0
I/O1
D14
I/O2
I/O3
DM
DQS /DQS /CS
I/O0
I/O1
D15
I/O2
I/O3
DM
DQS /DQS /CS
I/O0
I/O1
D16
I/O2
I/O3
DM
DQS /DQS /CS
I/O0
I/O1
D17
I/O2
I/O3
DM
VDD SPD
Serial
PD
VDD/VDDQ
DO-D17
VREF
DO-D17
VSS
DO-D17
/DQS17
DQS17
/DQS8
DQS8
CB0
CB1
CB2
CB3
A1
SA2
/DQS16
DQS16
/DQS7
DQS7
DQ56
DQ57
DQ58
DQ59
A1
SA1
/DQS15
DQS15
/DQS6
DQS6
DQ48
DQ49
DQ50
DQ51
A0
SA0
/DQS14
DQS14
/DQS5
DQS5
DQ40
DQ41
DQ42
DQ43
DQS /DQS /CS
I/O0
I/O1
D10
I/O2
I/O3
SDA
Serial PD
/DQS13
DQS13
/DQS0
DQS0
DQ32
DQ33
DQ34
DQ35
SCL
WP
/DQS12
DQS12
/DQS3
DQS3
DQ24
DQ25
DQ26
DQ27
SCL
/DQS11
DQS11
/DQS2
DQS2
DQ16
DQ17
DQ18
DQ19
DM
/DQS10
DQS10
/DQS1
DQS1
DQ8
DQ9
DQ10
DQ11
DQS /DQS /CS
I/O0
I/O1
D9
I/O2
I/O3
DQS /DQS /CS
I/O0
I/O1
D8
I/O2
I/O3
1:2
R
E
G
I
S
T
E
R
DM
CB4
CB5
CB6
CB7
CK0
/RS0 to /CS :SDRAMs D0 to D17
RBA0 - RBA1 ==> BA0 - BA1: SDRAMs D0 to D17
/CK0
P
L
L
/RESET
OE
PCK0 to PCK6, PCK8,PCK9 ==> CK: SDRAMs D0 toD17
/PCK0 to /PCK6, /PCK8, /PCK9 ==> /CK: SDRAMs D0 toD17
/RA0 - RA13 ==> A0 to A13: SDRAMs D0 to D17
PCK7 ==> CK: Register
/RRAS ==>/RAS: SDRAMs D0 to D17
/RCAS ==>/CAS: SDRAMs D0 to D17
/PCK7 ==> /CK: Register
/RWE ==>/WE: SDRAMs D0 to D17
RCKE0 ==> CKE0: SDRAMs D0 to D17
RODT0 ==> ODT0: SDRAMs D0 to D17
/RST
Notes:
1. DQ-to-I/O wiring shown as recommanded but may be changed.
2, Unless otherwise noted, resistor value are 22 Ohms +/- 5%.
3. /RS0 and /RS1 alternate between the back and front sides of the DIMM.
/PCK7**
6
HYMP512R72(L)4
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Note
Operating temperature(ambient)
TOPR
0 ~ +55
o
C
1
DRAM Component Case Temperature Range
TCASE
0 ~+95
o
C
2
Operating Humidity(relative)
HOPR
10 to 90
%
1
Storage Temperature
TSTG
-50 ~ +100
o
C
1
Storage Humidity(without condensation)
HSTG
5 to 95
o
C
1
Barometric Pressure(operating & storage)
PBAR
105 to 69
K Pascal
1,3
Note :
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional
operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods
may affect reliablility.
2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9㎲.
For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
3. Up to 9850 ft.
Operating Condtions(AC&DC)
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter
Symbol
Min
Max
Unit
Note
VDD
1.7
1.9
V
VDDQ
1.7
1.9
V
1
Input Reference Voltage
VREF
0.49 x VDDQ
0.51 x VDDQ
V
2
EEPROM Supply Voltage
VDDSPD
1.7
3.6
V
Termination Voltage
VTT
VREF-0.04
VREF+0.04
V
3
Min
Max
Unit
Note
Power Supply Voltage
Note :
1.VDDQ must be less than or equal to VDD.
2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc)
3. VTT of transmitting device must track VREF of receiving device.
Input DC Logic Level
Parameter
Symbol
Input High Voltage
VIH(DC)
VREF + 0.125
VDDQ + 0.3
V
Input Low Voltage
VIL(DC)
-0.30
VREF - 0.125
V
Rev. 0.2 / July 2004
7
HYMP512R72(L)4
Input AC Logic Level
Parameter
Symbol
Min
Max
Unit
AC Input logic High
VIH(AC)
VREF + 0.250
-
V
AC Input logic Low
VIL(AC)
-
VREF - 0.250
V
Note
AC Input Test Conditions
Symbol
Condition
Value
Units
Notes
VREF
Input reference voltage
0.5 * VDDQ
V
1
VSWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
Notes:
1.
2.
3.
Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
The input signal minimum slew rate is to be maintained over the range from VIL(dc) max to VIH(ac) min for rising edges and the
range from VIH(dc) min to VIL(ac) max for falling edges as shown in the below figure.
AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions.
Start of Falling Edge Input Timing
Start of Rising Edge Input Timing
VSWING(MAX)
delta TF
Falling Slew =
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
delta TR
VIH(dc) min - VIL(ac) max
Rising Slew =
delta TF
VIH(ac) min - VIL(dc) max
delta TR
< Figure : AC Input Test Signal Waveform >
Rev. 0.2 / July 2004
8
HYMP512R72(L)4
Differential Input AC logic Level
Symbol
Parameter
VID (ac)
ac differential input voltage
VIX (ac)
ac differential cross point voltage
Min.
Max.
Units
Notes
0.5
VDDQ + 0.6
V
1
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and
UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS
or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V
IL(DC).
VDDQ
VTR
Crossing point
VID
VIX or VOX
VCP
VSSQ
< Differential signal levels >
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS,
LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC)
- V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in
VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
Differential AC output parameters
Symbol
VOX (ac)
Parameter
ac differential cross point voltage
Min.
Max.
Units
Notes
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
Notes:
1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations
in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Rev. 0.2 / July 2004
9
HYMP512R72(L)4
Output Buffer Levels
Output AC Test Conditions
Symbol
Parameter
SSTL_18 Class II
Units
Notes
VOH
Minimum Required Output Pull-up under AC Test Load
VTT + 0.603
V
VOL
Maximum Required Output Pull-down under AC Test Load
VTT - 0.603
V
VOTR
Output Timing Measurement Reference Level
0.5 * VDDQ
V
1
SSTl_18 Class II
Units
Notes
- 13.4
mA
1, 3, 4
13.4
mA
2, 3, 4
1. The VDDQ of the device under test is referenced.
Output DC Current Drive
Symbol
1.
2.
3.
4.
Parameter
IOH(dc)
Output Minimum Source DC Current
IOL(dc)
Output Minimum Sink DC Current
VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280
mV.
VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
The dc value of VREF applied to the receiving device is set to VTT
The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current
capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The
actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define
a convenient driver current for measurement.
OCD defalut characteristics
Description
Parameter
Output impedance
Pull-up and pull-down mismatch
Output slew rate
Min
12.6
Nom
1.5
Unit
Notes
23.4
ohms
4
ohms
1,2,3
-
5
V/ns
1,4,5,6
0
Sout
Max
18
1,2
Note:
1. Absolute Specifications (0°C ≤ TCASE ≤ +95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less
than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current:
VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from vil(ac) to vih(ac).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC.
6. DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins. Output slew rate at 667&800MT/s will be added with
JEDEC process.
Rev. 0.2 / July 2004
10
HYMP512R72(L)4
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Capacitance
CK0, /CK0
CCK
9
13
pF
Input Capacitance
CKE, ODT
CI1
10
15
pF
Input Capacitance
/CS
CI2
10
15
pF
Input Capacitance
Address, /RAS, /CAS, /WE
CI3
10
15
pF
Input Capacitance
DQ,DM,DQS, /DQS
CIO
10
15
pF
Note :
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
IDD Specifications
HYMP512R72(L)4
PC2 3200
PC2 4300
PC2 5300
Symbol
max.
max.
max.
Unit
Operating one bank active-precharge
current
IDD0
2090
2270
2450
mA
Operating one bank active-read-precharge
current
IDD1
2270
2450
2630
mA
Precharge power-down current
IDD2P
704
722
740
mA
Precharge quiet standby current
IDD2Q
1190
1280
1460
mA
Precharge standby current
IDD2N
1280
1370
1550
mA
IDD3P(F)
920
1010
1100
mA
IDD3P(S)
704
722
740
mA
Active Standby Current
IDD3N
1550
1730
1910
mA
Operating burst read current
IDD4R
2990
3170
3440
mA
Operating Current
IDD4W
2990
3170
3440
mA
Burst auto refresh current
IDD5B
1790
1790
1790
mA
IDD6
440
440
440
mA
IDD6(L)
404
404
404
mA
IDD7
4250
4610
4970
mA
Parameter
Note
Active power-down current
Self Refresh Current
Operating bank interleave read current
Rev. 0.2 / July 2004
11
HYMP512R72(L)4
IDD Meauarement Conditions
Symbol
Conditions
Units
IDD0
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus
inputs are SWITCHING
mA
IDD1
Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH
between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
mA
IDD2P
Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2Q
Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2N
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD3P
Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Fast PDN Exit MRS(12) = 0
mA
Slow PDN Exit MRS(12) = 1
mA
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
mA
IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK =
tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD4R
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
mA
IDD5B
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA
IDD6
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
mA
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL
= tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions
mA
Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
Rev. 0.2 / July 2004
12
HYMP512R72(L)4
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed
DDR2-667(Y5)
DDR2-667(Y6)
DDR2-533(C4)
DDR2-533(C5)
DDR2-400(C3)
DDR2-400(C4)
Unit
Bin(CL-tRCD-tRP)
5-5-5
6-6-6
4-4-4
5-5-5
3-3-3
4-4-4
Parameter
min
min
min
min
min
min
CAS Latency
5
6
4
5
3
4
ns
tRCD
15
18
15
18.75
15
20
ns
tRP
15
18
15
18.75
15
20
ns
tRC
55
63
60
63.75
55
65
ns
tRAS
40
45
45
45
40
45
ns
AC Timing Parameters by Speed Grade
DDR2-400
Parameter
DDR2-533
DDR2-667
Symbol
Unit
Min
Max
Min
Max
Min
Max
Note
Data-Out edge to Clock edge Skew
tAC
-600
600
-500
500
-450
450
ps
DQS-Out edge to Clock edge Skew
tDQSCK
-500
500
-500
450
-400
400
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
CK
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
ns
System Clock Cycle Time
tCK
5000
8000
3750
8000
3000
8000
ps
DQ and DM input hold time
tDH
400
-
350
-
300
-
ps
1
DQ and DM input setup time
tDS
400
-
350
-
300
-
ps
1
Control & Address input Pulse Width for each input
tIPW
0.6
-
0.6
-
0.6
-
tCK
DQ and DM input pulse witdth for each input pulse
width for each input
tDIPW
0.35
-
0.35
-
0.35
-
tCK
tHZ
-
tAC max
-
tAC max
-
tAC max
ps
tAC min
tAC max
tAC min
tAC max
tAC min
tAC max
ps
2*tAC min tAC max
ps
Data-out high-impedance window from CK, /CK
DQS low-impedance time from CK/CK
tLZ(DQS)
DQ low-impedance time from CK/CK
tLZ(DQ)
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
-
350
-
300
-
tbd
ps
tQHS
-
450
-
400
-
tbd
ps
DQ hold skew factor
DQ/DQS output hold time from DQS
2*tAC min tAC max
2*tAC min tAC max
tQH
tHP - tQHS
-
tHP - tQHS
-
tHP - tQHS
-
ps
tDQSS
WL - 0.25
WL +
0.25
WL - 0.25
WL +
0.25
WL - 0.25
WL +
0.25
tCK
DQS input high pulse width
tDQSH
0.35
-
0.35
-
0.35
-
tCK
DQS input low pulse width
tDQSL
0.35
-
0.35
-
0.35
-
tCK
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
0.2
-
tCK
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
0.2
-
tCK
Write command to first DQS latching transition
Mode register set command cycle time
tMRD
2
-
2
-
2
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
-
0.35
-
0.35
-
tCK
Rev. 0.2 / July 2004
13
HYMP512R72(L)4
- continued DDR2 400
Parameter
DDR2 533
DDR2 667
Symbol
Address and control input hold time
Address and control input setup time
Unit
Min
Max
Min
Max
Min
Max
tIH
600
-
500
-
tbd
-
ps
tIS
600
-
500
-
tbd
-
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
105
-
105
-
105
-
ns
Row Active to Row Active Delay
tRRD
7.5
-
7.5
-
7.5
-
ns
CAS to CAS command delay
tCCD
2
Write recovery time
tWR
15
-
15
-
15
-
ns
Auto Precharge Write Recovery + Precharge
Time
tDAL
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-
tCK
Write to Read Command Delay
tWTR
10
-
7.5
-
7.5
-
ns
Internal read to precharge command delay
tRTP
7.5
Exit self refresh to a non-read command
tXSNR
tRFC + 10
Exit self refresh to a read command
tXSRD
200
-
200
-
200
-
tCK
tXP
2
-
2
-
2
-
tCK
Exit active power down to read command
tXARD
2
2
2
tCK
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
6 - AL
6 - AL
tCK
CKE
3
3
3
tCK
tAOND
2
2
tAON
tAC(min)
tAC(max)
+1
tAONPD
tAC(min)+2
tAOFD
2.5
2.5
tAC(min)
tAC(max)
+ 0.6
Exit precharge power down to any non-read
command
CKE minimum pulse width
(high and low pulse width)
t
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAOF
ODT turn-off
ODT turn-off (Power-Down mode)
t
AOFPD
2
2
7.5
tCK
7.5
tRFC + 10
ns
tRFC + 10
2
2
tAC(min)
tAC(max)
+1
ns
2
2
tCK
tAC(min)
tAC(max)
+0.7
ns
2tCK+tAC
2tCK+tAC
2tCK+tAC
tAC(min)+2
tAC(min)+2
(max)+1
(max)+1
(max)+1
ns
2.5
2.5
tCK
tAC(min)
tAC(max)
+ 0.6
ns
2.5tCK+t
2.5tCK+t
2.5tCK+t
tAC(min)+
tAC(min)+
tAC(min)+
AC(max)
AC(max)
AC(max)
2
2
2
+1
+1
+1
ns
2.5
tAC(min)
tAC(max)
+ 0.6
ODT to power down entry latency
tANPD
ODT power down exit latency
tAXPD
8
OCD drive mode output delay
tOIT
0
tDelay
tIS+tCK+tI
H
tREFI
-
7.8
-
7.8
-
7.8
us
2
tREFI
-
3.9
-
3.9
-
3.9
us
3
Minimum time clocks remains ON after
CKE asynchronously drops LOW
Average periodic Refresh Interval
3
2.5
3
Note
3
8
12
0
tCK
8
12
tIS+tCK+tI
H
0
tCK
12
tIS+tCK+tI
H
ns
ns
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS12821(L)F).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C < TCASE ≤ 95°C
Rev. 0.2 / July 2004
14
HYMP512R72(L)4
PACKAGE OUTLINE
Front
Side
133.35
4.0 max
R
E
G
I
S
T
E
R
4.0±0.1
30.0
PLL
Detail-A
Detail-B
1.27 ± 0.10
5.175
63.0
5.0
55.0
5.175
17.80
10.0
Back
R
E
G
I
S
T
E
R
3.0
3.0
Detail of Contacts B
2.50
1.0
0.8
3.80
2.50
0.20
± 0.20
Detail of Contacts A
± 0.05
1.50± 0.10
5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 0.2 / July 2004
15
SERIAL PRESENCE DETECT
SPD SPECIFICATION
(128Mx72 Registered DDR2 DIMM)
Rev. 0.2 / July 2004
16
HYMP512R72(L)4
SERIAL PRESENCE DETECT
Byte#
Function Description
0
1
2
3
4
5
6
7
8
Number of bytes utilized by module manufacturer
Total number of Bytes in SPD device
Fundamental memory type
Number of row address on this assembly
Number of column address on this assembly
Number of DIMM ranks
Module data width
Module data width (continued)
Voltage Interface level of this assembly
9
DDR SDRAM cycle time at CL=5
10
DDR SDRAM access time from clock (tAC)
11
12
13
14
15
16
17
18
19
20
21
22
DIMM Configuration type
Refresh Rate and Type
Primary DDR SDRAM width
Error Checking DDR SDRAM data width
Reserved
Burst Lengths Supported
Number of banks on each SDRAM Device
CAS latency supported
Reserved
DIMM Type
DDR SDRAM module attributes
DDR SDRAM device attributes : General
23
DDR SDRAM cycle time at CL=4(tCK)
24
DDR SDRAM access time from clock at CL=4(tAC)
25
DDR SDRAM cycle time at CL=3(tCK)
26
DDR SDRAM access time from clock at CL=3(tAC)
27
Minimum Row Precharge Time(tRP)
28
Minimum Row Activate to Row Active delay(tRRD)
29
Minimum RAS to CAS delay(tRCD)
30
Minimum active to precharge time(tRAS)
31
Module rank density
32
Address and command input setup time before clock (tIS)
33
Address and command input hold time after clock (tIH)
34
Data input setup time before clock (tDS)
35
Data input hold time after clock (tDH)
36
Write recovery time(tWR)
37
Internal write to read command delay(tWTR)
38
39
Internal read to precharge command delay(tRTP)
Memory analysis probe characteristics
40
Extension of byte 41 tRC and byte 42 tRFC
41
Minimum active / auto-refresh time ( tRC)
Rev. 0.2 / July 2004
Bin Sort : E3(DDR2 400 3-3-3), E4(DDR2 400 4-4-4),
C4(DDR2 533 4-4-4), C5(DDR2 533 5-5-5)
Speed
Grade
all
all
all
all
all
all
all
all
all
E3,E4
C4,C5
E3,E4
C4,C5
all
all
all
all
all
all
all
all
all
all
E3,E4,C5
C4
E3,E4,C5
C4
E3,C4
E4,C5
E3,C4
E4,C5
E3, C4
E4
C5
all
E3, C4
E4
C5
E3
E4,C4,C5
all
E3, E4
C4, C5
E3, E4
C4, C5
E3, E4
C4, C5
E3, E4
C4, C5
all
E3, E4
C4, C5
all
E3,E4,C4
C5
E3
C4
E4
C5
Function Supported
Hexa Value
128 Bytes
256 Bytes
DDR2 SDRAM
14
11
30.0 mm/ planar/ 1 rank
72 Bits
SSTL 1.8V
5.0 ns
3.75 ns
+/-0.6ns
+/-0.5ns
ECC
7.8us & Self refresh
x4
x4
4,8
4
3, 4, 5
Regular RDIMM
Normal
Supports weak driver
5.0ns
3.75ns
+/-0.6ns
+/-0.5ns
5.0ns
Undefined
+/-0.6ns
Undefined
15ns
20ns
18.75ns
7.5ns
15ns
20ns
18.75ns
40ns
45ns
1GB
0.6ns
0.5ns
0.6ns
0.5ns
0.40ns
0.35ns
0.40ns
0.35ns
15ns
10ns
7.5ns
7.5ns
Undefined
Undefined
tRC extended
55ns
60ns
65ns
63.75ns
80
08
08
0E
0B
60
48
00
05
50
3D
60
50
02
82
04
04
00
0C
04
38
00
01
00
01
50
3D
60
50
50
00
60
00
3C
50
4B
1E
3C
50
4B
28
2D
01
60
50
60
50
40
35
40
35
3C
28
1E
1E
00
00
50
37
3C
41
3F
Note
1
1
2
2
2
2
2
2
17
HYMP512R72(L)4
- continued Byte#
Function Description
43
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
Maximum cycle time (tCK max)
44
Maximim DQS-DQ skew time(tDQSQ)
45
Maximum read data hold skew factor(tQHS)
46
PLL Relock time
42
47~61
62
63
64
65~71
Function Supported
all
105ns
69
all
E3, E4
C4, C5
E3, E4
C4, C5
8.0ns
0.35ns
0.30ns
0.45ns
0.40ns
15us
Undefined
1.0
Hynix JEDEC ID
Hynix(Korea Area)
HSA(United States Area)
HSE(Europe Area)
HSJ(Japan Area)
Singapore
Asia Area
H
Y
M
P
5
1
2
R
7
2
4
‘-’
E
C
3
4
5
Blank
80
23
1E
2D
28
0F
00
10
4C
D3
C6
AA
AD
00
0*
1*
2*
3*
4*
5*
48
59
4D
50
35
31
32
52
37
32
34
2D
45
43
33
34
35
20
Superset information(may be used in future)
SPD Revision code
Checksum for Bytes 0~62
E3
E4
C4
C5
Manufacturer JEDEC ID Code
--------- Manufacturer JEDEC ID Code
72
Manufacturing location
73
74
75
76
77
78
79
80
81
82
83
84
Manufacture part number(Hynix Memory Module)
-------- Manufacture part number(Hynix Memory Module)
-------- Manufacture part number(Hynix Memory Module)
Manufacture part number (DDR2 SDRAM)
---------Manufacture part number(Memory density)
Manufacture part number(Module Depth)
------- Manufacture part number(Module Depth)
Manufacture part number(Module type)
Manufacture part number(Data width)
-------Manufacture part number(Data width)
Manufacture part number(Component configuration)
Manufacture part number(Hyphen)
85
Manufacture part number(Minimum cycle time)
86
-------Manufacture part number(Minimum cycle time)
87~90
91
92
93
94
95~98
99~127
128~255
Speed
Grade
E3, E4
C4, C5
E3
E4,C4
C5
Manufacture part number(T.B.D)
Manufacture revision code(for Component)
Manufacture revision code (for PCB)
Manufacturing date(Year)
Manufacturing date(Week)
Module serial number
Manufacturer specific data (may be used in future)
Open for customer use
Hexa Value
Note
6
00
00
3
3
4
5
5
Function Supported
Hexa Value
Note
L
4
4C
34
Undefined
Undefined
Note :
1. The bank address is excluded
2. This value is based on the component specification
3. These bytes are programmed by code of date week & date year
4. These bytes apply to Hynix’s own Module Serial Number System
5. These bytes undefined and coded as ‘00h’
6. Refer to Hynix Web Site
Byte 83~84, Low Power Part
Byte #
83
84
Function Description
Manufacture part number(Low power part)
Manufacture part number(Component Configuration)
Rev. 0.2 / July 2004
Speed
Grade
18
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