NSC DAC0890 Dual 8-bit mp-compatible digital-to-analog converter Datasheet

DAC0890
Dual 8-bit mP-Compatible Digital-to-Analog Converter
Y
General Description
Y
The DAC0890 is a complete dual 8-bit voltage output digitalto-analog converter that can operate on a single 5V supply.
It includes on-chip output amplifiers, precision bandgap voltage reference, and full microprocessor interface.
Each DAC0890 output amplifier has two externally selectable output ranges, 0V to 2.55V and 0V to 10.2V. The amplifiers are internally trimmed for offset and full-scale accuracy
and therefore require no external user trims.
The DAC0890 is supplied in 20-pin ceramic DIP package.
Y
Y
Y
Y
Applications
Y
Y
Y
Features
Y
Y
Guaranteed monotonic over temperature
Internal precision bandgap reference
Two calibrated output ranges; 2.55V and 10.2V
2 ms settling time for full-scale output change
No external trims
Microprocessor interface
Y
Industrial processing controls
Automotive controls
Disk drive motor controls
Automatic test equipment
Two 8-bit voltage output DACs
4.75V to 16.5V single operation
Block Diagram
TL/H/10592 – 1
Ordering Information
Industrial (b40§ C s TA s a 85§ C)
DAC0890CIJ
Connection Diagram
Package
Dual-In-Line Package
J20A Cerdip
TL/H/10592 – 2
Top View
C1995 National Semiconductor Corporation
TL/H/10592
RRD-B30M115/Printed in U. S. A.
DAC0890 Dual 8-bit mP-Compatible Digital-to-Analog Converter
May 1995
Absolute Maximum Ratings (Notes 1 & 2)
Soldering Information
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Positive Supply Voltage (V a )
Voltage at Any Pin (Note 3)
Input Current at Any Pin (Note 3)
Package Input Current (Note 4)
Power Dissipation (Note 5)
ESD Susceptability (Note 6)
Output Short-Circuit Protection
Duration
20V
GND b0.3 to V a a 0.3V
5 mA
20 mA
1.0W
2000V
J package (10 sec.)
300§ C
Storage Temperature
Junction Temperature
b 65§ C to 150§ C
(Note 5)
Operating Ratings (Notes 1 & 2)
Temperature Range
TMIN s TA s TMAX
DAC0890CIJ
Positive Supply Voltage, V a
b 40§ C s TA s a 85§ C
4.75 to 16.5V
Indefinite
Electrical Characteristics The following specifications apply for V a e a 5V and V a e a 15V and AGND e
DGND e 0V, unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C.
Symbol
Typical
(Note 7)
Limit
(Note 8)
Units
Resolution
8
Bits(min)
Monotonicity
8
Bit(min)
Parameter
Conditions
Integral Linearity Error
g 0.5
LSB(min)
Fullscale Error
g 0.16
g 1.5/ g 2.5
LSB(max)
Zero Error
g 1.0/ g 2.0
LSB(max)
Full Scale DAC-to-DAC
Tracking (Note 9)
g 0.25
LSB
b 74
b 66
dB
dB
Glitch Energy
(Note 11)
45
V-ns
Digital Feedthrough
(Note 12)
60
V-ns
2
3
ms
ms
Analog Crosstalk
(Note 10)
Va e
Va e
15V, 10.2V range
5V, 2.55V range
tS
Positive Output Settling
Time (Note 13)
CLOAD s 500 pF
CLOAD s 1000 pF
IO
Output Current Drive
Capability
(Note 14)
ISC
Output Short Circuit
Current (Note 15)
Va e
PSRR
Power Supply Rejection
Ratio
(Note 16)
f k 30 Hz
10.2V range
13.5V s V a s16.5V
7
15
ppm/% (max)
2.55V range
13.5V s V a s 16.5V
4.75V s V a s 5.25V
4.75V s V a s 16.5V
4
4
4
59
20
ppm/% (max)
ppm/% (max)
ppm/%
All Inputs Low
V a e 16.5
V a e 4.75
25
23
30/35
mA (max)
mA
IS
Supply Current
8
15V
5/3.5
20
mA(min)
mA
VILD
Data Logic Low Threshold
0.8
V (max)
VIHD
Data Logic High Threshold
2.0
V (min)
VILC
Control Logic Low
Threshold
0.8
V (max)
2
Electrical Characteristics (Continued)
The following specifications apply for V a e a 5V and V a e a 15V and AGND e DGND e 0V, unless otherwise specified.
Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C.
Symbol
VIHC
Parameter
Conditions
Typical
(Note 7)
Control Logic High
Threshold
Digital Input Current
(Note 17)
Limit
(Note 8)
Units
2.2
V (min)
2.2
25
mA (max)
tWR
Write Time
18
40
ns (min)
tDS
Data Setup Time
18
35
ns (min)
tDH
Data Hold Time
3
tCS
Control Setup Time
18
tCH
Control Hold Time
ns (max)
40
ns (min)
0
ns (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits.
For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to AGND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k AGND or VIN l V a ) the absolute value of current at that pin should be
limited to 5 mA or less.
Note 4: The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mA.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, iJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD e (TJMAX - TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. The
TJMAX(§ C) and iJA(§ C/W) for the DAC0890CIJ are 125§ C and 53§ C/W, respectively.
Part Number
TJMAX(§ C)
iJA(§ C/W)
DAC0890CIJ
125
53
Note 6: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 7: Typicals are at 25§ C, unless otherwise specified, and represent the most likely parametric norm.
Note 8: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Full Scale DAC-to-DAC Tracking is defined as the change in the voltage difference between the full scale output levels of DAC1 and DAC2. The result is
expressed in LSBs and it referred to the full-scale voltage difference at 25§ C.
Note 10: Analog Crosstalk is a measure of the change in one DAC’s full scale output voltage as the second DAC’s output voltage changes value. It is measured as
the voltage change in one DAC’s full scale output voltage divided by the voltage range through which the second DAC’s output has changed (zero to full scale).
This ratio is then expressed in dB.
Note 11: Glitch Energy is a worst case measurement, over the entire input code range, of transients that occur when changing code. The positive and negative
areas of the transient waveforms are summed together to obtain the value listed.
Note 12: Digital Feedthrough is measured with both DAC outputs latched at full scale and a 2 ns, 5V step applied to all 8 data inputs. This gives the worst case
digital feedthrough for the DAC0890.
Note 13: Settling Time is specified for a positive full scale step to g (/2 LSB. Settling time for negative steps will be slower but may be improved with an external
pull-down resistor. Negative settling time to g (/2 LSB can be calculated for each range where tS e 6.23 (CLOAD) (RLOAD/10 kX) for the high range and tS e 6.23
(CLOAD) (RLOAD/2.5 kX) for the low range.
Note 14: Output Current Drive Capability is the minimum current that can be sourced by the output amplifiers with less than (/2 LSB reduction in full scale. Current
sinking capability is provided by a passive internal resistance of 10 kX in the high range and 2.5 kX in the low range.
Note 15: Output Short Circuit Current is measured with the output at full-scale and shorted to AGND.
Note 16: Power Supply Rejection Ratio is a measure of how much the output voltage changes (in parts-per-million) per change (in percent) in the power supply
voltage.
Note 17: Digital Input Current is measured with 0V and V a input levels. The limit specified is the higher of these two measurements.
3
Typical Performance Characteristics
Fullscale Drift
vs Temperature
Offset Drift
vs Temperature
Integral Linearity
vs Temperature
Fullscale Dac to Dac
Tracking
vs Temperature
Analog Crosstalk
vs Temperature
Power Supply Rejection
vs Temperature
Write Time
vs Temperature
Data Threshold
vs Temperature
Control Threshold
vs Temperature
TL/H/10592 – 3
4
Typical Performance Characteristics
Supply Current
vs Temperature
Short Circuit Current
vs Temperature
Digital Input Current
vs Temperature
Minimum Supply Voltage
vs Temperature
(10.2V Range)
Minimum Supply Voltage
vs Temperature
(2.55V Range)
Max Power Dissipation
vs Temperature
Power Supply Rejection
vs Frequency
TL/H/10592 – 4
5
Timing Waveforms
TL/H/10592 – 5
6
Connection Diagram
Dual-In-Line Package
TL/H/10592 – 2
Pin Description
VOUT2 (14)
DB0 – DB7 (1–8) These pins are data inputs for each of the
internal 8-bit DACs. DB0 is the least-significant-bit.
WR (9)
This is the WRITE command input pin.
This input is used in conjunction with CS1
and CS2 to write data into either of the
internal DACs. The data is latched into a
selected DAC with the rising edge of either WR or CS1 for DAC1 or CS2 for
DAC2, whichever occurs first.
CS1 (10)
This is the input pin used to select DAC1.
This input is used in conjunction with the
WR input to write data into either of the
internal DACs. The data is latched into
DAC1 with the rising edge of either CS1 or
WR, whichever occurs first.
This is the input pin used to select DAC2.
CS2 (11)
This input is used in conjunction with the
WR input to write data into either of the
internal DACs. The data is latched into
DAC2 with the rising edge of either CS2 or
WR, whichever occurs first.
DGND (12)
The system digital ground is connected to
this pin. For proper operation, this and
AGND must be connected together.
SENSE 2 (13)
DAC2’s output sense connection. When
this pin is connected to the VOUT2’s load
impedance, the feedback loop will compensate for any voltage drops between
the VOUT2 pin and the load.
SELECT 2 (15)
AGND (16)
SELECT 1 (17)
VOUT1 (18)
SENSE 1 (19)
V a (20)
7
DAC2’s voltage output connection. It provides two full-scale output voltage ranges,
2.55V and 10.2V.
The two output voltage ranges available
from DAC2 are selected by connecting
this pin to SENSE2 for the 2.55V full-scale
range and leaving it unconnected for the
10.2V full-scale range.
The system digital ground is connected to
this pin. For proper operation, this and
DGND must be connected together.
The two output voltage ranges available
from DAC1 are selected by connecting
this pin to SENSE1 for he 2.55V full-scale
range and leaving it unconnected for the
10.2V full-scale range.
DAC1’s voltage output connection. It provides two full-scale output voltage ranges,
2.55V and 10.2V.
DAC1’s output sense connection. When
this pin is connected to the VOUT1’s load
impedance, the feedback loop will compensate for any voltage drops between
the VOUT1 pin and the load.
The power supply voltage, ranging from
4.75V to 16.5V, is applied to this pin. It
should be bypassed, to AGND, with a 0.01
E 0.1 mF ceramic capacitor in parallel
with a 2.2 E 22 mF electrolytic capacitor.
Functional Description
externally set through the range select pin. The two ranges
are 0V to 2.55V and 0V to 10.2V. The internal resistors that
set the gain are matched to the unit resistor of the R/2R
ladder. This ensures that these resistors match over process variations and temperature. This greatly reduces gain
variations that would exist if external gain setting resistors
were used.
An internal band-gap reference and its control amplifier generate a full scale reference voltage for the DACs. It produces a 1.2V output from a single supply.
The DAC0890 provides a TTL and CMOS-compatible control interface and allows writing and latching digital values to
each of the internal DACs.
The DAC0890 is a monolithic dual 8-bit bipolar Digital-to-Analog converter comprising six major functional blocks designed to operate on a single supply as low as 5V ( g 5%).
These include two latch/DAC combinations, two high-speed
output amplifiers, band-gap reference, and control/interface
logic.
The two internal 8-bit DACs use equal valued current sources. Controlled by a corresponding bit in the input data, each
current source’s output is switched into either an R/2R ladder or AGND. Each internal DAC has an 8-bit latch to store
a digital input. See Figure 1 .
The high-speed output amplifiers operate in the non-inverting mode. The R-2R’s output current is applied to the output
amplifier and converted to a voltage. The amplifier’s gain is
TL/H/10592 – 7
FIGURE 1. Simplified Internal Schematic (One DAC Shown)
8
Applications Information
Grounding and Power Supply
Bypassing
Full-Scale Output Voltage Range Selection
The DAC0890 has been designed for ease of use. All reference voltage and output amplifier connections are internal.
All trims such as full-scale (gain) and zero (offset) are performed during manufacturing. Therefore, no external trimming is required to achieve the specified accuracy. The only
external connections required select the desired full-scale
output voltage range.
The two full-scale output voltage ranges are selected by
connecting SENSE, SELECT and VOUT as shown in Figure
2a , b . The 2.55V range can be used with supply voltages as
low as 4.75V. The 10.2V range can be selected with supplies as low as 12.0V.
Proper grounding is essential to extract all the precision and
full rated performance that the DAC0890 is capable of delivering. Typical applications for the DAC0890 include operation with a microprocessor. In this environment digital noise
is prevalent and anticipated. Therefore, special care must
be taken to ensure that proper operation will be achieved.
The DAC0890 uses two ground pins, AGND and DGND, to
minimize ground drops and noise in the analog signal paths.
Figure 3 details the proper bypassing and ground connections.
The DAC0890’s best performance can be ensured by connecting 0.01 mF to 0.1 mF ceramic capacitor in parallel with
an electrolytic of 2.2 mF to 22 mF between the V a pin and
AGND.
Sense Inputs
The SENSE inputs (pins 13 and 19) allow compensation for
voltage drops in long output lines to remote loads. This
places the drops in the internal amplifier’s feedback loop.
An example of this is shown in Figure 3 . The I-R drop, which
might be caused by printed circuit board traces or long cables, between the VOUT2 and the load impedance RL is
placed inside the feedback loop if SENSE1 is connected
directly to the load. This forces the voltage at the load to be
the correct value. It is important to remember that the voltage at the DAC0890’s VOUT pins may become higher than
the full-scale output voltage selected using the SELECT
pins. Therefore, the power supply voltage applied to V a
must be t2.2V above the resulting output voltage (at pins
14 and 18) when the SENSE inputs are used.
The SENSE inputs have a finite input impedance. The
range-setting resistors load the output with 2.5 kX when the
0V to 2.55V range is selected and 10 kX when the 0V to
10.2V range is selected.
TL/H/10592 – 8
FIGURE 2a. 0V to 2.55V Output Voltage Range
TL/H/10592 – 9
FIGURE 2b. 0V to 10.2V Output Voltage Range
Power Supply Voltage
The DAC0890 is designed to operate on a single power
supply voltages a 4.75V and a 16.5V. For 2.55V full-scale
operation the power supply voltage can be as low as
a 4.75V. When the 10.2V full-scale is used the supply voltage needs to be between a 12V to a 16.5V.
TL/H/10592 – 10
FIGURE 3. Typical Connection Showing Power Supply
Bypassing, and the Use of SENSE Inputs
9
is offset and scaled to achieve a b1.27V to a 1.28V output
range with the addition of a b5V supply. The required offset
is generated with an LM385 – 1.2V reference. The external
output amplification is provided by the LMC660. The output
voltage is generated with a complementary binary offset input code.
Minimizing Settling Time
The DAC0890’s output stage uses a passive pull-down resistor to achieve single supply operation and an output voltage range that includes ground. This results in a negativegoing settling time that is longer than the settling time or
positive-going signals. The actual settling time is dependant
on the load resistance and capacitance. If available, a negative power supply can be used to improve the negative settling time by connecting a pull down resistor between the
output and the negative supply. The resistor’s value is chosen so that the current through the pull down resistor is not
greater than 0.5 mA when the output voltage is 0V. See
Figure 4 .
Microprocessor Interface
When interfacing with a microprocessor, the DAC0890 appears as a two byte write-only memory location for memory
mapped and I/O mapped input-output. Each of the internal
DACs is chosen through one of the two chips selects, CS1
or CS2. The action of the control signals is detailed in Table
I. The data is latched on the rising edge of either Chip Select or WR, whichever occurs first for a given selected DAC.
For interfacing ease, WR can be tied low and CS1 or CS2
can be used to latch the data. Both DACs can be updated
simultaneously by pulling both CS1 and CS2 low. Further
versatility is provided by the ability of WR and CS1 and/or
CS2 to be tied together.
TABLE I. DAC0890 Control Logic Truth Table
Input
Data
0
1
0
1
0
1
X
X
X
TL/H/10592–11
FIGURE 4. Improving Negative Slew Rate
Bipolar Operation
While the DAC0890 was designed to operate on a single
positive supply voltage and generate a unipolar output voltage, bipolar operation is still possible if a negative supply is
available or added. As shown in Figure 5 , the output voltage
WR
CS
DAC Data
Latch
Condition
0
0
0
0
0
0
0
1
0
1
0
1
previous data
previous data
previous data
‘‘transparent’’
‘‘transparent’’
latching
latching
latching
latching
latching
latching
latching
u
u
0
0
1
X
1
u
u
X
1
1
TL/H/10592 – 12
FIGURE 5. Bipolar Operation
10
11
DAC0890 Dual 8-bit mP-Compatible Digital-to-Analog Converter
Physical Dimensions inches (millimeters)
Cerdip Dual-In-Line Package (J)
Order Number DAC0890CIJ
NS Package Number J20A
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