BSI BS616LV2012DI Very low power/voltage cmos sram 128k x 16 bit Datasheet

BSI
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BS616LV2012
„ DESCRIPTION
„ FEATURES
• Very low operation voltage : 2.7 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V
C-grade: 30mA (Max.) operating current
I -grade: 35mA (Max.) operating current
0.15uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
-10
100ns (Max.) at Vcc = 3.0V
•Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV2012 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.15uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
The BS616LV2012 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2012 is available in DICE form, JEDEC standard
48-pin TSOP Type I package and 48-pin BGA type.
„ PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
POWER DISSIPATION
STANDBY
Operating
SPEED
(ns)
( ICCSB1, Max )
( ICC , Max )
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
BS616LV2012DC
PKG TYPE
DICE
O
BS616LV2012TC
O
+0 C to +70 C
2.7V ~ 3.6V
70 / 100
8uA
30mA
TSOP1-48
BGA-48-0608
BS616LV2012AC
BS616LV2012DI
DICE
BS616LV2012TI
-40 O C to +85 O C
2.7V ~ 3.6V
70 / 100
12uA
35mA
BS616LV2012AI
TSOP1-48
BGA-48-0608
„ PIN CONFIGURATIONS
„ BLOCK DIAGRAM
A8
A13
1
A
LB
2
OE
3
A0
4
A1
5
A2
A15
6
Address
A16
A14
Input
A12
N.C.
Buffer
A7
B
D8
UB
A3
A4
CE
D0
C
D9
D10
A5
A6
D1
D2
D
VSS
D11
N.C.
A7
D3
VCC
E
VCC
D12
N.C.
A16
D4
VSS
F
D14
D13
A14
A15
D5
D6
G
D15
N.C.
A12
A13
WE
D7
H
N.C.
A8
A9
A10
A11
N.C.
20
1024
Row
Memory Array
Decoder
1024 x 2048
A6
A5
A4
2048
16
DQ0
.
.
.
.
.
.
.
.
Data
Input
Buffer
16
Column I/O
Write Driver
Sense Amp
16
Data
Output
Buffer
DQ15
16
128
Column Decoder
14
CE
WE
OE
UB
LB
Control
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
Vcc
Gnd
48-ball BGA top view
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV2012
1
Revision 2.4
April 2002
BSI
BS616LV2012
„ PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE Chip Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
„ TRUTH TABLE
MODE
CE
WE
OE
LB
UB
DQ0~DQ7
DQ8~DQ15
Vcc CURRENT
Not selected
(Power Down)
H
X
X
X
X
High Z
High Z
ICCSB, ICCSB1
Output Disabled
L
H
H
X
X
High Z
High Z
ICC
L
L
Dout
Dout
ICC
Read
L
H
L
H
L
High Z
Dout
ICC
L
H
Dout
High Z
ICC
L
L
Din
Din
ICC
Write
R0201-BS616LV2012
L
L
X
H
L
X
Din
ICC
L
H
Din
X
ICC
2
Revision 2.4
April 2002
BSI
BS616LV2012
„ ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
V TERM
PARAMETER
Terminal Voltage with
Respect to GND
RATING
-0.5 to
Vcc+0.5
„ OPERATING RANGE
UNITS
RANGE
AMBIENT
TEMPERATURE
Vcc
V
Commercial
0 O C to +70 O C
2.7V ~ 3.6V
T BIAS
Temperature Under Bias
-40 to +125
O
T STG
Storage Temperature
-60 to +150
O
PT
Power Dissipation
1.0
W
I OUT
DC Output Current
20
mA
C
C
O
Industrial
O
-40 C to +85 C
2.7V ~ 3.6V
„ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
CIN
CDQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V
6
pF
VI/O=0V
8
pF
1. This parameter is guaranteed and not tested.
„ DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP. (1) MAX.
UNITS
IIL
Guaranteed Input Low
Voltage(2)
Guaranteed Input High
Voltage(2)
Input Leakage Current
IOL
Output Leakage Current
Vcc = Max, CE = VIH, or OE = VIH,
VI/O = 0V to Vcc
VOL
Output Low Voltage
Vcc = Max, IOL = 2mA
Vcc=3.0V
--
--
0.4
V
VOH
Output High Voltage
Vcc = Min, IOH = -1mA
Vcc=3.0V
2.4
--
--
V
ICC
Operating Power Supply
Current
CE = VIL, IDQ = 0mA, F = Fmax(3)
Vcc=3.0V
--
--
30
mA
ICCSB
Standby Current-TTL
CE = VIH, IDQ = 0mA
Vcc=3.0V
--
--
1
mA
ICCSB1
Standby Current-CMOS
CE Њ Vcc-0.2V,
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
Vcc=3.0V
--
0.15
8
uA
VIL
VIH
Vcc=3.0V
-0.5
--
0.8
V
Vcc=3.0V
2.0
--
Vcc+0.2
V
Vcc = Max, VIN = 0V to Vcc
--
--
1
uA
--
--
1
uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
„ DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
VDR
Vcc for Data Retention
CE Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
1.5
--
--
V
ICCDR
Data Retention Current
CE Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
--
0.1
5
uA
tCDR
Chip Deselect to Data
Retention Time
0
--
--
ns
TRC (2)
--
--
ns
tR
See Retention Waveform
Operation Recovery Time
25OC
1. Vcc = 1.5V, TA = +
2. tRC = Read Cycle Time
R0201-BS616LV2012
3
Revision 2.4
April 2002
BSI
BS616LV2012
„ LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
Vcc
VDR ≥ 1.5V
Vcc
Vcc
tR
t CDR
CE ≥ Vcc - 0.2V
VIH
CE
„ KEY TO SWITCHING WAVEFORMS
„ AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
WAVEFORM
0.5Vcc
„ AC TEST LOADS AND WAVEFORMS
1269 Ω
3.3V
VIH
3.3V
OUTPUT
1269 Ω
OUTPUT
100PF
INCLUDING
JIG AND
SCOPE
5PF
INCLUDING
JIG AND
SCOPE
1404 Ω
FIGURE 1B
THEVENIN EQUIVALENT
667 Ω
OUTPUT
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
1404 Ω
FIGURE 1A
INPUTS
DON T CARE:
ANY CHANGE
PERMITTED
CHANGE :
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
1.73V
ALL INPUT PULSES
Vcc
GND
90% 90%
10%
→
←
→
10%
← 5ns
FIGURE 2
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
tAVAX
tAVQV
tELQV
tBA
tGLQV
t E1LQX
tBE
tGLQX
tEHQZ
tBDO
tGHQZ
tRC
tAA
tACS
tBA(1)
tOE
tCLZ
tBE
tOLZ
tCHZ
tBDO
tOHZ
tAXOX
tOH
BS616LV2012-70
MIN. TYP. MAX.
DESCRIPTION
70
Read Cycle Time
Data Byte Control Access Time
Data Byte Control to Output Low Z
--
--
ns
--
--
70
--
--
100
ns
--
70
--
--
100
ns
(LB,UB)
--
--
35
--
--
50
ns
--
--
35
--
--
50
ns
(CE)
10
--
--
15
--
--
ns
(LB,UB)
10
--
--
15
--
--
ns
10
--
--
15
--
--
ns
(CE)
0
--
35
0
--
40
ns
(LB,UB)
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
100
--
Output Enable to Output Valid
Chip Select to Output Low Z
--
UNIT
(CE)
Address Access Time
Chip Select Access Time
--
BS616LV2012-10
MIN. TYP. MAX.
0
--
35
0
--
40
ns
Output Disable to Output in High Z
0
--
30
0
--
35
ns
Output Disable to Address Change
10
--
--
15
--
--
ns
Data Byte Control to Output High Z
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; .tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle.
R0201-BS616LV2012
4
Revision 2.4
April 2002
BSI
BS616LV2012
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t RC
ADDRESS
t
t
t OH
AA
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t ACS
t BA
LB,UB
t BE
D OUT
t
t BDO
(5)
CLZ
t
(5)
CHZ
READ CYCLE3 (1,4)
t RC
ADDRESS
t
AA
OE
t OH
t OE
t OLZ
CE
(5)
t CLZ
t
t OHZ (5)
t CHZ(1,5)
ACS
t BA
LB,UB
t BE
t BDO
D OUT
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS616LV2012
5
Revision 2.4
April 2002
BSI
BS616LV2012
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
t AVAX
t E1LWH
t AVWL
t AVWH
t WLWH
t WHAX
t BW
t WLQZ
t DVWH
t WHDX
t GHQZ
t WC
t CW
t AS
t AW
t WP
t WR
t BW (1)
t WHZ
t DW
t DH
t OHZ
t WHOX
t OW
BS616LV2012-70
MIN. TYP. MAX.
DESCRIPTION
BS616LV2012-10
MIN. TYP. MAX.
UNIT
Write Cycle Time
70
--
--
100
--
--
ns
Chip Select to End of Write
70
--
--
100
--
--
ns
0
--
--
0
--
--
ns
Address Valid to End of Write
70
--
--
100
--
--
ns
Write Pulse Width
35
--
--
50
--
--
ns
(CE,WE)
0
--
--
0
--
--
ns
(LB,UB)
30
--
--
40
--
--
ns
Address Setup Time
Write recovery Time
Date Byte Control to End of Write
0
--
30
0
--
40
ns
Data to Write Time Overlap
30
--
--
40
--
--
ns
Data Hold from Write Time
0
--
--
0
--
--
ns
Output Disable to Output in High Z
0
--
30
0
--
40
ns
End of Write to Output Active
5
--
--
10
--
--
ns
Write to Output in High Z
NOTE :
1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle.
„ SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t WC
ADDRESS
(3)
t WR
OE
(11)
t CW
(5)
CE
t BW
LB,UB
t AW
WE
(3)
t WP
t AS
(2)
(4,10)
t OHZ
D OUT
t
DH
t DW
D IN
R0201-BS616LV2012
6
Revision 2.4
April 2002
BSI
BS616LV2012
WRITE CYCLE2 (1,6)
t WC
ADDRESS
(11)
t CW
(5)
CE
t BW
LB,UB
t AW
WE
t WR
t WP
(3)
(2)
t
t AS
DH
(4,10)
t WHZ
D OUT
(7)
(8)
t DW
t
DH
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
R0201-BS616LV2012
7
Revision 2.4
April 2002
BSI
BS616LV2012
„ ORDERING INFORMATION
BS616LV2012
X X
-- Y Y
SPEED
70: 70ns
10: 100ns
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
T: TSOP 1
A: BGA - 48 PIN(6x8mm)
D: DICE
„ PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
1.4 Max.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
E1
e
D1
VIEW A
48 mini-BGA (6 x 8)
R0201-BS616LV2012
8
Revision 2.4
April 2002
BSI
BS616LV2012
„ PACKAGE DIMENSIONS
48
24
25
b
E
1
UNIT
SYMBOL
12̓(2X)
CL
e
12̓(2X)
HD
Seating Plane
12̓(2x)
y
"A"
MM
1.10̈́0.10
0.10̈́0.05
1.00̈́0.05
0.22̈́0.05
0.20̈́0.03
0.10 ~ 0.21
0.10 ~ 0.16
16.40̈́0.10
12.00̈́0.10
0.50̈́0.10
18.00̈́0.20
0.60̈́0.15
0.80̈́0.10
0.1 Max.
0̓~ 8̓
A2
A
D
INCH
A
0.0433̈́0.004
A1 0.004̈́0.002
A2 0.039̈́0.002
0.009̈́0.002
b
b1 0.008̈́0.001
0.004 ~ 0.008
c
c1 0.004 ~ 0.006
D
0.645̈́0.004
0.472̈́0.004
E
e
0.020̈́0.004
HD 0.708̈́0.008
L
0.0236̈́0.006
L1 0.0315̈́0.004
y
0.004 Max.
Ӱ
0̓~ 8̓
GAUGE PLANE
25
24
0
SEATING PLANE
A
12̓(2x)
b
WITH PLATING
"A" DETAIL VIEW
0.254
A1
A
L
L1
c c1
b1
BASE METAL
SECTION A-A
48
1
TSOP1-48PIN
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
/WE
CE2
NC
/UB
/LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
9
10
13
48
47
46
Pkg Type :
48TSOP(I)-12x18mm
37
16
17
27
24
R0201-BS616LV2012
25
9
A16
NC
VSS
IO15
IO7
IO14
IO6
IO13
IO5
IO12
IO4
VCC
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
/OE
VSS
/CE
A0
Revision 2.4
April 2002
BSI
BS616LV2012
REVISION HISTORY
Revision
Description
Date
2.2
2001 Data Sheet release
Apr. 15, 2001
2.3
Modify CSP Pin Configuration Sep.12, 2001
Pin number : E3
“ VSS ” rename to “ N.C. “
Modify some AC parameters
April,12,2002
2.4
R0201-BS616LV2012
10
Note
Revision 2.4
April 2002
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