STMicroelectronics M48Z2M1YPL 16 mb 2mb x 8 zeropower sram Datasheet

M48Z2M1
M48Z2M1Y
16 Mb (2Mb x 8) ZEROPOWER® SRAM
INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERIES
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
10 YEARS of DATA RETENTION in the
ABSENCE of POWER
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z2M1: 4.5V ≤ VPFD ≤ 4.75V
– M48Z2M1Y: 4.2V ≤ VPFD ≤ 4.50V
BATTERIES ARE INTERNALLY ISOLATED
UNTIL POWER IS APPLIED
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2Mb x 8 SRAMs
36
1
PMLDIP36 (PL)
Module
Figure 1. Logic Diagram
DESCRIPTION
The M48Z2M1/2M1Y ZEROPOWER® RAM is a
non-volatile 16,777,216 bit Static RAM organized
as 2,097,152 words by 8 bits. The device combines
two internal lithium batteries, CMOS SRAMs and a
control circuit in a plastic 36 pin DIP long Module.
The ZEROPOWER RAM replaces industry standard SRAMs. It provides the nonvolatility of PROMs
without any requirement for special write timing or
limitations on the number of writes that can be
performed.
VCC
21
A0-A20
W
Table 1. Signal Names
A0-A20
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
8
DQ0-DQ7
M48Z2M1
M48Z2M1Y
E
G
VSS
January 1998
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
AI02048
1/12
M48Z2M1, M48Z2M1Y
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
0 to 70
°C
TSTG
Storage Temperature (VCC Off)
–40 to 85
°C
TBIAS
Temperature Under Bias
–40 to 85
°C
TSLD
(2)
Lead Soldering Temperature for 10 seconds
260
°C
VIO
Input or Output Voltages
–0.3 to 7
V
VCC
Supply Voltage
–0.3 to 7
V
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Mode
VCC
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
Write
Read
Read
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO
X
X
X
High Z
Battery Back-up Mode
Notes: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Figure 2. DIP Pin Connections
NC
A20
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
36
1
35
2
34
3
33
4
32
5
31
6
30
7
29
8
M48Z2M1
9 M48Z2M1Y 28
27
10
26
11
25
12
24
13
23
14
22
15
21
16
20
17
19
18
AI02049
Warning: NC = Not Connected.
2/12
VCC
A19
NC
A15
A17
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
DESCRIPTION (cont’d)
The M48Z2M1/2M1Y has its own Power-fail Detect
Circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system operations brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
batteries which sustain data until valid power returns.
READ MODE
The M48Z2M1/2M1Y is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable)
is low. The device architecture allows ripplethrough access of data from eight of 16,777,216
locations in the static storage array. Thus, the
unique address specified by the 21 Address Inputs
defines which one of the 2,097,152 bytes of data is
to be accessed. Valid data will be available at the
Data I/O pins within Address Access time (tAVQV)
after the last address input signal is stable, providing that the E (Chip Enable) and G (Output Enable)
access times are also satisfied. If the E and G
access times are not met, valid data will be avail-
M48Z2M1, M48Z2M1Y
Figure 3. Block Diagram
VCC
A0-A20
POWER
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
DQ0-DQ7
2048K x 8
SRAM ARRAY
E
W
G
INTERNAL
BATTERIES
VSS
able after the later of Chip Enable Access time
(tELQV) or Output Enable Access Time (tGLQV). The
state of the eight three-state Data I/O signals is
controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain low, output
data will remain valid for Output Data Hold time
(tAXQX) but will go indeterminate until the next Address Access.
AI02050
Table 4. AC Measurement Conditions
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
WRITE MODE
The M48Z2M1/2M1Y is in the Write Mode whenever W and E are active. The start of a write is
referenced from the latter occurring falling edge of
W or E. A write is terminated by the earlier rising
edge of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for minimum of tEHAX
from E or tWHAX from W prior to the initiation of
another read or write cycle. Data-in must be valid
tDVEH or tDVWH prior to the end of write and remain
valid for tEHDX or tWHDX afterward. G should be kept
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs
tWLQZ after W falls.
5V
1.9kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
CL includes JIG capacitance
CL = 100pF or 5pF
AI01030
3/12
M48Z2M1, M48Z2M1Y
Table 5. Capacitance (1, 2)
(TA = 25 °C, f = 1 MHz )
Symbol
CIN
CIO
(3)
Parameter
Test Condition
Input Capacitance
Input / Output Capacitance
Min
Max
Unit
VIN = 0V
40
pF
VOUT = 0V
40
pF
Notes: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected
Table 6. DC Characteristics
(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
ILI
(1)
Input Leakage Current
ILO
(1)
Output Leakage Current
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±4
µA
0V ≤ VOUT ≤ VCC
±4
µA
E = VIL, Outputs open
140
mA
E = VIH
10
mA
E ≥ VCC – 0.2V
8
mA
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
VIL
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
2.4
V
Note: 1. Outputs deselected.
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA = 0 to 70°C)
Symbol
Parameter
Typ
Max
Unit
VPFD
Power-fail Deselect Voltage (M48Z2M1)
4.5
4.6
4.75
V
VPFD
Power-fail Deselect Voltage (M48Z2M1Y)
4.2
4.3
4.5
V
VSO
Battery Back-up Switchover Voltage
tDR
(2)
Data Retention Time
Notes: 1. All voltages referenced to VSS.
2. At 25°C
4/12
Min
3
10
V
YEARS
M48Z2M1, M48Z2M1Y
Table 8. Power Down/Up Mode AC Characteristics
(TA = 0 to 70°C)
Symbol
tF (1)
Parameter
Min
Max
Unit
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
VPFD (min) to VSO VCC Fall Time
10
µs
Write Protect Time from VCC = VPFD
40
tR
VSO to VPFD (max) VCC Rise Time
0
tER
E Recovery Time
40
tFB
(2)
tWP
µs
150
µs
120
ms
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tDR
tR
tFB
tER
tWP
E
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01031
5/12
M48Z2M1, M48Z2M1Y
Table 9. Read Mode AC Characteristics
(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z2M1 / M48Z2M1Y
Symbol
Parameter
Min
tAVAV
tAVQV
(1)
tELQV (1)
Unit
-70
Read Cycle Time
Max
70
ns
Address Valid to Output Valid
70
ns
Chip Enable Low to Output Valid
70
ns
tGLQV
(1)
Output Enable Low to Output Valid
35
ns
tELQX
(2)
Chip Enable Low to Output Transition
5
ns
tGLQX
(2)
Output Enable Low to Output Transition
5
ns
tEHQZ (2)
Chip Enable High to Output Hi-Z
30
ns
tGHQZ
(2)
Output Enable High to Output Hi-Z
25
ns
tAXQX
(1)
Address Transition to Output Transition
5
ns
Notes: 1. CL = 100pF (see Figure 4).
2. CL = 5pF (see Figure 4)
Figure 6. Address Controlled, Read Mode AC Waveforms
A0-A20
tAVAV
tAVQV
DQ0-DQ7
tAXQX
DATA VALID
AI02051
Note: Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.
6/12
M48Z2M1, M48Z2M1Y
Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
VALID
A0-A20
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI02052
Note: Write Enable (W) = High.
DATA RETENTION MODE
With valid VCC applied, the M48Z2M1/2M1Y operates as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself tWP after VCC falls below VPFD. All outputs
become high impedance, and all inputs are treated
as "don’t care."
If power fail detection occurs during a valid access,
the memory cycle continues to completion. If the
memory cycle fails to terminate within the time tWP,
write protection takes place. When VCC drops be-
low VSO, the control circuit switches power to the
internal energy source which preserves data.
The internal coin cells will maintain data in the
M48Z2M1/2M1Y after the initial application of VCC
for an accumulated period of at least 10 years when
VCC is less than VSO. As system power returns and
VCC rises above VSO, the batteries are disconnected, and the power supply is switched to external Vcc. Write protection continues for tER after VCC
reaches VPFD to allow for processor stabilization.
After tER, normal RAM operation can resume.
For more information on Battery Storage life refer
to the Application Note AN1012.
7/12
M48Z2M1, M48Z2M1Y
Table 10. Write Mode AC Characteristics
(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z2M1 / M48Z2M1Y
Symbol
Parameter
Unit
-70
Min
Max
tAVAV
Write Cycle Time
70
ns
tAVWL
Address Valid to Write Enable Low
0
ns
tAVEL
Address Valid to Chip Enable Low
0
ns
tWLWH
Write Enable Pulse Width
55
ns
tELEH
Chip Enable Low to Chip Enable High
55
ns
tWHAX
Write Enable High to Address Transition
5
ns
tEHAX
Chip Enable High to Address Transition
15
ns
tDVWH
Input Valid to Write Enable High
30
ns
tDVEH
Input Valid to Chip Enable High
30
ns
tWHDX
Write Enable High to Input Transition
0
ns
tEHDX
Chip Enable High to Input Transition
10
ns
tWLQZ
(1,2)
Write Enable Low to Output Hi-Z
25
ns
tAVWH
Address Valid to Write Enable High
65
ns
tAVEH
Address Valid to Chip Enable High
65
ns
Write Enable High to Output Transition
5
ns
tWHQX
(1,2)
Notes: 1. CL = 5pF (see Figure 4).
2. If E goes low simultaneously with W going low, the outputs remain in the high-impedance state.
POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can
be reduced if capacitors are used to store energy,
which stabilizes the VCC bus. The energy stored in
the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur. A bypass capacitor value
of 0.1µF (as shown in Figure 8) is recommended
in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate
negative voltage spikes on VCC that drive it to
values below VSS by as much as one Volt. These
negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, it is recommeded to
connect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
8/12
Figure 8. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
M48Z2M1, M48Z2M1Y
Figure 9. Write Enable Controlled, Write AC Waveforms
tAVAV
VALID
A0-A20
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02053
Note: Output Enable (G) = High.
Figure 10. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A20
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI02054
Note: Output Enable (G) = High.
9/12
M48Z2M1, M48Z2M1Y
ORDERING INFORMATION SCHEME
Example:
M48Z2M1Y
Supply Voltage and Write
Protect Voltage
2M1
2M1Y
VCC = 4.75V to 5.5V
VPFD = 4.5V to 4.75V
-70
PL
1
Speed
-70
70ns
VCC = 4.5V to 5.5V
VPFD = 4.2V to 4.5V
Package
PL
PMLDIP36
Temp. Range
1
0 to 70°C
9 (1)
Extended
Temperature
Note: 1. Contact Sales Offices for availability of Extended Temperature.
For a list of available options (Speed, Package, etc.) or for further information or any aspect of this device,
please contact the SGS-THOMSON Sales Office nearest to you.
10/12
M48Z2M1, M48Z2M1Y
PMLDIP36 - 36 pin Plastic DIP Long Module
mm
Symb
Typ
inches
Min
Max
A
9.27
A1
Typ
Min
Max
9.52
0.365
0.375
0.38
–
0.015
–
B
0.43
0.59
0.017
0.023
C
0.20
0.33
0.008
0.013
D
52.58
53.34
2.070
2.100
E
18.03
18.80
0.710
0.740
e1
2.30
2.81
0.090
0.110
e3
38.86
47.50
1.530
1.870
eA
14.99
16.00
0.590
0.630
L
3.05
3.81
0.120
0.150
S
4.45
5.33
0.175
0.210
N
36
36
PMLDIP36
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
PMDIP
Drawing is not to scale.
11/12
M48Z2M1, M48Z2M1Y
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
© 1998 SGS-THOMSON Microelectronics - All Rights Reserved
® ZEROPOWER is a registered trademark of SGS-THOMSON Microelectronics
 BYTEWIDE is a trademark of SGS-THOMSON Microelectronics
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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12/12
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