NXP NX3L1G53GD Low-ohmic single-pole double-throw analog switch Datasheet

NX3L1G53
Low-ohmic single-pole double-throw analog switch
Rev. 04 — 27 January 2010
Product data sheet
1. General description
The NX3L1G53 is a low-ohmic single-pole double-throw analog switch suitable for use as
an analog or digital 2:1 multiplexer/demultiplexer. It has a digital select input (S), two
independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an active LOW
enable input (E). When pin E is HIGH, the switch is turned off. Schmitt-trigger action at the
digital inputs makes the circuit tolerant to slower input rise and fall times.
The NX3L1G53 allows signals with amplitude up to VCC to be transmitted from Z to Y0 or
Y1; or from Y0 or Y1 to Z. Its low ON resistance (0.5 Ω) and flatness (0.13 Ω) ensures
minimal attenuation and distortion of transmitted signals.
2. Features
„ Wide supply voltage range from 1.4 V to 4.3 V
„ Very low ON resistance (peak):
‹ 1.6 Ω (typical) at VCC = 1.4 V
‹ 1.0 Ω (typical) at VCC = 1.65 V
‹ 0.55 Ω (typical) at VCC = 2.3 V
‹ 0.50 Ω (typical) at VCC = 2.7 V
‹ 0.50 Ω (typical) at VCC = 4.3 V
„ Break-before-make switching
„ High noise immunity
„ ESD protection:
‹ HBM JESD22-A114E Class 3A exceeds 7500 V
‹ MM JESD22-A115-A exceeds 200 V
‹ CDM AEC-Q100-011 revision B exceeds 1000 V
‹ IEC61000-4-2 contact discharge exceeds 8000 V for switch ports
„ CMOS low-power consumption
„ Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
„ Direct interface with TTL levels at 3.0 V
„ Control input accepts voltages above supply voltage
„ High current handling capability (350 mA continuous current under 3.3 V supply)
„ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
3. Applications
„ Cell phone
„ PDA
„ Portable media player
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
NX3L1G53GT
−40 °C to +125 °C
XSON8
plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm
SOT833-1
NX3L1G53GD
−40 °C to +125 °C
XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
SOT996-2
NX3L1G53GM
−40 °C to +125 °C
XQFN8U plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
SOT902-1
5. Marking
Table 2.
Marking codes[1]
Type number
Marking code
NX3L1G53GT
D53
NX3L1G53GD
D53
NX3L1G53GM
D53
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
6 Y1
S 5
7 Y0
Z 1
E
2
Fig 1.
001aad386
Logic symbol
NX3L1G53_4
Product data sheet
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Rev. 04 — 27 January 2010
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NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
Y0
S
Z
Y1
E
Fig 2.
001aad387
Logic diagram
7. Pinning information
7.1 Pinning
NX3L1G53
Z
1
8
VCC
E
2
7
Y0
GND
3
6
Y1
GND
4
5
NX3L1G53
S
Z
1
8
VCC
E
2
7
Y0
GND
3
6
Y1
GND
4
5
S
001aah454
001aaj534
Transparent top view
Fig 3.
Transparent top view
Pin configuration SOT833-1 (XSON8)
Fig 4.
Pin configuration SOT996-2 (XSON8U)
NX3L1G53_4
Product data sheet
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Rev. 04 — 27 January 2010
3 of 23
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
NX3L1G53
Y0
1
Y1
S
8
VCC
terminal 1
index area
Z
2
6
E
3
5
GND
GND
4
7
001aah455
Transparent top view
Fig 5.
Pin configuration SOT902-1 (XQFN8U)
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT833-1 and SOT996-2
SOT902-1
Z
1
7
common output or input
E
2
6
enable input (active LOW)
GND
3
5
ground (0 V)
GND
4
4
ground (0 V)
S
5
3
select input
Y1
6
2
independent input or output
Y0
7
1
independent input or output
VCC
8
8
supply voltage
8. Functional description
Table 4.
Function table[1]
Input
Channel
S
E
L
L
Y0 to Z or Z to Y0
H
L
Y1 to Z or Z to Y1
X
H
switch off
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
NX3L1G53_4
Product data sheet
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Rev. 04 — 27 January 2010
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NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
Max
Unit
−0.5
+4.6
V
[1]
−0.5
+4.6
V
[2]
−0.5
VCC + 0.5 V
VI
input voltage
VSW
switch voltage
IIK
input clamping current
VI < −0.5 V
−50
-
mA
ISK
switch clamping current
VI < −0.5 V or VI > VCC + 0.5 V
-
±50
mA
ISW
switch current
VSW > −0.5 V or VSW < VCC + 0.5 V;
source or sink current
-
±350
mA
VSW > −0.5 V or VSW < VCC + 0.5 V;
pulsed at 1 ms duration, < 10 % duty cycle;
peak current
-
±500
mA
−65
+150
°C
-
250
mW
Tstg
select input S and enable input E
Min
storage temperature
Ptot
total power dissipation
Tamb = −40 °C to +125 °C
[3]
[1]
The minimum input voltage rating may be exceeded if the input current rating is observed.
[2]
The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not
exceed 4.6 V.
[3]
For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
10. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol Parameter
VCC
supply voltage
VI
input voltage
VSW
switch voltage
Tamb
ambient temperature
Δt/ΔV
input transition rise and fall rate
Conditions
select input S and enable input E
[1]
VCC = 1.4 V to 4.3 V
[2]
Min
Max
Unit
1.4
4.3
V
0
4.3
V
0
VCC
V
−40
+125
°C
-
200
ns/V
[1]
To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit
for the voltage drop across the switch.
[2]
Applies to control signals.
NX3L1G53_4
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 04 — 27 January 2010
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NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
VIH
VIL
HIGH-level
input voltage
LOW-level
input voltage
25 °C
Conditions
−40 °C to +125 °C
Unit
Min
Typ
Max
Min
Max
Max
(85 °C) (125 °C)
VCC = 1.4 V to 1.95 V
0.65VCC
-
-
0.65VCC
-
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
-
V
VCC = 3.6 V to 4.3 V
0.7VCC
-
-
0.7VCC
-
-
V
VCC = 1.4 V to 1.95 V
-
-
0.35VCC
-
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
0.8
V
0.35VCC 0.35VCC V
VCC = 3.6 V to 4.3 V
-
-
0.3VCC
-
0.3VCC
II
input leakage
current
select input S and enable
input E; VI = GND to 4.3 V;
VCC = 1.4 V to 4.3 V
-
-
-
-
±0.5
±1
μA
IS(OFF)
OFF-state
leakage
current
Y0 and Y1 port;
see Figure 6
VCC = 1.4 V to 3.6 V
-
-
±5
-
±50
±500
nA
VCC = 3.6 V to 4.3 V
-
-
±10
-
±50
±500
nA
VCC = 1.4 V to 3.6 V
-
-
±5
-
±50
±500
nA
VCC = 3.6 V to 4.3 V
-
-
±10
-
±50
±500
nA
VCC = 3.6 V
-
-
100
-
690
6000
nA
VCC = 4.3 V
-
-
150
-
800
7000
nA
IS(ON)
ICC
ON-state
leakage
current
0.3VCC V
Z port; see Figure 7
supply current VI = VCC or GND;
VSW = GND or VCC
CI
input
capacitance
-
1.0
-
-
-
-
pF
CS(OFF)
OFF-state
capacitance
-
35
-
-
-
-
pF
CS(ON)
ON-state
capacitance
-
130
-
-
-
-
pF
NX3L1G53_4
Product data sheet
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Rev. 04 — 27 January 2010
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NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
11.1 Test circuits
VCC
S
VIL or VIH
Y0
Z
Y1
1
switch
2
switch
S
E
1
VIL
VIH
2
VIH
VIH
IS
E
GND
VIH
VI
VO
001aad390
VI = 0.3 V or VCC − 0.3 V; VO = VCC − 0.3 V or 0.3 V.
Fig 6.
Test circuit for measuring OFF-state leakage current
VCC
S
VIL or VIH
IS
Z
Y0
1
Y1
2
switch
S
E
1
VIL
VIL
2
VIH
VIL
switch
E
GND
VIL
VO
VI
001aad391
VI = 0.3 V or VCC − 0.3 V; VO = open circuit.
Fig 7.
Test circuit for measuring ON-state leakage current
NX3L1G53_4
Product data sheet
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Rev. 04 — 27 January 2010
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NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
11.2 ON resistance
Table 8.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 to Figure 15.
Symbol
RON(peak)
Parameter
ON resistance (peak)
−40 °C to +85 °C
Conditions
Max
Min
Max
VCC = 1.4 V
-
1.6
3.7
-
4.1
Ω
VCC = 1.65 V
-
1.0
1.6
-
1.7
Ω
VCC = 2.3 V
-
0.55
0.8
-
0.9
Ω
VCC = 2.7 V
-
0.5
0.75
-
0.9
Ω
-
0.5
0.75
-
0.9
Ω
VCC = 1.4 V
-
0.04
0.3
-
0.3
Ω
VCC = 1.65 V
-
0.04
0.2
-
0.3
Ω
VCC = 2.3 V
-
0.02
0.08
-
0.1
Ω
VCC = 2.7 V
-
0.02
0.075
-
0.1
Ω
-
0.02
0.075
-
0.1
Ω
VCC = 1.4 V
-
1.0
3.3
-
3.6
Ω
VCC = 1.65 V
-
0.5
1.2
-
1.3
Ω
VCC = 2.3 V
-
0.15
0.3
-
0.35
Ω
VCC = 2.7 V
-
0.13
0.3
-
0.35
Ω
VCC = 4.3 V
-
0.2
0.4
-
0.45
Ω
VI = GND to VCC;
ISW = 100 mA;
see Figure 8
ON resistance mismatch VI = GND to VCC;
between channels
ISW = 100 mA
[2]
VCC = 4.3 V
RON(flat)
Unit
Min
VCC = 4.3 V
ΔRON
−40 °C to +125 °C
Typ[1]
ON resistance (flatness) VI = GND to VCC;
ISW = 100 mA
[3]
[1]
Typical values are measured at Tamb = 25 °C.
[2]
Measured at identical VCC, temperature and input voltage.
[3]
Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
NX3L1G53_4
Product data sheet
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Rev. 04 — 27 January 2010
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NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
11.3 ON resistance test circuit and waveforms
V
VCC
S
VIL or VIH
Z
VSW
Y0
1
Y1
2
switch
S
E
1
VIL
VIL
2
VIH
VIL
switch
E
GND
VIL
VI
ISW
001aah456
RON = VSW / ISW.
Fig 8.
Test circuit for measuring ON resistance
001aag564
1.6
RON
(Ω)
1.2
(1)
0.8
(2)
(3)
(4)
0.4
(5)
(6)
0
0
1
2
3
4
5
VI (V)
(1) VCC = 1.5 V.
(2) VCC = 1.8 V.
(3) VCC = 2.5 V.
(4) VCC = 2.7 V.
(5) VCC = 3.3 V.
(6) VCC = 4.3 V.
Measured at Tamb = 25 °C.
Fig 9.
ON resistance as a function of input voltage
NX3L1G53_4
Product data sheet
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Rev. 04 — 27 January 2010
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NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
001aag565
1.6
001aag566
1.0
RON
(Ω)
RON
(Ω)
0.8
1.2
(1)
(2)
(3)
(4)
0.6
(1)
(2)
(3)
(4)
0.8
0.4
0.4
0.2
0
0
0
1
2
3
0
1
2
VI (V)
(1) Tamb = 125 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(4) Tamb = −40 °C.
Fig 10. ON resistance as a function of input voltage;
VCC = 1.5 V
001aag567
1.0
3
VI (V)
RON
(Ω)
Fig 11. ON resistance as a function of input voltage;
VCC = 1.8 V
001aaj896
1.0
RON
(Ω)
0.8
0.8
0.6
0.6
(1)
(2)
(3)
(4)
0.4
0.4
0.2
0.2
0
(1)
(2)
(3)
(4)
0
0
1
2
3
0
1
VI (V)
3
4
5
VI (V)
(1) Tamb = 125 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(4) Tamb = −40 °C.
Fig 12. ON resistance as a function of input voltage;
VCC = 2.5 V
Fig 13. ON resistance as a function of input voltage;
VCC = 2.7 V
NX3L1G53_4
Product data sheet
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NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
001aag569
1.0
RON
(Ω)
001aaj896
1.0
RON
(Ω)
0.8
0.8
0.6
0.6
(1)
(2)
(3)
(4)
0.4
(1)
(2)
(3)
(4)
0.4
0.2
0.2
0
0
0
1
2
3
4
0
1
2
3
4
VI (V)
5
VI (V)
(1) Tamb = 125 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(4) Tamb = −40 °C.
Fig 14. ON resistance as a function of input voltage;
VCC = 3.3 V
Fig 15. ON resistance as a function of input voltage;
VCC = 4.3 V
12. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18.
Symbol Parameter
ten
tdis
enable time
disable time
25 °C
Conditions
Unit
Min
Max
Min
Max
(85 °C)
Max
(125 °C)
VCC = 1.4 V to 1.6 V
-
28
42
-
45
50
ns
VCC = 1.65 V to 1.95 V
-
23
34
-
37
41
ns
VCC = 2.3 V to 2.7 V
-
17
27
-
29
31
ns
VCC = 2.7 V to 3.6 V
-
15
24
-
26
28
ns
VCC = 3.6 V to 4.3 V
-
15
24
-
26
28
ns
VCC = 1.4 V to 1.6 V
-
10
19
-
21
23
ns
VCC = 1.65 V to 1.95 V
-
7
14
-
16
17
ns
VCC = 2.3 V to 2.7 V
-
5
9
-
10
11
ns
VCC = 2.7 V to 3.6 V
-
4
8
-
9
9
ns
VCC = 2.7 V to 4.3 V
-
4
8
-
9
9
ns
S or E to Z or Yn;
see Figure 16
S or E to Z or Yn;
see Figure 16
NX3L1G53_4
Product data sheet
−40 °C to +125 °C
Typ[1]
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NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
Table 9.
Dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18.
Symbol Parameter
tb-m
25 °C
Conditions
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
(85 °C)
Max
(125 °C)
-
19
-
9
-
-
ns
VCC = 1.65 V to 1.95 V
-
17
-
7
-
-
ns
VCC = 2.3 V to 2.7 V
-
13
-
5
-
-
ns
VCC = 2.7 V to 3.6 V
-
10
-
3
-
-
ns
VCC = 2.7 V to 4.3 V
-
10
-
2
-
-
ns
[2]
break-before-make see Figure 17
time
VCC = 1.4 V to 1.6 V
[1]
Typical values are measured at Tamb = 25 °C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively.
[2]
Break-before-make guaranteed by design.
12.1 Waveform and test circuits
VI
VM
S, E input
VM
GND
ten
tdis
VOH
output
OFF to HIGH
HIGH to OFF
VX
VX
GND
ten
tdis
VOH
VX
output
HIGH to OFF
OFF to HIGH
VX
001aah457
GND
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Enable and disable times
Table 10.
Measurement points
Supply voltage
Input
Output
VCC
VM
VX
1.4 V to 4.3 V
0.5VCC
0.9VOH
NX3L1G53_4
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Rev. 04 — 27 January 2010
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NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
VCC
Y0
S
Z
Y1
E
VIL
G
VI
V
VO
RL
CL
VEXT = 1.5 V
GND
001aah458
a. Test circuit
VI
0.5VI
0.9VO
0.9VO
VO
tb-m
001aag572
b. Input and output measurement points
Fig 17. Test circuit for measuring break-before-make timing
VCC
S
Y0
1
Z
Y1
2
switch
E
VIL
VI
G
V
VO
RL
CL
VEXT = 1.5 V
GND
001aah459
Test data is given in Table 11.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
VEXT = External voltage for measuring switching times.
VI may be connected to S or E.
Fig 18. Load circuit for switching times
NX3L1G53_4
Product data sheet
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Rev. 04 — 27 January 2010
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NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
Table 11.
Test data
Supply voltage
Input
Load
VCC
VI
tr, tf
CL
RL
1.4 V to 4.3 V
VCC
≤ 2.5 ns
35 pF
50 Ω
12.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specified); tr = tf ≤ 2.5 ns; Tamb = 25 °C.
Symbol Parameter
Conditions
THD
fi = 20 Hz to 20 kHz; RL = 32 Ω; see Figure 19
total harmonic
distortion
Min
-
0.15
-
%
-
0.10
-
%
VCC = 2.3 V; VI = 1.5 V (p-p)
-
0.02
-
%
VCC = 2.7 V; VI = 2 V (p-p)
-
0.02
-
%
-
0.02
-
%
-
60
-
MHz
-
−90
-
dB
-
0.2
-
V
-
0.3
-
V
-
−90
-
dB
VCC = 1.5 V
-
3
-
pC
VCC = 1.8 V
-
4
-
pC
VCC = 2.5 V
-
6
-
pC
VCC = 3.3 V
-
9
-
pC
VCC = 4.3 V
-
15
-
pC
VCC = 4.3 V; VI = 2 V (p-p)
αiso
isolation (OFF-state)
fi = 100 kHz; RL = 50 Ω; see Figure 21
Vct
crosstalk voltage
between digital inputs and switch;
fi = 1 MHz; CL = 50 pF; RL = 50 Ω; see Figure 22
[1]
VCC = 1.4 V to 4.3 V
[1]
VCC = 1.4 V to 4.3 V
VCC = 1.4 V to 3.6 V
VCC = 3.6 V to 4.3 V
crosstalk
between switches;
fi = 100 kHz; RL = 50 Ω; see Figure 23
VCC = 1.4 V to 4.3 V
Qinj
[1]
charge injection
Unit
VCC = 1.65 V; VI = 1.2 V (p-p)
RL = 50 Ω; see Figure 20
Xtalk
Max
VCC = 1.4 V; VI = 1 V (p-p)
−3 dB frequency
response
f(−3dB)
Typ
[1]
[1]
fi = 1 MHz; CL = 0.1 nF; RL = 1 MΩ; Vgen = 0 V;
Rgen = 0 Ω; see Figure 24
fi is biased at 0.5VCC.
NX3L1G53_4
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 04 — 27 January 2010
14 of 23
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
12.3 Test circuits
VCC
0.5VCC
RL
S
VIL or VIH
Z
Y0
1
Y1
2
switch
switch
S
E
1
VIL
VIL
2
VIH
VIL
E
VIL
D
fi
GND
001aah460
Fig 19. Test circuit for measuring total harmonic distortion
VCC
0.5VCC
RL
S
VIL or VIH
Z
Y0
1
Y1
2
switch
switch
S
E
1
VIL
VIL
2
VIH
VIL
E
VIL
dB
fi
GND
001aah461
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3 dB.
Fig 20. Test circuit for measuring the frequency response when switch is in ON-state
0.5VCC
VCC
0.5VCC
RL
RL
S
VIL or VIH
Z
Y0
1
Y1
2
switch
switch
S
E
1
VIH
VIH
2
VIL
VIH
E
VIH
dB
fi
GND
001aah462
Adjust fi voltage to obtain 0 dBm level at input.
Fig 21. Test circuit for measuring isolation (OFF-state)
NX3L1G53_4
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 04 — 27 January 2010
15 of 23
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
VCC
S
VIL or VIH
E
Y0
Z
VI
logic
input
G
Y1
RL
RL
0.5VCC
0.5VCC
CL
V
VO
001aah452
a. Test circuit
logic input
(S, E)
off
on
off
Vct
VO
001aah453
b. Input and output pulse definitions
VI may be connected to S or E.
Fig 22. Test circuit for measuring crosstalk voltage between digital inputs and switch
VCC
VIL or VIH
S
Z
0.5VCC
0.5VCC
RL
RL
Y0
1
Y1
2
E
VIH
fi
dB
GND
001aah463
Fig 23. Test circuit for measuring crosstalk
NX3L1G53_4
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 04 — 27 January 2010
16 of 23
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
VCC
S
Y0
1
Z
Y1
2
switch
E
Rgen
VIL
VI G
VO
RL
CL
Vgen
GND
001aad398
a. Test circuit
logic input
(S, E)
off
on
off
ΔVO
VO
001aah451
b. Input and output pulse definitions
Qinj = ΔVO × CL.
ΔVO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
VI may be connected to S or E.
Fig 24. Test circuit for measuring charge injection
NX3L1G53_4
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 04 — 27 January 2010
17 of 23
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
13. Package outline
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
1
2
SOT833-1
b
4
3
4×
(2)
L
L1
e
8
7
6
e1
5
e1
e1
8×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
2.0
1.9
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT833-1
---
MO-252
---
EUROPEAN
PROJECTION
ISSUE DATE
07-11-14
07-12-07
Fig 25. Package outline SOT833-1 (XSON8)
NX3L1G53_4
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 04 — 27 January 2010
18 of 23
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
B
D
SOT996-2
A
A
E
A1
detail X
terminal 1
index area
e1
v
w
b
e
L1
1
4
8
5
C
C A B
C
M
M
y
y1 C
L2
L
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
L2
v
w
y
y1
mm
0.5
0.05
0.00
0.35
0.15
2.1
1.9
3.1
2.9
0.5
1.5
0.5
0.3
0.15
0.05
0.6
0.4
0.1
0.05
0.05
0.1
REFERENCES
OUTLINE
VERSION
IEC
SOT996-2
---
JEDEC
JEITA
---
EUROPEAN
PROJECTION
ISSUE DATE
07-12-18
07-12-21
Fig 26. Package outline SOT996-2 (XSON8U)
NX3L1G53_4
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 04 — 27 January 2010
19 of 23
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
B
D
SOT902-1
A
terminal 1
index area
A
E
A1
detail X
L1
e
e
C
∅v M C A B
∅w M C
L
4
y1 C
y
5
3
metal area
not for soldering
e1
b
2
6
e1
7
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
v
w
y
y1
mm
0.5
0.05
0.00
0.25
0.15
1.65
1.55
1.65
1.55
0.55
0.5
0.35
0.25
0.15
0.05
0.1
0.05
0.05
0.05
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT902-1
---
MO-255
---
EUROPEAN
PROJECTION
ISSUE DATE
05-11-25
07-11-14
Fig 27. Package outline SOT902-1 (XQFN8U)
NX3L1G53_4
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 04 — 27 January 2010
20 of 23
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
14. Abbreviations
Table 13.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NX3L1G53_4
20100127
Product data sheet
-
NX3L1G53_3
Modifications:
•
•
Section 2: IEC61000-4-2 added.
Table 8: ON resistance (flattness) changed at VCC = 4.3 V.
NX3L1G53_3
20090417
Product data sheet
-
NX3L1G53_2
NX3L1G53_2
20080718
Product data sheet
-
NX3L1G53_1
NX3L1G53_1
20080408
Product data sheet
-
-
NX3L1G53_4
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 04 — 27 January 2010
21 of 23
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NX3L1G53_4
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 04 — 27 January 2010
22 of 23
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
18. Contents
1
2
3
4
5
6
7
7.1
7.2
8
9
10
11
11.1
11.2
11.3
12
12.1
12.2
12.3
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ON resistance test circuit and waveforms . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveform and test circuits . . . . . . . . . . . . . . . 12
Additional dynamic characteristics . . . . . . . . . 14
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 27 January 2010
Document identifier: NX3L1G53_4
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