PHILIPS BUK108-50GS Powermos transistor topfet Datasheet

Philips Semiconductors
Product specification
PowerMOS transistor
TOPFET
DESCRIPTION
Monolithic temperature and
overload protected power MOSFET
in a 3 pin plastic surface mount
envelope, intended as a general
purpose switch for automotive
systems and other applications.
APPLICATIONS
BUK108-50GS
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
PD
Tj
RDS(ON)
Continuous drain source voltage
Continuous drain current
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
VIS = 10 V
MAX.
UNIT
50
15
40
150
100
V
A
W
˚C
mΩ
General controller for driving
lamps
motors
solenoids
heaters
FEATURES
Vertical power DMOS output
stage
Low on-state resistance
Overload protection against
over temperature
Overload protection against
short circuit load
Latched overload protection
reset by input
10 V input level
Low threshold voltage
also allows 5 V control
Control of power MOSFET
and supply of overload
protection circuits
derived from input
ESD protection on input pin
Overvoltage clamping for turn
off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
DRAIN
O/V
CLAMP
POWER
INPUT
MOSFET
RIG
LOGIC AND
PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT404
PIN
PIN CONFIGURATION
DESCRIPTION
mb
1
input
2
drain
3
source
mb
SYMBOL
drain
June 1996
D
TOPFET
I
P
2
1
S
3
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
TOPFET
BUK108-50GS
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
VDSS
VIS = 0 V
VIS
ID
ID
IDRM
PD
Tstg
Tj
Continuous off-state drain source
voltage1
Continuous input voltage
Continuous drain current
Continuous drain current
Repetitive peak on-state drain current
Total power dissipation
Storage temperature
Continuous junction temperature2
Tmb ≤ 25 ˚C; VIS = 10 V
Tmb ≤ 100 ˚C; VIS = 10 V
Tmb ≤ 25 ˚C; VIS = 10 V
Tmb ≤ 25 ˚C
normal operation
Tsold
Lead temperature
during soldering
MIN.
MAX.
UNIT
-
50
V
0
-55
-
11
15
9.5
60
40
150
150
V
A
A
A
W
˚C
˚C
-
250
˚C
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload.
SYMBOL
VISP
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
5
-
V
Protected drain source supply voltage VIS = 10 V
-
50
V
Short circuit load protection
Protected drain source supply voltage4 VIS = 10 V
VIS = 5 V
Instantaneous overload dissipation
Tmb = 25 ˚C
-
20
35
0.6
V
V
kW
3
Protection supply voltage
for valid protection
Over temperature protection
VDDP(T)
VDDP(P)
PDSM
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL
PARAMETER
CONDITIONS
IDROM
EDSM
Repetitive peak clamping current
Non-repetitive clamping energy
EDRM
Repetitive clamping energy
VIS = 0 V
Tmb ≤ 25 ˚C; IDM = 15 A;
VDD ≤ 20 V; inductive load
Tmb ≤ 95 ˚C; IDM = 4 A;
VDD ≤ 20 V; f = 250 Hz
MIN.
MAX.
UNIT
-
15
200
A
mJ
-
20
mJ
MIN.
MAX.
UNIT
-
2
kV
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
VC
Electrostatic discharge capacitor
voltage
Human body model;
C = 250 pF; R = 1.5 kΩ
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.
3 The input voltage for which the overload protection circuits are functional.
4 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed VDDP(P) maximum.
For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.
June 1996
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
TOPFET
BUK108-50GS
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
-
2.5
3.1
K/W
-
50
-
K/W
MIN.
TYP.
MAX.
UNIT
50
-
-
V
Thermal resistance
Rth j-mb
Junction to mounting base
Rth j-a
Junction to ambient
minimum footprint FR4 PCB
(see fig. 33)
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
V(CL)DSS
Drain-source clamping voltage
VIS = 0 V; ID = 10 mA
V(CL)DSS
Drain-source clamping voltage
IDSS
IDSS
IDSS
RDS(ON)
VIS = 0 V; IDM = 1 A; tp ≤ 300 µs;
δ ≤ 0.01
Zero input voltage drain current VDS = 12 V; VIS = 0 V
Zero input voltage drain current VDS = 50 V; VIS = 0 V
Zero input voltage drain current VDS = 40 V; VIS = 0 V; Tj = 125 ˚C
-
-
70
V
-
0.5
1
10
10
20
100
µA
µA
µA
Drain-source on-state
resistance
-
65
85
100
125
mΩ
mΩ
IDM = 7.5 A;
tp ≤ 300 µs; δ ≤ 0.01
VIS = 10 V
VIS = 5 V
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input.
SYMBOL
PARAMETER
CONDITIONS
1
Tmb = 25 ˚C; L ≤ 10 µH
VDD = 13 V; VIS = 10 V
VDD = 13 V; VIS = 10 V
EDS(TO)
td sc
Short circuit load protection
Overload threshold energy
Response time
Tj(TO)
Over temperature protection
Threshold junction temperature VIS = 10 V; from ID ≥ 0.5 A2
MIN.
TYP.
MAX.
UNIT
-
0.2
0.8
-
J
ms
150
-
-
˚C
1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for
PDSM, which is always the case when VDS is less than VDSP maximum. Refer to OVERLOAD PROTECTION LIMITING VALUES.
2 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID
ensures this condition.
June 1996
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
TOPFET
BUK108-50GS
INPUT CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VIS(TO)
IIS
VISR
Input threshold voltage
Input supply current
Protection reset voltage1
VDS = 5 V; ID = 1 mA
VIS = 10 V; normal operation
1.0
2.0
1.5
0.4
2.6
2.0
1.0
3.5
V
mA
V
VISR
Protection reset voltage
Tj = 150 ˚C
1.0
-
-
IISL
V(BR)IS
RIG
Input supply current
Input clamp voltage
Input series resistance
VIS = 10 V; protection latched
II = 10 mA
to gate of power MOSFET
1.0
11
-
2.5
13
4
5.0
-
mA
V
kΩ
MIN.
TYP.
MAX.
UNIT
TRANSFER CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL
PARAMETER
CONDITIONS
gfs
Forward transconductance
VDS = 10 V; IDM = 7.5 A tp ≤ 300 µs;
δ ≤ 0.01
5
9
-
S
ID(SC)
Drain current2
VDS = 13 V; VIS = 10 V
-
40
-
A
MIN.
TYP.
MAX.
UNIT
SWITCHING CHARACTERISTICS
Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figures and test circuits.
SYMBOL
PARAMETER
CONDITIONS
td on
Turn-on delay time
VDD = 13 V; VIS = 10 V
-
1
-
µs
tr
Rise time
resistive load RL = 4 Ω
-
4
-
µs
td off
Turn-off delay time
VDD = 13 V; VIS = 0 V
-
10
-
µs
tf
Fall time
resistive load RL = 4 Ω
-
5
-
µs
td on
Turn-on delay time
VDD = 13 V; VIS = 10 V
-
1
-
µs
tr
Rise time
inductive load IDM = 3 A
-
0.5
-
µs
td off
Turn-off delay time
VDD = 13 V; VIS = 0 V
-
15
-
µs
tf
Fall time
inductive load IDM = 3 A
-
0.5
-
µs
REVERSE DIODE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
IS
Continuous forward current
Tmb ≤ 25 ˚C; VIS = 0 V
MIN.
MAX.
UNIT
-
15
A
1 The input voltage below which the overload protection circuits will be reset.
2 During overload before short circuit load protection operates.
June 1996
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
TOPFET
BUK108-50GS
REVERSE DIODE CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VSDS
Forward voltage
IS = 15 A; VIS = 0 V; tp = 300 µs
-
1.0
1.5
V
trr
Reverse recovery time
not applicable1
-
-
-
-
MIN.
TYP.
MAX.
UNIT
-
2.5
-
nH
-
7.5
-
nH
ENVELOPE CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
Ld
Internal drain inductance
Ls
Internal source inductance
Measured from upper edge of tab
to centre of die
Measured from source lead
solering point to source bond pad
120
Normalised Power Derating
PD%
BUK108-50GS
ID & IDM / A
100
110
D
S/I
tp =
D
100
90
N)
=V
10 us
O
S(
RD
80
10
100 us
70
1 ms
60
50
DC
40
10 ms
1
100 ms
30
20
10
Overload protection characteristics not shown
0
0
20
40
60
80
100
Tmb / C
120
0.1
140
Fig.4. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
100
VDS / V
Fig.2. Normalised limiting power dissipation.
PD% = 100⋅PD/PD(25 ˚C) = f(Tmb)
120
10
1
10
BUK108-50GS
Zth / (K/W)
110
D=
100
90
0.5
1
80
70
0.2
60
50
0.05
0.1
0.1
40
0.02
PD
30
20
10
tp
D=
tp
T
0
0
0
20
40
60
80
Tmb / C
100
120
0.01
1E-07
140
Fig.3. Normalised continuous drain current.
ID% = 100⋅ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V
T
1E-05
1E-03
t/s
t
1E-01
1E+01
Fig.5. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
1 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
June 1996
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
TOPFET
BUK108-50GS
ID / A
60
BUK108-50GS
11
60
ID / A
BUK108-50GS
10
50
50
9
8
40
40
7
30
30
6
5
20
20
4
10
10
3
0
0
0
4
8
12
16
VDS / V
20
24
28
32
0
ID / A
BUK108-50GS
VIS / V =
8
9
4
6
VIS / V
8
10
12
Fig.9. Typical transfer characteristics, Tj = 25 ˚C.
ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 µs
Fig.6. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 250 µs & tp < td sc
50
2
12
10
gfs / S
BUK108-50GS
11
10
40
9
7
8
6
30
7
6
5
20
5
4
3
10
4
2
1
0
0
1
0
3
2
5
4
10
0
RDS(ON) / Ohm
Fig.10. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 10 V; tp = 250 µs
a
BUK108-50GS
VIS / V =
0.15
Normalised RDS(ON) = f(Tj)
1.5
6
5
4
50
40
ID / A
Fig.7. Typical on-state characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 250 µs
0.20
30
20
VDS / V
7
8
9
1.0
10
0.10
0.5
0.05
0
0
0
10
20
30
40
50
ID / A
Fig.8. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VIS; tp = 250 µs
June 1996
-60 -40 -20
0
20
40 60
Tj / C
80
100 120 140
Fig.11. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 7.5 A; VIS = 5 V
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
TOPFET
BUK108-50GS
td sc / ms
100
BUK108-50GS
20
ID / A
BUK108-50GS
15
10
typ.
10
PDSM
1
5
0
0.1
0.1
PDS / kW
0.01
50
1
Fig.12. Typical overload protection characteristics.
td sc = f(PDS); conditions: VIS ≥ 5 V; Tj = 25 ˚C.
60
VDS / V
70
Fig.15. Typical clamping characteristics, 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs
VIS(TO) / V
PDSM%
120
max.
2
100
typ.
80
60
min.
1
40
20
0
0
-60
-40
-20
0
20
40
60
Tmb / C
80
100
120
140
-60
Fig.13. Normalised limiting overload dissipation.
PDSM% =100⋅PDSM/PDSM(25 ˚C) = f(Tmb)
1
-20
0
20
40
60
Tj / C
80
100
120 140
Fig.16. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
BUK108-50GS
Energy & Time
-40
1.0
II / mA
BUK108-50GS
Time / ms
0.5
0.5
Energy / J
0
-60
-20
20
60
100
Tmb / C
Tj(TO)
140
180
0
220
0
4
6
8
10
12
14
VIS / V
Fig.14. Typical overload protection characteristics.
Conditions: VDD = 13 V; VIS = 10 V; SC load = 30 mΩ
June 1996
2
Fig.17. Typical DC input characteristics, Tj = 25 ˚C.
IIS = f(VIS); normal operation
7
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
TOPFET
BUK108-50GS
BUK108-50GS
RESISTIVE TURN-ON
BUK108-50GS
IIS / mA
5
10
4
VIS / V
3
PROTECTION LATCHED
5
tr
2
ID / A
RESET
90%
NORMAL
VDS / V
10%
1
10%
0
td on
0
0
0
2
4
6
8
VIS / V
10
12
IS / A
20
Fig.21. Typical switching waveforms, resistive load.
VDD = 13 V; RL = 4 Ω; RI = 50 Ω, Tj = 25 ˚C.
Fig.18. Typical DC input characteristics, Tj = 25 ˚C.
IISL = f(VIS); overload protection operated ⇒ ID = 0 A
60
10
time / us
14
BUK108-50GS
RESISTIVE TURN-OFF
BUK108-50GS
td off
50
10
90%
VDS / V
40
VIS / V
30
tf
5
ID / A
20
90%
10
10%
0
0
0
0
0.2
0.4
0.6
0.8
VSD / V
1
1.2
10
time / us
1.4
20
Fig.22. Typical switching waveforms, resistive load.
VDD = 13 V; RL = 4 Ω; RI = 50 Ω, Tj = 25 ˚C.
Fig.19. Typical reverse diode current, Tj = 25 ˚C.
IS = f(VSDS); conditions: VIS = 0 V; tp = 250 µs
VDD
VDD = VCL
RL
LD
t p : adjust for correct ID
TOPFET
I
P
D
TOPFET
I
D.U.T.
P
RI
VIS
D
D.U.T.
RI
VIS
S
ID measure
S
ID measure
0V
0V
0R1
0R1
Fig.20. Test circuit for resistive load switching times.
June 1996
Fig.23. Test circuit for inductive load switching times.
8
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
TOPFET
BUK108-50GS
V(CL)DSS
BUK108-50GS
INDUCTIVE TURN-ON
VDS
VDD
VDS
+
0
VIS / V
10
L
ID
VDS
0
td on
TOPFET
tr
ID / A
0
P
90%
2
R 01
shunt
Schottky
10%
0
-ID/100
D.U.T.
I
10%
0
-
D
VIS
5
RIS
4
6
8
VDD
S
10
time / us
Fig.27. Clamping energy test circuit, RIS = 50 Ω.
EDSM = 0.5 ⋅ LID2 ⋅ V(CL)DSS /(V(CL)DSS − VDD )
Fig.24. Typical switching waveforms, inductive load.
VDD = 13 V; ID = 3 A; RI = 50 Ω, Tj = 25 ˚C.
15
BUK108-50GS
INDUCTIVE TURN-OFF
1 mA
Idss
VDS / V
td off
100 uA
10
90%
VIS / V
tf
10 uA
typ.
5
ID / A
90%
1 uA
10%
0
0
10
time / us
100 nA
20
0
Fig.25. Typical switching waveforms, inductive load.
VDD = 13 V; ID = 3 A; RI = 50 Ω, Tj = 25 ˚C.
120
20
40
60
80
Tj / C
100
120
140
Fig.28. Typical off-state leakage current.
IDSS = f(Tj); Conditions: VDS = 40 V; IIS = 0 V.
Iiso normalised to 25 C
EDSM%
110
100
1.5
90
80
70
60
50
1
40
30
20
10
0
0.5
0
20
40
60
80
Tmb / C
100
120
140
-60
Fig.26. Normalised limiting clamping energy.
EDSM% = f(Tmb); conditions: ID = 15 A; VIS = 10 V
June 1996
-20
20
60
Tj / C
100
140
180
Fig.29. Normalised input current (normal operation).
IIS/IIS25 ˚C = f(Tj); VIS = 10 V
9
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
TOPFET
BUK108-50GS
Iisl normalised to 25 C
50
1.5
VDDP(P) / V
BUK108-50GS
40
max
30
1
20
10
0
0.5
-60
-20
20
60
Tj / C
100
140
0
180
Fig.30. Normalised input current (protection latched).
IISL/IISL25 ˚C = f(Tj); VIS = 10 V
June 1996
2
4
6
VIS / V
8
10
Fig.31. Maximum drain source supply voltage for
SC load protection. VDDP(P) = f(VIS); Tmb ≤ 150 ˚C
10
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
TOPFET
BUK108-50GS
MECHANICAL DATA
Dimensions in mm
4.5 max
1.4 max
10.3 max
Net Mass: 1.4 g
11 max
15.4
2.5
0.85 max
(x2)
0.5
2.54 (x2)
Fig.32. SOT404 : centre pin connected to mounting base.
Notes
1. Epoxy meets UL94 V0 at 1/8".
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.33. SOT404 : minimum pad sizes for surface mounting.
Notes
1. Plastic meets UL94 V0 at 1/8".
June 1996
11
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
TOPFET
BUK108-50GS
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
June 1996
12
Rev 1.000
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