Catalyst CAT5411UI-00-TE13 Dual digitally programmable potentiometers (dpp) with 64 taps and spi interface Datasheet

H
CAT5411
EE
GEN FR
ALO
Dual Digitally Programmable Potentiometers (DPP™) with
64 Taps and SPI Interface
LE
FEATURES
A D F R E ETM
■ Automatic recall of saved wiper settings at
■ Two linear-taper digitally programmable
power up
potentiometers
■ 64 resistor taps per potentiometer
■ 2.5 to 6.0 volt operation
■ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ
■ Standby current less than 1µA
■ Potentiometer control and memory access via
■ 1,000,000 nonvolatile WRITE cycles
SPI interface: Mode (0, 0) and (1, 1)
■ 100 year nonvolatile memory data retention
Ω
■ Low wiper resistance, typically 80Ω
■ 24-lead SOIC, 24-lead TSSOP, and BGA
■ Nonvolatile memory storage for up to four wiper
■ Industrial temperature ranges
settings for each potentiometer
DESCRIPTION
wiper control register or any of the non-volatile data
registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the
two potentiometers is automatically loaded into its
respective wiper control register.
The CAT5411 is two Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
SOIC Package (J, W)
TSSOP Package (U, Y)
VCC
1
24
NC
SI
1
24
WP
RL0
RH0
2
23
NC
2
23
CS
3
22
NC
A1
RL1
3
22
RW0
RW0
4
21
NC
RH1
4
21
RH0
CS
5
20
A0
RW1
5
20
RL0
WP
6
VCC
7
CAT 19
5411 18
SO
SI
A1
RL1
RH1
8
9
10
15
NC
NC
10
15
NC
RW1
11
14
NC
SCK
11
14
A0
GND
12
13
NC
HOLD
12
13
SO
A
B
BGA
C
D
E
F
The CAT5411 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
GND
6
HOLD
NC
7
CAT 19
5411 18
17
SCK
NC
8
17
NC
16
NC
NC
9
16
NC
1
2
3
4
RW0
CS
A1
RL1
RL0
WP
SI
RW1
VCC
RH0
RH1
VSS
NC
NC
NC
NC
NC
SO
HOLD
NC
NC
A0
SCK
NC
RH0
CS
SCK
SI
SO
SPI BUS
INTERFACE
WP
A0
A1
CONTROL
LOGIC
RH1
WIPER
CONTROL
REGISTERS
R W0
NC
R W1
NONVOLATILE
DATA
REGISTERS
RL0
RL1
Top View - Bump Side Down
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Document No. 2114, Rev. G
CAT5411
PIN DESCRIPTION
Pin
(SOIC)
PIN DESCRIPTIONS
Pin
Pin
(TSSOP) (BGA) Name
SI:
Serial Input
SI is the serial data input pin. This pin is used to input
all opcodes, byte addresses and data to be written to
the CAT5411. Input data is latched on the rising edge
of the serial clock.
Function
1
19
C1
VCC
Supply Voltage
2
20
B1
RL0
Low Reference Terminal
for Potentiometer 0
3
21
C2
RH0
High Reference Terminal
for Potentiometer 0
4
22
A1
RW0
Wiper Terminal for Potentiometer 0
5
23
A2
CS
Chip Select
6
24
B2
WP
Write Protection
7
1
B3
SI
Serial Input
8
2
A3
A1
Device Address
9
3
A4
RL1
Low Reference Terminal
for Potentiometer 1
10
4
C3
RH1
High Reference Terminal
for Potentiometer 1
11
5
B4
RW1
Wiper Terminal for Potentiometer 1
12
6
C4
GND
Ground
13
7
D4
NC
No Connect
14
8
E4
NC
No Connect
15
9
D3
NC
No Connect
16
10
F4
NC
17
11
F3
SCK
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5411. During a read
cycle, data is shifted out on the falling edge of the
serial clock.
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5411. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when addressing multiple devices. A total of four devices can be
addressed on a single bus. A match in the slave
address must be made with the address input in
order to initiate communication with the CAT5411.
No Connect
RH, RL: Resistor End Points
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
Bus Serial Clock
18
12
E3
HOLD
19
13
E2
SO
Serial Data Output
20
14
F2
A0
Device Address, LSB
21
15
F1
NC
No Connect
22
16
D2
NC
No Connect
23
17
E1
NC
No Connect
24
18
D1
NC
No Connect
Hold
Wiper
RW:
The RW pins are equivalent to the wiper terminal of a
mechanical potentiometer.
CS
CS:
Chip Select
CS is the Chip select pin. CS low enables the
CAT5411 and CS high disables the CAT5411. CS high
takes the SO output pin to high impedance and forces the devices into a Standby mode (unless an internal write operation is
underway). The CAT5411 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any
sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle.
WP
WP:
Write Protect
WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low, all
non-volatile write operations to the Data registers are inhibited (change of wiper control register is allowed). WP going low while
CS is still low will interrupt a write to the registers. If the internal write cycle has already been initiated, WP going low will have no
effect on any write operation.
HOLD
HOLD: Hold
The HOLD pin is used to pause transmission to the CAT5411 while in the middle of a serial sequence without having to retransmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is
brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high
directly to VCC or tied to VCC through a resistor.
Document No. 2114, Rev. F
2
CAT5411
SERIAL BUS PROTOCOL
After the device is selected with CS going low the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK. The
first byte contains one of the six op-codes that define the
operation to be performed.
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5411 to interface directly with many
of today's popular microcontrollers. The CAT5041
contains an 8-bit instruction register .The instruction set
and the operation codes are detailed in the instruction
set table 3.
DEVICE OPERATION
The CAT5411 is two resistor arrays integrated with SPI
serial interface logic, four 6-bit wiper control registers
and eight 6-bit, non-volatile memory data registers.
Each resistor array contains 63 separate resistive
elements connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (RH and RL). RH and RL are
symmetrical and may be interchanged. The tap positions
between and at the ends of the series resistors are
connected to the output wiper terminals (RW) by a
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a time
and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the SPI bus. Additional instructions allows data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
3
Document No. 2114, Rev. G
CAT5411
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions outside of those listed in the operational sections
of this specification is not implied. Exposure to any absolute
maximum rating for extended periods may affect device performance and reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on any Pin with
Respect to VSS(1)(2) ................ -2.0V to +VCC +2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Recommended Operating Conditions:
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
VCC = +2.5V to +6.0V
Temperature
Industrial
Lead Soldering Temperature (10 secs) ............ 300°C
Min
-40°C
Max
85°C
Wiper Current .................................................. +12mA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
RPOT
Potentiometer Resistance (-00)
Test Conditions
Min
Typ
100
kΩ
RPOT
Potentiometer Resistance (-50)
50
kΩ
RPOT
Potentiometer Resistance (-10)
10
kΩ
RPOT
Potentiometer Resistance (-2.5)
2.5
kΩ
Potentiometer Resistance
Max
Units
+20
%
1
%
50
mW
+6
mA
300
Ω
150
Ω
VCC
V
Tolerance
RPOT Matching
Power Rating
25°C, each pot
IW
Wiper Current
RW
Wiper Resistance
IW = +3mA @ VCC =3V
RW
Wiper Resistance
IW = +3mA @ VCC = 5V
VTERM
Voltage on any RH or RL Pin
VSS = 0V
Noise
(1)
VN
Resolution
80
GND
nV/ Hz
1.6
%
Rw(n)(actual)-R(n)(expected)(5)
+1
LSB (4)
Relative Linearity (3)
Rw(n+1)-[Rw(n)+LSB](5)
+0.2
LSB (4)
TCRPOT
Temperature Coefficient of
RPOT
(1)
TCRATIO
Ratiometric Temp. Coefficient
(1)
CH/CL/CW
Potentiometer Capacitances
(1)
10/10/25
pF
fc
Frequency Response
RPOT = 50kΩ(1)
0.4
MHz
Absolute Linearity
(2)
+300
ppm/°C
20
ppm/°C
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = RTOT / 63 or (RH - RL) / 63, single pot
(5) n = 0, 1, 2, ..., 63
Document No. 2114, Rev. F
4
CAT5411
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
fSCK = 2MHz, SO Open
Inputs = GND
1
mA
VIN = GND or VCC; SO Open
1
µA
VIN = GND to VCC
10
µA
VOUT = GND to VCC
10
µA
ICC
Power Supply Current
ISB
Standby Current (VCC = 5.0V)
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL
Input Low Voltage
-1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
0.4
V
VOL1
Output Low Voltage (VCC = 3.0V)
IOL = 3 mA
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Min
Max
Units
Output Capacitance (SO)
8
pF
VOUT=0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN=0V
5
Typ
Conditions
Document No. 2114, Rev. G
CAT5411
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Test
SYMBOL
PARAMETER
Min
Typ
Max
UNITS
tSU
Data Setup Time
50
ns
tH
Data Hold Time
50
ns
tWH
SCK High Time
125
ns
tWL
SCK Low Time
125
ns
fSCK
Clock Frequency
DC
tLZ
3
MHz
HOLD to Output Low Z
50
ns
tRI(1)
Input Rise Time
2
µs
tFI(1)
Input Fall Time
2
µs
tHD
HOLD Setup Time
100
ns
tCD
HOLD Hold Time
100
ns
tWC
Write Cycle Time
10
ms
tV
Output Valid from Clock Low
250
ns
tHO
Output Hold Time
tDIS
Output Disable Time
250
ns
tHZ
HOLD to Output High Z
100
ns
tCS
CS High Time
250
ns
tCSS
CS Setup Time
250
ns
tCSH
CS Hold Time
250
ns
0
ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
POWER UP TIMING (1)
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Document No. 2114, Rev. F
6
Conditions
CL = 50pF
CAT5411
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol
tWR
Parameter
Min
Typ
Write Cycle Time
Max
Units
5
ms
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Reference Test Method
Min
NEND(1)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
Data Retention
MIL-STD-883, Test Method 1008
100
Years
VZAP(1)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
ILTH(1)(2)
Latch-Up
JEDEC Standard 17
100
mA
TDR
(1)
Typ
Max
Units
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Figure 1. Sychronous Data Timing
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWL
tWH
SCK
VIL
tH
tSU
VIH
VALID IN
SI
VIL
tRI
tFI
tV
VOH
SO
tHO
tDIS
HI-Z
HI-Z
VOL
Note: Dashed Line= mode (1, 1) — — — —
Figure 2. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
HIGH IMPEDANCE
SO
tLZ
7
Document No. 2114, Rev. G
CAT5411
INSTRUCTION AND REGISTER
DESCRIPTION
INSTRUCTION BYTE
The next byte sent to the CAT5411 contains the instruction
and register pointer information. The four most significant
bits used provide the instruction opcode I [3:0]. The R1
and R0 bits point to one of the four data registers of each
associated potentiometer. The least two significant bits
point to one of two Wiper Control Registers. The format
is shown in Table 2.
DEVICE TYPE / ADDRESS BYTE
The first byte sent to the CAT5411 from the master/
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a
device type identifier. These bits for the CAT5411 are
fixed at 0101[B] (refer to Table 1).
Data Register Selection
Data Register Selected
The two least significant bits in the slave address byte,
A1 - A0, are the internal slave address and must match
the physical device address which is defined by the state
of the A1 - A0 input pins for the CAT5411 to successfully
continue the command sequence. Only the device which
slave address matches the incoming device address
sent by the master executes the instruction. The A1 - A0
inputs can be actively driven by CMOS input signals or
tied to VCC or VSS. The remaining two bits in the device
address byte must be set to 0.
R1
R0
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
Table 1. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
ID2
ID1
ID0
0
1
0
1
0
0
A1
(MSB)
A0
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
I3
I2
Data Register
Selection
I1
I0
R1
(MSB)
Document No. 2114, Rev. F
R0
WCR/Pot Selection
0
P0
(LSB)
8
CAT5411
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data Registers
is a non-volatile operation and will take a maximum of
5ms.
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The CAT5411 contains two 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of 64
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written by
the host via Write Wiper Control Register instruction;
it may be written by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction, it can be modified one step at a
time by the Increment/decrement instruction (see
Instruction section for more details). Finally, it is
loaded with the content of its data register zero (DR0)
upon power-up.
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS input goes HIGH after
a write sequence is received. The status of the internal
write cycle can be monitored by issuing a Read Status
command to read the Write in Process (WIP) bit.
INSTRUCTIONS
Five of the ten instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register - read the current
wiper position of the selected potentiometer in the WCR
The Wiper Control Register is a volatile register that
loses its contents when the CAT5411 is powered-down.
Although the register is automatically loaded with the
value in DR0 upon power-up, this may be different from
the value present at power-down.
— Write Wiper Control Register - change current
wiper position in the WCR of the selected potentiometer
— Read Data Register - read the contents of the
selected Data Register
Data Registers (DR)
— Write Data Register - write a new value to the
selected Data Register
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
— Read Status - Read the status of the WIP bit which
Table 3. Instruction Set
Instruction Set
Instruction
I3
I2
I1
I0
R1
R0
0
WCR0/
P0
Read Wiper Control
Register
Write Wiper Control Register
1
0
0
1
0
0
0
1/0
1
0
1
0
0
0
0
1/0
Read Data Register
1
0
1
1
1/0
1/0
0
1/0
Write Data Register
1
1
0
0
1/0
1/0
0
1/0
XFR Data Register to Wiper
Control Register
1
1
0
1
1/0
1/0
0
1/0
XFR Wiper Control Register
to Data Register
1
1
1
0
1/0
1/0
0
1/0
Global XFR Data Registers
to Wiper Control Registers
0
0
0
1
1/0
1/0
0
0
Global XFR Wiper Control
Registers to Data Register
1
0
0
0
1/0
1/0
0
0
Increment/Decrement Wiper
Control Register
0
0
1
0
0
0
0
1/0
Read Status (WIP bit)
0
1
0
1
0
0
0
1
Note:
Operation
Read the contents of the Wiper Control
Register pointed to by P0
Write new value to the Wiper Control
Register pointed to by P0
Read the contents of the Data Register
pointed to by P0 and R1-R0
Write new value to the Data Register
pointed to by P0 and R1-R0
Transfer the contents of the Data Register
pointed to by P0 and R1-R0 to its
associated Wiper Control Register
Transfer the contents of the Wiper Control
Register pointed to by P0 to the Data
Register pointed to by R1-R0
Transfer the contents of the Data Registers
pointed to by R1-R0 of all four pots to their
respective Wiper Control Register
s
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1-R0 of all four pots
Enable Increment/decrement of the Control
Latch pointed to by P0
Read WIP bit to check internal
write cycle status
1/0 = data is one or zero
9
Document No. 2114, Rev. G
CAT5411
when set to "1" signifies a write cycle is in progress.
— Global XFR Data Register to Wiper
Control Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be delayed
by tWRL. A transfer from the WCR (current wiper position),
to a Data Register is a write to non-volatile memory and
takes a minimum of tWR to complete. The transfer can
occur between one of the potentiometers and one of its
associated registers; or the transfer can occur between
both potentiometers and one associated register.
— Global XFR Wiper Counter Register to
Data Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 5
and 9). The Increment/Decrement command is different
from the other commands. Once the command is issued
the master can clock the selected wiper up and/or down
in one segment steps; thereby providing a fine tuning
capability to the host. For each SCK clock pulse (tHIGH)
while SI is HIGH, the selected wiper will move one
resistor segment towards the RH terminal. Similarly, for
each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the RL
terminal.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5411; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated
Data Register.
See Instructions format for more detail.
Figure 7. Two-Byte Instruction Sequence
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0 A3 A2 A1 A0 I3
Internal
Address
Device ID
I2
I1
I0
P0
R1 R0 0
Instruction
Opcode
Register
Address
Pot/WCR
Address
Figure 8. Three-Byte Instruction Sequence
SI
0
1
0
1
ID3 ID2 ID1 ID0 A3
A2
A1
A0 I3
Internal
Address
Device ID
I2
I1 I0
R1 R0
Instruction
Opcode
0
P0
D7 D6 D5 D4 D3 D2 D1 D0
Data
Pot/WCR
Register Address
Address
WCR[7:0]
or
Data Register D[7:0]
Figure 9. Increment/Decrement Instruction Sequence
SI
0
1
0
1
ID3 ID2 ID1 ID0
Device ID
Document No. 2114, Rev. F
A3
A2 A1 A0
Internal
Address
I3
I2
I1
Instruction
Opcode
10
I0
R1 R0
0
P0
I
N
Pot/WCR C
Data
Register Address 1
Address
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
CAT5411
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
tWRID
SCK
SI
Voltage Out
RW
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
DEVICE ADDRESSES
CS
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 0 0 1 0 0 0 P0 7 6 5
4
3
2 1 0
CS
3
2 1 0
CS
2 1
0
CS
2 1
0
CS
0 0
Write Wiper Control Register (WCR)
DEVICE ADDRESSES
CS
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 0 0 1 0 0 0 P0 7 6 5
4
0 0
Read Data Register (DR)
DEVICE ADDRESSES
CS
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 0 1 1 R1 R0 0 P0 7 6 5 4 3
Write Data Register (DR)
DEVICE ADDRESSES
CS
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 1 0 0 R1 R0 0 P0 7 6 5 4 3
High Voltage
Write Cycle
Read (WIP) Status
DEVICE ADDRESSES
CS
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 0 1 0 1 0 0 0 1 7 6 5
4 3
0 0 0 0
0
2
1
W
0
0
I
CS
P
11
Document No. 2114, Rev. G
CAT5411
INSTRUCTION FORMAT (continued)
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
CS
0 1 0 1
INSTRUCTION
0 0 A1 A0 0 0 0 1 R1 R0 0 0
CS
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
CS
0 1 0 1
INSTRUCTION
0 0 A1 A0 1 0 0 0 R1 R0 0 0
CS
High Voltage
Write Cycle
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
CS
0 1 0 1
INSTRUCTION
0 0 A1 A0 1 1 1 0 R1 R0 0 P0
CS
High Voltage
Write Cycle
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
CS
0 1 0 1 0
INSTRUCTION
0 A1 A0 1 1 0 1 R1 R0 0 P0
CS
Increment (I)/Decrement (D) Wiper Control Register (WCR)
DEVICE ADDRESSES
CS
0 1 0 1 0
INSTRUCTION
DATA
0 A1 A0 0 0 1 0 0 0 0 P0 I/D I/D
I/D I/D
• • •
CS
Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after CS goes high.
Document No. 2114, Rev. F
12
CAT5411
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
5411
J
Optional
Company ID
Product
Number
I
Package
J: SOIC
B: BGA
U: TSSOP
W: SOIC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
-10
-TE13
Tape & Reel
TE13: 2000/Reel
Resistance
-25: 2.5kohm
-10: 10kohm
-50: 50kohm
-00: 100kohm
Temperature Range
I = Industrial (-40 C to 85 C)
Notes:
(1) The device used in the above example is a CAT5411JI-10-TE13 (SOIC, Industrial Temperature, 10kohm, Tape & Reel)
PACKAGING INFORMATION
24-LEAD 300 MIL WIDE SOIC (J)
0.2914 (7.40)
0.2992 (7.60)
0.394 (10.00)
0.419 (10.65)
0.5985 (15.20)
0.6141 (15.60)
0.0926 (2.35)
0.1043 (2.65)
0.050 (1.27) BSC
0.013 (0.33)
0.020 (0.51)
0.0040 (0.10)
0.0118 (0.30)
0.010 (0.25)
X 45
0.029 (0.75)
0.0091 (0.23)
0.0125 (0.32)
0 —8
0.016 (0.40)
0.050 (1.27)
13
Document No. 2114, Rev. G
CAT5411
PACKAGING INFORMATION CON'T
24 Lead TSSOP (U)
7.8 + 0.1
-A-
7.72 TYP
6.4
4.16 TYP
4.4 + 0.1
-B(1.78 TYP)
3.2
0.42 TYP
0.65 TYP
0.2 C B A
ALL LEAD TIPS
PIN #1 INDENT.
1.1 MAX TYP
LAND PATTERN RECOMMENDATION
0.1 C
ALL LEAD TIPS
(0.9)
-C0.10 + 0.05 TYP
0.65 TYP
0.19 - 0.30 TYP
0.3 M A B S C S
SEE DETAIL A
GAGE PLANE
0.25
0.09 - 0.20 TYP
o
o
0-8
0.6+0.1
SEATING PLANE
DETAIL A
Document No. 2114, Rev. F
14
CAT5411
PACKAGING INFORMATION CON'T
24 Ball BGA
a
a
1
2
j
3
m
4
4
3
2
A
A
B
B
k
C
b
1
C
D
D
E
E
F
F
f
Top View (Bump Side Down)
b
Bottom View (Bump Side Up)
Note: Drawing not to scale
= Die orientation mark
d
c
e
Side View (Bump Side Down)
Millimeters
Inches
Symbol
Min
Nom
Max
Nom
Min
Max
Package Body Dimension X
a
TBD
TBD
TBD
TBD
TBD
TBD
Package Body Dimension Y
b
TBD
TBD
TBD
TBD
TBD
TBD
Package Height
c
0.635
0.505
0.765
0.02500
0.01988
0.03012
Package Body Thickness
d
0.433
0.395
0.471
0.01705
0.01555
0.01854
Ball Height
e
0.202
0.110
0.294
0.00795
0.00433
0.01157
Ball Diameter
f
0.284
0.180
0.388
0.01118
0.00709
0.01528
Total Ball Count
g
24
Ball Count X Axis
h
4
Ball Count Y Axis
i
6
Pins Pitch X Axis
j
0.5
Pins Pitch Y Axis
k
0.5
Edge to Ball Center (Corner)
Distance Along X
l
TBD
TBD
TBD
TBD
TBD
TBD
Edge to Ball Center (Corner)
Distance Along Y
m
TBD
TBD
TBD
TBD
TBD
TBD
15
Document No. 2114, Rev. G
REVISION HISTORY
Date
Rev.
Reason
04/01/04
G
Eliminate data sheet designation
Update Features
Update Description
Update Pin Description
Update Absolute Maximum Ratings
Update Recommended Operating Conditions
Update Potentiometer Characteristics
Update Reliability Characteristics
Update Ordering Information
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Issue date:
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G
4/01/04
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