Maxim MAX1166BCUP Low-power, 16-bit analog-to-digital converters with parallel interface Datasheet

19-2551; Rev 2; 8/08
Low-Power, 16-Bit Analog-to-Digital Converters
with Parallel Interface
The MAX1165/MAX1166 16-bit, low-power, successiveapproximation analog-to-digital converters (ADCs) feature automatic power-down, factory-trimmed internal
clock, and a 16-bit wide (MAX1165) or byte wide
(MAX1166) parallel interface. The devices operate from
a single +4.75V to +5.25V analog supply and a +2.7V
to +5.25V digital supply.
The MAX1165/MAX1166 use an internal 4.096V reference or an external reference. The MAX1165/MAX1166
consume only 1.8mA at a sampling rate of 165ksps with
external reference and 2.7mA with internal reference.
AutoShutdown™ reduces supply current to 0.1mA at
10ksps.
The MAX1165/MAX1166 are ideal for high-performance, battery-powered, data-acquisition applications.
Excellent dynamic performance and low power consumption in a small package make the MAX1165/
MAX1166 ideal for circuits with demanding power consumption and space requirements.
The 16-bit wide MAX1165 is available in a 28-pin
TSSOP package and the byte wide MAX1166 is available in a 20-pin TSSOP package. Both devices are
available in either the 0°C to +70°C commercial, or the
-40°C to +85°C extended temperature range.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Applications
Temperature Sensor/Monitor
Features
♦ 16-Bit Wide (MAX1165) and Byte Wide (MAX1166)
Parallel Interface
♦ High Speed: 165ksps Sample Rate
♦ Accurate: ±2.5 LSB INL, 16 Bit No Missing Codes
♦ 4.096V, 25ppm/°C Internal Reference
♦ External Reference Range: +3.8V to +5.25V
♦ Single +4.75V to +5.25V Analog Supply Voltage
♦ +2.7V to +5.25V Digital Supply Voltage
♦ Low Supply Current
1.8mA (External Reference)
2.7mA (Internal Reference)
0.1µA (10ksps, External Reference)
♦ Small Footprint
28-Pin TSSOP Package (16-Bit Wide)
20-Pin TSSOP Package (Byte Wide)
Ordering Information
TEMP RANGE
PINPACKAGE
INL
MAX1165ACUI
0°C to +70°C
28 TSSOP
±2
MAX1165BCUI
0°C to +70°C
28 TSSOP
±2
MAX1165CCUI
0°C to +70°C
28 TSSOP
±4
MAX1165AEUI
-40°C to +85°C
28 TSSOP
±2.5
MAX1165BEUI
-40°C to +85°C
28 TSSOP
±2.5
MAX1165CEUI
-40°C to +85°C
28 TSSOP
±4
PART
Ordering Information continued at end of data sheet.
Industrial Process Control
I/O Boards
Typical Operating Circuit
Data-Acquisition Systems
Cable/Harness Tester
+5V ANALOG
+5V DIGITAL
Accelerometer Measurements
0.1µF
Digital Signal Processing
0.1µF
µP DATA
BUS
Pin Configurations and Functional Diagram appear at end of
data sheet.
ANALOG INPUT
AIN
DVDD
D0–D15
AVDD
MAX1165
EOC
R/C
CS
RESET
REF
REFADJ
AGND DGND
0.1µF
4.7µF
________________________________________________________________ Maxim Integrated Products
1
For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1165/MAX1166
General Description
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND ........................................-0.3V to (AVDD + 0.3V)
AGND to DGND.....................................................-0.3V to +0.3V
AIN, REF, REFADJ to AGND....................-0.3V to (AVDD + 0.3V)
CS, HBEN, R/C, RESET to DGND ............................-0.3V to +6V
Digital Output (D15–D0, EOC)
to DGND ..............................................-0.3V to (DVDD + 0.3V)
Maximum Continuous Current Into Any Pin ........................50mA
Continuous Power Dissipation (TA = +70°C)
20-Pin TSSOP (derate 10.9mW/°C above+70°C) ........879mW
28-Pin TSSOP (derate 12.8mW/°C above +70°C) .....1026mW
Operating Temperature Ranges
MAX116_ _CU_ ...................................................0°C to +70°C
MAX116_ _EU_ ................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
N
16
TA = -40°C
Relative Accuracy
(Note 1)
INL
TA = 0°C
TA = +85°C
-2.5
+2.5
MAX116_B
-2.5
+2.5
MAX116_C
-4
+4
MAX116_A
-2
+2
MAX116_B
-2
+2
MAX116_C
-4
+4
MAX116_A
-2
+2
MAX116_B
-2
+2
MAX116_C
TA = -40°C
No missing
codes
-4
+4
MAX116_A
-1
+2
MAX116_B
-1
+2
-2
+2
MAX116_A
-1
+1.5
MAX116_B
-1
+1.5
MAX116_C
Differential Nonlinearity
DNL
TA = 0°C
No missing
codes
MAX116_C
TA = +85°C
No missing
codes
-2
+2
MAX116_A
-1
+1
MAX116_B
-1
+1.5
-2
+2
MAX116_C
RMS noise, external reference, includes
quantization noise
Transition Noise
0.65
Internal reference
(Note 2)
LSB
LSB
LSBRMS
0.7
Offset Error
Gain Error
Bits
MAX116_A
LSBRMS
0.05
1
±0.002
±0.02
mV
%FSR
Offset Drift
0.6
ppm/°C
Gain Drift
0.2
ppm/°C
90
dB
DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 1kHz, VIN = 4.096VP-P, 165ksps)
Signal-to-Noise Plus Distortion
2
SINAD
86
_______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Sample Rate
Aperture Delay
Aperture Jitter
ANALOG INPUT
Input Range
Input Capacitance
INTERNAL REFERENCE
REF Output Voltage
REF Output Tempco
REF Short-Circuit Current
Capacitive Bypass at REFADJ
Capacitive Bypass at REF
REFADJ Input Leakage Current
EXTERNAL REFERENCE
SYMBOL
SNR
THD
SFDR
CONDITIONS
91
-3dB point
SINAD > 81dB
TYP
90
-102
105
4
33
fSAMPLE
MAX
-90
VAIN
CAIN
0
VREF
TCREF
IREFSC
CREFADJ
CREF
IREFADJ
4.054
ksps
ns
ps
VREF
V
pF
4.136
V
ppm/°C
mA
µF
µF
µA
40
0.1
1
20
To power down the internal reference
REF Input Voltage Range
Internal reference disabled (Note 3)
IREF
4.096
±25
±10
UNITS
dB
dB
dB
MHz
kHz
165
27
<100
REFADJ Buffer Disable Threshold
REF Input Current
MIN
87
AVDD 0.4
AVDD 0.1
V
3.8
AVDD 0.2
V
VREF = +4.096V, fSAMPLE = 165ksps
Shutdown mode
14
±0.1
25
µA
DIGITAL INPUTS/OUTPUTS
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage Current
Input Hysteresis
Input Capacitance
IIN
VHYST
CIN
0.7 ×
DVDD
V
0.3 ×
DVDD
VIH = 0 or DVDD
Output High Voltage
VOH
ISOURCE = 0.5mA, DVDD = +2.7V to +5.25V,
AVDD = +5.25V
Output Low Voltage
VOL
ISINK = 1.6mA, DVDD = +2.7V to +5.25V,
AVDD = +5.25V
Three-State Leakage Current
IOZ
D0–D15
±0.1
0.1
15
±1
DVDD 0.4
V
µA
V
pF
V
±0.1
0.4
V
±10
µA
_______________________________________________________________________________________
3
MAX1165/MAX1166
ELECTRICAL CHARACTERISTICS (continued)
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply
SYMBOL
COZ
CONDITIONS
AVDD
DVDD
IAVDD
External reference
Digital Supply Current
IDVDD
D0–D15 = all zeros
Full power-down
Shutdown Supply Current
Power-Supply Rejection Ratio
ISHDN
PSRR
TYP
15
4.75
2.7
Internal reference
Analog Supply Current
MIN
REF and REF buffer enabled
(standby mode)
165ksps
100ksps
10ksps
1ksps
165ksps
100ksps
10ksps
1ksps
165ksps
100ksps
10ksps
1ksps
IAVDD
IDVDD
IAVDD
3.2
2.6
1.9
1.8
2.4
1.8
0.8
0.08
0.5
0.3
0.03
0.003
0.5
0.5
1.0
IDVDD
(Note 4)
0.5
AVDD = +5V ±5%, full-scale input (Note 5)
MAX
UNITS
pF
5.25
AVDD
3.6
V
V
2.8
mA
0.7
mA
5
6
1.2
mA
5
µA
68
µA
dB
TIMING CHARACTERISTICS (Figures 1 and 2)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to AVDD, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, CLOAD = 20pF,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
Acquisition Time
tACQ
Conversion Time
tCONV
CS Pulse Width High
tCSH
CS Pulse Width Low (Note 6)
tCSL
R/C to CS Fall Setup Time
tDS
R/C to CS Fall Hold Time
tDH
CS to Output Data Valid
tDO
HBEN Transition to Output Data
Valid (MAX1166 Only)
tDO1
EOC Fall to CS Fall
4
tDV
CONDITIONS
MIN
TYP
MAX
1.1
4.7
(Note 6)
40
VDVDD = 4.75V to 5.25V
40
VDVDD = 2.7V to 5.25V
60
40
VDVDD = 2.7V to 5.25V
60
ns
ns
ns
VDVDD = 4.75V to 5.25V
40
VDVDD = 2.7V to 5.25V
80
VDVDD = 4.75V to 5.25V
40
VDVDD = 2.7V to 5.25V
80
0
_______________________________________________________________________________________
µs
ns
0
VDVDD = 4.75V to 5.25V
UNITS
ns
ns
ns
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to AVDD, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, CLOAD = 20pF,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CS Rise to EOC Rise
CONDITIONS
tEOC
Bus Relinquish Time (Note 6)
tBR
MIN
TYP
MAX
VDVDD = 4.75V to 5.25V
40
VDVDD = 2.7V to 5.25V
80
VDVDD = 4.75V to 5.25V
40
VDVDD = 2.7V to 5.25V
80
UNITS
ns
ns
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 2: Offset nulled.
Note 3: Guaranteed by design, not production tested.
Note 4: Shutdown supply currents are typically 0.5µA, maximum specification is limited by automated test equipment.
Note 5: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply.
Note 6: To ensure best performance, finish reading the data and wait tBR before starting a new acquisition.
Typical Operating Characteristics
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, TA = +25°C, unless otherwise noted.)
INL vs. OUTPUT CODE
DNL (LSB)
0.5
1.0
0
0.5
0
-0.5
-0.5
-1.0
-1.0
-1.5
-1.5
MAX1165/66 toc03
1.0
1.5
10
1
SUPPLY CURRENT (mA)
1.5
MAX1165/66 toc02
2.0
MAX1165/66 toc01
2.0
INL (LSB)
IAVDD + IDVDD SUPPLY CURRENT
vs. SAMPLE RATE
DNL vs. OUTPUT CODE
0.1
0.01
0.001
-2.0
-2.0
16384
32768
49152
65536
16384
32768
49152
66536
0.1
1
10
100
OUTPUT CODE
SAMPLE RATE (ksps)
IAVDD + IDVDD SUPPLY CURRENT
vs. TEMPERATURE
IAVDD + IDVDD SHUTDOWN CURRENT
vs. TEMPERATURE
INTERNAL REFERENCE
vs. TEMPERATURE
2.0
1.5
1.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
SAMPLE RATE = 165ksps
0
-20
0
20
40
TEMPERATURE (°C)
60
80
1000
4.136
MAX1165/66 toc06
4.5
4.126
INTERNAL REFERENCE (V)
2.5
5.0
MAX1165/66 toc05
MAX1165/66 toc04
3.0
-40
0.01
OUTPUT CODE
3.5
SUPPLY CURRENT (mA)
0.0001
0
SHUTDOWN CURRENT (µA)
0
4.116
4.106
4.096
4.086
4.076
4.066
0.5
4.056
0
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX1165/MAX1166
TIMING CHARACTERISTICS (Figures 1 and 2) (continued)
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, TA = +25°C, unless otherwise noted.)
GAIN ERROR
vs. TEMPERATURE
0.015
400
200
0
-200
-400
0.010
80
70
0.005
0
60
50
40
-0.005
30
-0.010
-600
20
-800
-0.015
10
-1000
-0.020
0
-40
-20
0
20
40
80
60
-40
-20
TEMPERATURE (°C)
0
20
40
60
-40
SFDR (dB)
THD (dB)
-30
-50
-60
-70
-80
-90
-100
1
0.1
10
100
MAX1165/66 toc11
SAMPLE RATE = 165ksps
0.1
FREQUENCY (kHz)
100
SNR (dB)
-40
-60
-80
-100
-120
-140
60
80
80
70
60
50
40
30
20
10
0
MAX1165/66 toc13
120
110
100
90
MAX1165/66 toc12
SAMPLE RATE = 165ksps
-20
40
10
SNR vs. FREQUENCY
FFT AT 1kHz
FREQUENCY (kHz)
1
FREQUENCY (kHz)
0
20
10
80
70
60
50
40
30
20
10
0
-110
MAGNITUDE (dB)
1
FREQUENCY (kHz)
120
110
100
90
MAX1165/66 toc10
-20
0
0.1
80
SFDR vs. FREQUENCY
SAMPLE RATE = 165ksps
-10
SAMPLE RATE = 165ksps
TEMPERATURE (°C)
THD vs. FREQUENCY
0
6
90
SINAD (dB)
GAIN ERROR (%FSR)
600
100
MAX1165/66 toc08
800
SINAD vs. FREQUENCY
0.020
MAX1165/66 toc07
1000
MAX1165/66 toc09
OFFSET ERROR
vs. TEMPERATURE
OFFSET ERROR (µV)
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
SAMPLE RATE = 165ksps
0.1
1
10
FREQUENCY (kHz)
_______________________________________________________________________________________
100
100
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
PIN
NAME
FUNCTION
MAX1165
MAX1166
MAX1165 MAX1166
1
1
D8
D4/D12
Three-State Digital Data Output
2
2
D9
D5/D13
Three-State Digital Data Output
3
3
D10
D6/D14
Three-State Digital Data Output
4
4
D11
D7/D15
5
—
D12
—
Three-State Digital Data Output
6
—
D13
—
Three-State Digital Data Output
7
—
D14
—
Three-State Digital Data Output
8
—
D15
—
Three-State Digital Data Output (MSB)
Three-State Digital Data Output. D15 is the MSB.
Read/Convert Input. Power up and put the MAX1165/MAX1166 in acquisition mode
by holding R/C low during the first falling edge of CS. During the second falling
edge of CS, the level on R/C determines whether the reference and reference
buffer power down or remain on after conversion. Set R/C high during the second
falling edge of CS to power down the reference and buffer, or set R/C low to leave
the reference and buffer powered up. Set R/C high during the third falling edge of
CS to put valid data on the bus.
9
5
R/C
10
6
EOC
End of Conversion. EOC drives low when conversion is complete.
11
7
AVDD
Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.
12
8
AGND
13
9
AIN
14
10
AGND
15
11
REFADJ
16
12
REF
17
—
RESET
Reset Input. Logic high resets the device.
High-Byte Enable Input. Used to multiplex the 14-bit conversion result:
1: Most significant byte available on the data bus.
0: Least significant byte available on the data bus.
Analog Ground. Primary analog ground (star ground).
Analog Input
Analog Ground. Connect pin 14 to pin 12 (MAX1165). Connect pin 10 to pin 8
(MAX1166).
Reference Buffer Output. Bypass REFADJ with a 0.1µF capacitor to AGND for internal
reference mode. Connect REFADJ to AVDD to select external reference mode.
Reference Input/Output. Bypass REF with a 4.7µF capacitor to AGND for internal
reference mode. External reference input when in external reference mode.
—
13
HBEN
18
14
CS
19
15
DGND
Digital Ground
20
16
DVDD
Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.
21
17
D0
22
18
23
19
24
Convert Start. The first falling edge of CS powers up the device and enables
acquire mode when R/C is low. The second falling edge of CS starts conversion.
The third falling edge of CS loads the result onto the bus when R/C is high.
D0/D8
Three-State Digital Data Output
D1
D1/D9
Three-State Digital Data Output
D2
D2/D10
Three-State Digital Data Output
20
D3
D3/D11
Three-State Digital Data Output
25
—
D4
—
Three-State Digital Data Output
26
—
D5
—
Three-State Digital Data Output
27
—
D6
—
Three-State Digital Data Output
28
—
D7
—
Three-State Digital Data Output
_______________________________________________________________________________________
7
MAX1165/MAX1166
Pin Description
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
Analog Input
DVDD
The equivalent input circuit is shown in Figure 4. A
switched capacitor digital-to-analog converter (DAC)
provides an inherent T/H function. The single-ended
input is connected between AIN and AGND.
1mA
D0–D15
D0–D15
CLOAD = 20pF
Input Bandwidth
CLOAD = 20pF
1mA
The ADC’s input-tracking circuitry has a 4MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use anti-alias filtering.
DGND
DGND
a) HIGH-Z TO VOH, VOL TO VOH,
AND VOH TO HIGH-Z
b) HIGH-Z TO VOL, VOH TO VOL,
AND VOL TO HIGH-Z
Figure 1. Load Circuits
Detailed Description
Converter Operation
The MAX1165/MAX1166 use a successive-approximation (SAR) conversion technique with an inherent trackand-hold (T/H) stage to convert an analog input into a
16-bit digital output. Parallel outputs provide a highspeed interface to most microprocessors (µPs). The
Functional Diagram shows a simplified internal architecture of the MAX1165/MAX1166. Figure 3 shows a
typical application circuit for the MAX1166.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to AVDD and/or AGND, allow the input to swing
from AGND - 0.3V to AVDD + 0.3V, without damaging
the device.
If the analog input exceeds 300mV beyond the supplies, limit the input current to 10mA.
tCSH
tCSL
CS
tACQ
REF POWERDOWN BIT
R/C
tDH
tDS
tDV
tEOC
EOC
tCONV
HIGH-Z
D0–D15
tBR
tDO
HIGH-Z
DATA VALID
HBEN*
tDO1
D8/D15–
D0/D7*
HIGH-/LOWBYTE VALID
tBR
HIGH-/LOWBYTE VALID
*HBEN AND BYTE-WIDE DATA BUS
AVAILABLE ON MAX1166 ONLY.
Figure 2. MAX1165/MAX1166 Timing Diagram
8
_______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
REF
+5V DIGITAL
TRACK
ZERO
CSWITCH
3pF
AVDD
ANALOG INPUT
µP DATA
BUS
DVDD
HOLD
AGND
D0–D7
OR
D8–D15
AIN
CAPACITIVE DAC
AIN
0.1µF
0.1µF
CDAC = 32pF
RIN
800Ω
HOLD
TRACK
AUTOZERO
RAIL
MAX1166
EOC
R/C
CS
HIGH
BYTE
HBEN
REF
Figure 4. Equivalent Input Circuit
REFADJ
AGND DGND
0.1µF
4.7µF
LOW
BYTE
Figure 3. Typical Application Circuit for the MAX1166
Track and Hold (T/H)
In track mode, the analog signal is acquired on the internal hold capacitor. In hold mode, the T/H switches open
and the capacitive DAC samples the analog input.
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition ends on the second
falling edge of CS. At this instant, the T/H switches
open. The retained charge on CDAC represents a sample of the input.
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion time to restore node ZERO
to zero within the limits of 16-bit resolution. Force CS low
to put valid data on the bus at the end of the conversion.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal. Use the following formula to calculate acquisition time:
tACQ = 11 (RS + RIN) ✕ 35pF
where R IN = 800Ω, R S = the input signal’s source
impedance, and t ACQ is never less than 1.1µs. A
source impedance less than 1kΩ does not significantly
affect the ADC’s performance.
To improve the input signal bandwidth under AC conditions, drive AIN with a wideband buffer (>4MHz) that
can drive the ADC’s input capacitance and settle
quickly.
Power-Down Modes
Select standby mode or shutdown mode with the R/C
bit during the second falling edge of CS (see the
Selecting Standby or Shutdown Mode section). The
MAX1165/MAX1166 automatically enter either standby
mode (reference and buffer on) or shutdown (reference
and buffer off) after each conversion depending on the
status of R/C during the second falling edge of CS.
Internal Clock
The MAX1165/MAX1166 generate an internal conversion clock. This frees the microprocessor from the burden of running the SAR conversion clock. Total
conversion time after entering hold mode (second
falling edge of CS) to end of conversion (EOC) falling is
4.7µs (max).
Applications Information
Starting a Conversion
CS and R/C control acquisition and conversion in the
MAX1165/MAX1166 (Figure 2). The first falling edge of
CS powers up the device and puts it in acquire mode if
R/C is low. The convert start is ignored if R/C is high.
The MAX1165/MAX1166 need at least 10ms
(CREFADJ = 0.1µF, CREF = 4.7µF) for the internal reference to wake up and settle before starting the conversion if powering up from shutdown. The ADC can wake
up, from shutdown, to an unknown state. Put the ADC
in a known state by completing one “dummy” conversion. The MAX1165/MAX1166 are in a known state,
ready for actual data acquisition, after the completion
of the dummy conversion. A dummy conversion consists of one full conversion cycle.
The MAX1165 provides an alternative reset function to
reset the device (see the RESET section).
_______________________________________________________________________________________
9
MAX1165/MAX1166
+5V ANALOG
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
ACQUISITION
CS
CONVERSION
DATA
OUT
CS
REF POWERDOWN BIT
CONVERSION
ACQUISITION
R/C
R/C
EOC
EOC
REF
AND
BUFFER
REF
AND
BUFFER
DATA
OUT
REF POWERDOWN BIT
Figure 6. Selecting Shutdown Mode
Figure 5. Selecting Standby Mode
Selecting Standby or Shutdown Mode
The MAX1165/MAX1166 have a selectable standby or
low-power shutdown mode. In standby mode, the
ADC’s internal reference and reference buffer do not
power down between conversions, eliminating the need
to wait for the reference to power up before performing
the next conversion. Shutdown mode powers down the
reference and reference buffer after completing a conversion. The reference and reference buffer require a
minimum of 10ms (CREFADJ = 0.1µF, CREF = 4.7µF) to
power up and settle from shutdown.
The state of R/C at the second falling edge of CS
selects which power-down mode the MAX1165/
MAX1166 enter upon conversion completion. Holding
R/C low causes the MAX1165/MAX1166 to enter standby mode. The reference and buffer are left on after the
conversion completes. R/C high causes the MAX1165/
MAX1166 to enter shutdown mode and shut down the
reference and buffer after conversion (Figures 5 and 6).
When using an external reference, set the REF powerdown bit high for lowest current operation.
Standby Mode
While in standby mode, the supply current is reduced
to less than 1mA (typ). The next falling edge of CS with
R/C low causes the MAX1165/MAX1166 to exit standby
mode and begin acquisition. The reference and reference buffer remain active to allow quick turn-on time.
Standby mode allows significant power savings while
running at the maximum sample rate.
causes the reference and buffer to wake up and enter
acquisition mode. To achieve 16-bit accuracy, allow
10ms (CREFADJ = 0.1µF, CREF = 4.7µF) for the internal
reference to wake up.
Internal and External Reference
Internal Reference
The internal reference of the MAX1165/MAX1166 is
internally buffered to provide +4.096V output at REF.
Bypass REF to AGND and REFADJ to AGND with 4.7µF
and 0.1µF, respectively.
Fine adjustments can be made to the internal reference
voltage by sinking or sourcing current at REFADJ. The
input impedance of REFADJ is nominally 5kΩ. The
internal reference voltage is adjustable to ±1.5% with
the circuit of Figure 7.
+5V
68kΩ
100kΩ
MAX1165
MAX1166
REFADJ
0.1µF
150kΩ
Figure 7. MAX1165/MAX1166 Reference Adjust Circuit
Shutdown Mode
In shutdown mode, the reference and reference buffer
are shut down between conversions. Shutdown mode
reduces supply current to 0.5µA (typ) immediately after
the conversion. The falling edge of CS with R/C low
10
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1165/
MAX1166s’ internal buffer amplifier. When connecting an
______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
For optimal performance, buffer the reference through
an op amp and bypass REF with a 1µF capacitor.
Consider the MAX1165/MAX1166s’ equivalent input
noise (38µVRMS) when choosing a reference.
Reading a Conversion Result
EOC is provided to flag the microprocessor when a conversion is complete. The falling edge of EOC signals
that the data is valid and ready to be output to the bus.
D0–D15 are the parallel outputs of the MAX1165/
MAX1166. These three-state outputs allow for direct
connection to a microcontroller I/O bus. The outputs
remain high-impedance during acquisition and conversion. Data is loaded onto the bus with the third falling
edge of CS with R/C high after tDO. Bringing CS high
forces the output bus back to high impedance. The
MAX1165/MAX1166 then wait for the next falling edge
of CS to start the next conversion cycle (Figure 2).
The MAX1165 loads the conversion result onto a 16-bit
wide data bus while the MAX1166 has a byte-wide output format. HBEN toggles the output between the
most/least significant byte. The least significant byte is
loaded onto the output bus when HBEN is low and the
most significant byte is on the bus when HBEN is high
(Figure 2).
OUTPUT CODE
FULL-SCALE
TRANSITION
11...111
11...110
11...101
FS = VREF
1 LSB = VREF
65536
00...011
00...010
00...001
00...000
0
1
2
3
FS
INPUT VOLTAGE (LSB) FS - 3/2LSB
Figure 8. MAX1165/MAX1166 Transfer Function
plexed, the input channel should be switched immediately after acquisition, rather than near the end of or
after a conversion. This allows more time for the input
buffer amplifier to respond to a large step change in
input signal. The input amplifier must have a high
enough slew rate to complete the required output voltage change before the beginning of the acquisition
time. At the beginning of acquisition, the internal sampling capacitor array connects to AIN (the amplifier output), causing some output disturbance. Ensure that the
sampled voltage has settled to within the required limits
before the end of the acquisition time. If the frequency
of interest is low, AIN can be bypassed with a large
enough capacitor to charge the internal sampling
capacitor with very little ripple. However, for AC use,
AIN must be driven by a wideband buffer (at least
10MHz), which must be stable with the ADC’s capacitive load (in parallel with any AIN bypass capacitor
used) and also settle quickly. An example of this circuit
using the MAX4434 is given in Figure 9.
RESET
Toggle RESET with CS high. The next falling edge of CS
begins acquisition. This reset is an alternative to the
dummy conversion explained in the Starting a Conversion
section.
Transfer Function
Figure 8 shows the MAX1165/MAX1166 output transfer
function. The output is coded in standard binary.
MAX1165
MAX1166
10Ω
AIN
ANALOG
INPUT
40pF
MAX4434
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy. If the input signal is multi-
Figure 9. MAX1165/MAX1166 Fast Settling Input Buffer
______________________________________________________________________________________
11
MAX1165/MAX1166
external reference to REFADJ, the input impedance is
typically 5kΩ. Using the buffered REFADJ input makes
buffering the external reference unnecessary; however,
the internal buffer output must be bypassed at REF with
a 1µF capacitor.
Connect REFADJ to AVDD to disable the internal buffer.
Directly drive REF using an external reference. During
conversion the external reference must be able to drive
100µA of DC load current and have an output impedance of 10Ω or less. REFADJ’s impedance is typically
5kΩ. The DC input impedance of REF is a minimum
40kΩ.
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do
not run analog and digital lines parallel to each other,
and do not lay out digital signal paths underneath the
ADC package. Use separate analog and digital ground
planes with only one point connecting the two ground
systems (analog and digital) as close to the device as
possible.
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
onto the analog lines. If the analog and digital sections
share the same supply, then isolate the digital and analog supply by connecting them with a low-value (10Ω)
resistor or ferrite bead.
The ADC is sensitive to high-frequency noise on the
AV DD supply. Bypass AV DD to AGND with a 0.1µF
capacitor in parallel with a 1µF to 10µF low-ESR capacitor with the smallest capacitor closest to the device.
Keep capacitor leads short to minimize stray inductance.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1165/MAX1166
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of ±1 LSB guarantees no missing codes and a monotonic transfer function.
Aperture Jitter and Delay
Aperture jitter is the sample-to-sample variation in the
time between samples. Aperture delay is the time
between the rising edge of the sampling clock and the
instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
12
noise error only and results directly from the ADC’s resolution (N bits):
SNR = (6.02 ✕ N + 1.76)dB
where N = 16 bits.
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
⎡
⎤
SignalRMS
SINAD (dB) = 20 × log ⎢
⎥
⎣ (Noise + Distortion)RMS ⎦
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number
of bits as follows:
ENOB =
SINAD − 1.76
6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
⎡⎛
2
2
2
2⎞⎤
⎢ ⎜ V2 + V3 + V4 + V5 ⎟ ⎥
⎝
⎠⎥
THD = 20 × log ⎢
⎢
⎥
V1
⎢
⎥
⎢⎣
⎥⎦
where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest frequency component.
______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
HBEN*
REFADJ
AVDD AGND DVDD DGND
5kΩ
REFERENCE
OUTPUT
REGISTERS
16 OR 8*
16 OR 8*
D0–D15
OR
D0/D7–D8/D15*
REF
AIN
CAPACITIVE
DAC
MAX1165
MAX1166
AGND
RESET**
SUCCESSIVEAPPROXIMATION
REGISTER AND
CONTROL LOGIC
CLOCK
CS
EOC
R/C
* BYTE WIDE (MAX1166 ONLY)
**16-BIT WIDE (MAX1165 ONLY)
Ordering Information (continued)
TEMP RANGE
PINPACKAGE
INL
MAX1166ACUP
0°C to +70°C
20 TSSOP
±2
MAX1166BCUP
0°C to +70°C
20 TSSOP
±2
MAX1166CCUP
0°C to +70°C
20 TSSOP
±4
MAX1166AEUP
-40°C to +85°C
20 TSSOP
±2.5
MAX1166BEUP
-40°C to +85°C
20 TSSOP
±2.5
MAX1166CEUP
-40°C to +85°C
20 TSSOP
±4
PART
Chip Information
TRANSISTOR COUNT: 15,140
PROCESS: BiCMOS
______________________________________________________________________________________
13
MAX1165/MAX1166
Functional Diagram
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
MAX1165/MAX1166
Pin Configurations
TOP VIEW
D8 1
28 D7
D4/D12 1
20 D3/D11
D9 2
27 D6
D5/D13 2
19 D2/D10
D10 3
26 D5
D6/D14 3
18 D1/D9
D11 4
25 D4
D7/D15 4
17 D0/D8
MAX1166
24 D3
R/C 5
23 D2
EOC 6
D14 7
22 D1
AVDD 7
14 CS
D15 8
21 D0
AGND 8
13 HBEN
D12 5
D13 6
MAX1165
R/C 9
20 DVDD
AIN 9
EOC 10
19 DGND
AGND 10
AVDD 11
18 CS
AGND 12
17 RESET
AIN 13
16 DVDD
15 DGND
12 REF
11 REFADJ
TSSOP
16 REF
AGND 14
15 REFADJ
TSSOP
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
14
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
28 TSSOP
U28-1
21-0066
20 TSSOP
U20-2
21-0066
______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
PAGES
CHANGED
REVISION
NUMBER
REVISION
DATE
0
7/02
Initial release
1
2/07
Modified specifications due to inclusion of reference buffer
1–4, 13, 15
2
8/08
Modified specifications for GBD at -40°C
1, 2, 3, 13
DESCRIPTION
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
MAX1165/MAX1166
Revision History
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