Infineon ICE1PCS02 Standalone power factor correction (pfc) controller in continuous conduction mode (ccm) Datasheet

Datasheet, V1.2, 06 Feb 2007
CCM-PFC
ICE1PCS02
ICE1PCS02G
Standalone Power Factor
Correction (PFC) Controller in
Continuous Conduction Mode
(CCM) with Input Brown-Out
Protection
Pow e r M a na ge m e nt & S upply
N e v e r
s t o p
t h i n k i n g .
CCM-PFC
Revision History:
2007-02-06
Previous Version:
V 1.1
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Datasheet
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Edition 2007-02-06
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CCM-PFC
ICE1PCS02
ICE1PCS02G
Standalone Power Factor Correction (PFC)
Controller in Continuous Conduction Mode
(CCM) with Input Brown-Out Protection
ICE1PCS02
PG-DIP-8
Product Highlights
•
•
•
•
•
•
•
Leadfree DIP and DSO Package
Wide Input Range
Direct sensing, Input Brown-Out Detection
Optimized for applications which require fast Startup
Output Power Controllable by External Sense Resistor
Fast Output Dynamic Response during Load Jumps
Trimmed, internal fixed Switching Frequency (65kHz)
ICE1PCS02G
test
PG-DSO-8
Features
Description
•
•
•
•
The ICE1PCS02/G is a 8-pin wide input range controller
IC for active power factor correction converters. It is designed for converters in boost topology, and requires few
external components. Its power supply is recommended
to be provided by an external auxiliary supply which will
switch on and off the IC.
The IC operates in the CCM with average current control,
and in DCM only under light load condition. The switching
frequency is trimmed and fixed internally at 65kHz. Both
current and voltage loop compensations are done externally to allow full user control.
There are various protection features incorporated to ensure safe system operation conditions. The internal reference is trimmed (5V+2%) to ensure precise protection and
output control level.
The ICE1PCS02/G is a design variant of ICE1PCS01 to
incorporate the new input brown-out protection function
and optimised to have a faster startup time with controlled
peak startup current.
•
•
•
•
•
•
•
•
•
•
•
•
Ease of Use with Few External Components
Supports Wide Input Range
Average Current Control
External Current and Voltage Loop Compensation
for Greater User Flexibility
Trimmed internal fixed Switching Frequency
(65kHz+7.7% at 25oC)
Direct sensing, Input Brown-Out Detection
with Hysteresis
Short Startup(SoftStart) duration
Max Duty Cycle of 97% (typ)
Trimmed Internal Reference Voltage (5V+2%)
VCC Under-Voltage Lockout
Cycle by Cycle Peak Current Limiting
Over-Voltage Protection
Open Loop Detection
Soft Overcurrent Protection
Enhanced Dynamic Response
Fulfills Class D Requirements of IEC 1000-3-2
Typical Application
VOUT
Auxiliary Supply
85 ... 265 VAC
VCC
EMI-Filter
CCM PFC
VINS
Brown-out
GATE
PWM Logic
Driver
Fixed
Oscillator
ICOMP
Current Loop
Compensation
ISENSE
Type
Package
ICE1PCS02
PG-DIP-8
ICE1PCS02G
PG-DSO-8
Version 1.2
3
ICE1PCS02 /G
Protection Unit
Voltage Loop
Compensation
Ramp
Generator
VSENSE
VCOMP
Nonlinear
Gain
GND
06 Feb 2007
CCM-PFC
ICE1PCS02/G
1
1.1
1.2
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2
Representative Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.7
3.8
3.8.1
3.8.2
3.9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Input Brown-Out Protection (IBOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Soft Over Current Control (SOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Open Loop Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Over-Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Fixed Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Nonlinear Gain Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Enhanced Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5
Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Version 1.2
4
06 Feb 2007
CCM-PFC
ICE1PCS02/G
Pin Configuration and Functionality
1
Pin Configuration and Functionality
1.1
Pin Configuration
Pin
ICOMP (Current Loop Compensation)
Low pass filter and compensation of the current control
loop. The capacitor which is connected at this pin
integrates the output current of OTA2 and averages the
current sense signal.
Symbol
Function
1
GND
IC Ground
2
ICOMP
Current Loop Compensation
3
ISENSE
Current Sense Input
4
VINS
5
VCOMP
6
VSENSE VOUT Sense (Feedback) Input
ISENSE (Current Sense Input)
The ISENSE Pin senses the voltage drop at the
external sense resistor (R1). This is the input signal for
the average current regulation in the current loop. It is
also fed to the peak current limitation block.
During power up time, high inrush currents cause high
voltage drop at R1, driving currents into pin 3 which
could be beyond the absolute maximum ratings.
Therefore a series resistor (R2) of around 220Ω is
recommended in order to limit this current into the IC.
Brown-out Sense Input
Voltage Loop Compensation
7
VCC
IC Supply Voltage
8
GATE
Gate Drive Output
VINS (Brown-out Sense Input)
This VINS pin senses a filtered input voltage divider
and detects for the input voltage Brown-out condition.
A Brown-out condition of VINS<0.8V, shuts down the
IC. The IC turns on at VINS>1.5V.
Package PG-DIP-8 / PG-DSO-8
GND
1
8
GATE
ICOMP
2
7
VCC
ISENSE
3
6
VSENSE
VINS
4
5
VCOMP
Figure 1
1.2
VSENSE (Voltage Sense/Feedback)
The output bus voltage is sensed at this pin via a
resistive divider. The reference voltage for this pin is
5V.
VCOMP (Voltage Loop Compensation)
This pin provides the compensation of the output
voltage loop with a compensation network to ground
(see Figure 2).
VCC (Power Supply)
The VCC pin is the positive supply of the IC and should
be connected to an external auxiliary supply. The
operating range is between 10V and 21V. The turn-on
threshold is at 11.2V and under voltage occurs at
10.2V. There is no internal clamp for a limitation of the
power supply.
Pin Configuration (top view)
GATE
The GATE pin is the output of the internal driver stage,
which has a capability of 1.5A source and sink current.
Its gate drive voltage is internally clamped at 11.5V
(typically).
Pin Functionality
GND (Ground)
The ground potential of the IC.
Version 1.2
5
06 Feb 2007
Figure 2
Version 1.2
6
C3
ICOMP
ISENSE
C2
Fault
S2
OTA2
4.0V
1.1mS
+/-50uA linear range
Current Loop
Compensation
Current Loop
OP1
-1.43x
Current Sense
Opamp
1.5V
Over-current
Comparator
Peak Current Limit
250ns
OSC CLK
Deglitcher
300ns
Toff min
Fixed 65kHz Oscillator
R2
D2 ... D5
GND
C1
R
S
R
S
R7
Nonlinear
Gain
C1
PWM
Comparator
Ramp Generator
PWM Logic
R1
L1
D1
C2
0
-ve
0
S
R
5.25V
-ve
Window Detect
+ve
4.75V
Soft Over
Current Control
0.73 V
Voltage Loop
Fault
Protection
Logic
R4
R3
VCC
0.8V
OTA1
5V
1.5V
0.8V
+/-30uA, 42uS
S1
Fault
C5
C4
Brown-Out Detection
C3
open-loop protect
UVLO
undervoltage lockout
Protection Block
Gate Driver
VCC
auxiliary supply
D6
GATE
R9
D7
C4
R6
C5
VCOMP
C6
VINS
R8
VSENSE
Vout
2
ICE1PCS02/G
Vin
85 ... 265 VAC
RFI Filter
CCM-PFC
ICE1PCS02/G
Representative Block diagram
Representative Block diagram
Representative Block diagram
06 Feb 2007
CCM-PFC
ICE1PCS02/G
3
Functional Description
Functional Description
3.1
General
If VCC drops below 10.2V, the IC is off. The IC will then
be consuming typically 200µA, whereas consuming
18mA during normal operation.
The IC can be turned off and forced into standby mode
by pulling down the voltage at pin 6 (VSENSE) to lower
than 0.8V. In this standby mode, the current
consumption is reduced to 3mA. Other condition that
can result in the standby mode is when a Brown-out
condition occurs, ie pin 4 (VINS) <0.8V.
The ICE1PCS02/G is a 8 pin control IC for power factor
correction converters. It comes in both DIP and DSO
packages and is suitable for wide range line input
applications from 85 to 265 VAC. The IC supports
converters in boost topology and it operates in
continuous conduction mode (CCM) with average
current control.
It is a design derivative from the ICE1PCS01/G with the
differences in the supporting functions, namely the
input brown-out detection, internal fixed switching
frequency 65kHz and shortened startup time.
The IC operates with a cascaded control; the inner
current loop and the outer voltage loop. The inner
current loop of the IC controls the sinusoidal profile for
the average input current. It uses the dependency of
the PWM duty cycle on the line input voltage to
determine the corresponding input current. This means
the average input current follows the input voltage as
long as the device operates in CCM. Under light load
condition, depending on the choke inductance, the
system may enter into discontinuous conduction mode
(DCM) resulting in a higher harmonics but still meeting
the Class D requirement of IEC 1000-3-2.
The outer voltage loop controls the output bus voltage.
Depending on the load condition, OTA1 establishes an
appropriate voltage at VCOMP pin which controls the
amplitude of the average input current.
The IC is equipped with various protection features to
ensure safe operating condition for both the system
and device.
3.3
Start-up
Figure 4 shows the operation of voltage loop’s OTA1
during startup. The VCOMP pin is pull internally to
ground via switch S1 during UVLO and other fault
conditions (see later section on “System Protection”).
During power up when VOUT is less than 85% of the
rated level, it sources a constant 30µA into the
compensation network at pin 5 (VCOMP) causing the
voltage at this pin to rise linearly. This results in a
controlled linear increase of the input current from 0A
thus reducing the stress on the external component.
VSENSE
(
R4
x VOUT )
R3 + R4
+/-30uA, 42uS
OTA1
5V
VCOMP
3.2
S1
Power Supply
R6
An internal under voltage lockout (UVLO) block
monitors the VCC power supply. As soon as it exceeds
11.2V and both voltages at pin 6 (VSENSE) >0.8V and
pin 4 (VINS) >1.5V, the IC begins operating its gate
drive and performs its Startup as shown in Figure 3.
.
(VVSENSE > 0.8 V)
(VVSENSE < 0.8 V)
fault
C4
Figure 4
C5
ICE1PCS02/G
Startup Circuit
As VOUT has not reached within 5% from the rated
value, VCOMP voltage is level-shifted by the window
detect block as shown in Figure 5, to ensure there is no
long period of low or no current.
When VOUT approaches its rated value, OTA1’s
sourcing current drops and so does the level shift of the
window detect block. The normal voltage loop then
takes control.
(VVSENSE > 0.8 V)
AND (VVINS > 1.5 V) OR (VVINS < 0.8 V) AND (VVINS > 1.5 V)
VCC
11.2 V
10.5 V
t
IC's
State
OFF
Figure 3
Start Normal
Up Operation
Open loop/
Standby
Normal
Operation
OFF
State of Operation respect to VCC
Version 1.2
7
06 Feb 2007
CCM-PFC
ICE1PCS02/G
Functional Description
.
Window Detect
VOUT
VOUT,Rated
Normal Control
105%
100%
Max Vcomp current
VOUT =rated
VOUT
16%
95%rated
t
85%rated
Supply
related
Current
related
Output
related OLP
t
av(IIN)
Level-shifted VCOMP
VCOMP
Figure 6
t
Figure 5
PCL / SOC
OVP
OLP
Protection Features
3.4.1
Input Brown-Out Protection (IBOP)
Brown-out occurs when the input voltage VIN falls below
the minimum input voltage of the design (i.e. 85V for
universal input voltage range) and the VCC has not
entered into the VCCUVLO level yet. For a system without
IBOP, the boost converter will increasingly draw a
higher current from the mains at a given output power
which may exceed the maximum design values of the
input current.
ICE1PCS02/G provides a new IBOP feature whereby it
senses directly the input voltage for Input Brown-Out
condition via an external resistor/capacitor/diode
network as shown in Figure 7. This network provides a
filtered value of VIN which turns the IC on when the
voltage at pin 4 (VINS) is more than 1.5V. The IC enters
into the standby mode when VINS goes below 0.8V.
The hysteresis prevents the system to oscillate
between normal and standby mode. Note also that VIN
needs to at least 16% of the rated VOUT in order to
overcome OLP and powerup the system.
Startup with controlled maximum current
ICE1PCS02/G is different from ICE1PCS01/G in this
block as it does not has a reduced current (~10uA in
ICE1PCS01/G) during startup. The OTA1 in
ICE1PCS02/G has the same maximum source current
of 30uA (typ) in startup as in the normal operation. This
higher sourcing current in the startup time, will charge
VCOMP faster to its normal operating point, which in
turn results in a faster startup for VOUT.
3.4
UVLO / IBOP
System Protection
The IC provides several protection features in order to
ensure the PFC system in safe operating range:
• VCC Undervoltage Lockout (UVLO)
• Input Brown-out Detection (IBOP)
• Soft Over Current Control (SOC)
• Peak Current Limit (PCL)
• Open-Loop Detection (OLP)
• Output Over-Voltage Protection (OVP)
After the system is supplied with the correct level of
VCC and VIN, the system will enter into its normal mode
of operation. Figure 6 shows situation when these
protections features are active, as a function of the
output voltage VOUT.
An activation of the UVLO, IBOP and OLP results in the
internal fault signal going high and brings the IC into the
standby mode.
As the function of UVLO has already described in the
earlier “Power Supply” section, the following sections
continue to describe the functionality of these
protection features.
D2 ... D5
Vin
85 ... 265 VAC
C1
R8
Brown-Out Detection
C4
brown-out
S
R
0.8V
VINS
D7
20k
C5
1.5V
5V
C6
R9
ICE1PCS02/G
Figure 7
Version 1.2
8
Input Brown-Out Protection (IBOP)
06 Feb 2007
CCM-PFC
ICE1PCS02/G
Functional Description
3.5
3.4.2
Soft Over Current Control (SOC)
The IC is designed not to support any output power
that corresponds to a voltage lower than -0.73V at the
ISENSE pin. A further increase in the inductor current,
which results in a lower ISENSE voltage, will activate
the Soft Over Current Control (SOC). This is a soft
control as it does not directly switch off the gate drive
like the PCL. It acts on the nonlinear gain block to result
in a reduced PWM duty cycle.
Fixed Switching Frequency
ICE1PCS02/G has an internally fixed switching
frequency as opposed to the ICE1PCS01/G which can
be externally set. This frequency is trimmed to 65kHz
with an accuracy +/-7.7% at 25oC.
3.6
Average Current Control
3.6.1
Complete Current Loop
The complete system current loop is shown in Figure 9.
3.4.3
Peak Current Limit (PCL)
The IC provides a cycle by cycle peak current limitation
(PCL). It is active when the voltage at pin 3 (ISENSE)
reaches -1.08V. This voltage is amplified by OP1 by a
factor of -1.43 and connected to comparator C2 with a
reference voltage of 1.5V as shown in Figure 8. A
deglitcher with 300ns after the comparator improves
noise immunity to the activation of this protection.
L1
From
Full-wave
Retifier
D1
R3
Vout
C2
R7
R4
R2
R1
GATE
ISENSE
Current Limit
Full-wave
Rectifier
1.5V
ISENSE
Current Loop
Deglitcher
C2
300ns
ICOMP
Turn Off
Driver
Current Loop
Compensation
OTA2
R2
1.43x
C3
IINDUCTOR
OP1
voltage
proportional to
averaged
Inductor current
Gate
Driver
PWM
Comparator
R Q
S
C1
PWM Logic
1.1mS
+/-50uA (linear range)
S2
4V
R1
Nonlinear
Gain
Input From
Voltage Loop
Fault
ICE1PCS02/G
Figure 8
ICE1PCS02/G
Figure 9
Peak Current Limit (PCL)
It consists of the current loop block which averages the
voltage at pin ISENSE, resulted from the inductor
current flowing across R1. The averaged waveform is
compared with an internal ramp in the ramp generator
and PWM block. Once the ramp crosses the average
waveform, the comparator C1 turns on the driver stage
through the PWM logic block. The Nonlinear Gain block
defines the amplitude of the inductor current. The
following sections describe the functionality of each
individual blocks.
3.4.4
Open Loop Protection (OLP)
Whenever VSENSE voltage falls below 0.8V, or
equivalently VOUT falls below 16% of its rated value, it
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage VIN for
normal operation. In this case, most of the blocks within
the IC will be shutdown. It is implemented using
comparator C3 with a threshold of 0.8V as shown in the
IC block diagram in Figure 2.
3.6.2
Current Loop Compensation
The compensation of the current loop is done at the
ICOMP pin. This is the OTA2 output and a capacitor C3
has to be installed at this node to ground (see Figure
9). Under normal mode of operation, this pin gives a
voltage which is proportional to the averaged inductor
current. This pin is internally shorted to 4V in the event
of standby mode.
3.4.5
Over-Voltage Protection (OVP)
Whenever VOUT exceeds the rated value by 5%, the
over-voltage protection OVP is active as shown in
Figure 6. This is implemented by sensing the voltage at
pin VSENSE with respect to a reference voltage of
5.25V. A VSENSE voltage higher than 5.25V will
immediately reduce the output duty cycle, bypassing
the normal voltage loop control. This results in a lower
input power to reduce the output voltage VOUT.
Version 1.2
Complete System Current Loop
3.6.3
Pulse Width Modulation (PWM)
The IC employs an average current control scheme in
continuous conduction mode (CCM) to achieve the
power factor correction.
9
06 Feb 2007
CCM-PFC
ICE1PCS02/G
Functional Description
3.6.4
Nonlinear Gain Block
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
voltage at pin VCOMP. This block has been designed
to support the wide input voltage range (85-265VAC).
Assuming the voltage loop is working and output
voltage is kept constant, the off duty cycle DOFF for a
CCM PFC system is given as
V IN
D OFF = ------------V OUT
From the above equation, DOFF is proportional to VIN.
The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle DOFF, and thus to the input voltage
VIN. Figure 10 shows the scheme to achieve the
objective.
3.7
The PWM logic block prioritizes the control input
signals and generates the final logic signal to turn on
the driver stage. The speed of the logic gates in this
block, together with the width of the reset pulse TOFFMIN,
are designed to meet a maximum duty cycle DMAX of
95% at the GATE output.
In case of high input currents which result in Peak
Current Limitation, the GATE will be turned off
immediately and maintained in off state for the current
PWM cycle. The signal Toffmin resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 12.
ave(IIN) at ICOMP
ramp profile
GATE
drive
Peak Current
Limit
t
Figure 10
Average Current Control in CCM
Current Loop
PWM on signal
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 5
(ICOMP). The PWM cycle starts with the Gate turn off
for a duration of TOFFMIN (250ns typ.) and the ramp is
kept discharged. The ramp is then allowed to rise after
TOFFMIN expires. The off time of the boost transistor
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle DOFF.
Figure 11 shows the timing diagrams of TOFFMIN and the
PWM waveforms.
Figure 12
3.8
PWM cycle
VCREF(1)
HIGH =
turn GATE on
PWM on
Latch
S
L2
R
Q
PWM Logic
Voltage Loop
3.8.1
Voltage Loop Compensation
The compensation of the voltage loop is installed at the
VCOMP pin (see Figure 13). This is the output of OTA1
and the compensation must be connected at this pin to
ground. The compensation is also responsible for the
soft start function which controls an increasing AC input
current during start-up.
ramp
released
PWM
t
VCREF is a function of VICOMP
Figure 11
G1
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage VOUT. This loop is closed by the feedback
sensing voltage at VSENSE which is a resistive divider
tapping from VOUT. The pin VSENSE is the input of
OTA1 which has an accurate internal reference of 5V
(+/-2%). Figure 13 shows the important blocks of this
voltage loop.
TOFFMIN
VRAMP
Current
Limit Latch
Q
S
L1
R
Toffmin
250ns
250ns
(1)
PWM Logic
Ramp and PWM waveforms
Version 1.2
10
06 Feb 2007
CCM-PFC
ICE1PCS02/G
Functional Description
From
Full-wave
Retifier
L1
D1
R3
VCC
Vout
C2
R7
PWM Logic
HIGH to
turn on
R4
Gate Driver
LV
External
MOS
Z1
Gate Driver
Current Loop
+
PWM Generation
GATE
GATE
VIN
Nonlinear
Gain
Av(IIN)
OTA1
* LV: Level Shift
ICE1PCS02/G
5V
t
VSENSE
Figure 14
The output is active HIGH and at VCC voltages below
the under voltage lockout threshold VCCUVLO, the gate
drive is internally pull low to maintain the off state.
VCOMP
ICE1PCS02/G
Gate Driver
R6
C4
Figure 13
C5
Voltage Loop
3.8.2
Enhanced Dynamic Response
Due to the low frequency bandwidth of the voltage loop,
the dynamic response is slow and in the range of about
several 10ms. This may cause additional stress to the
bus capacitor and the switching transistor of the PFC in
the event of heavy load changes.
The IC provides therefore a “window detector” for the
feedback voltage VVSENSE at pin 6 (VSENSE).
Whenever VVSENSE exceeds the reference value (5V)
by +5%, it will act on the nonlinear gain block which in
turn affect the gate drive duty cycle directly. This
change in duty cycle is bypassing the slow changing
VCOMP voltage, thus results in a fast dynamic
response of VOUT.
3.9
Output Gate Driver
The output gate driver is a fast totem pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 14) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 8 (GATE) is typically
clamped at 11.5V.
Version 1.2
11
06 Feb 2007
CCM-PFC
ICE1PCS02/G
Electrical Characteristics
4
Electrical Characteristics
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit.
Parameter
Symbol
Limit Values
min.
max.
Unit
Remarks
VCC Supply Voltage
VCC
-0.3
22
V
VINS Voltage
VVINS
-0.3
20
V
ICOMP Voltage
VICOMP
-0.3
7
V
ISENSE Voltage
VISENSE
-24
7
V
ISENSE Current
IISENSE
-1
1
mA
VSENSE Voltage
VVSENSE
-0.3
7
V
VSENSE Current
IVSENSE
-1
1
mA
VCOMP Voltage
VVCOMP
-0.3
7
V
GATE Voltage
VGATE
-0.3
22
V
Junction Temperature
Tj
-40
150
°C
Storage Temperature
TS
-55
150
°C
Thermal Resistance
Junction-Ambient for PG-DSO-8
RthJA (DSO)
-
185
K/W
PG-DSO-8
Thermal Resistance
Junction-Ambient for PG-DIP-8
RthJA(DIP)
-
90
K/W
PG-DIP-8
ESD Protection
VESD
-
2
kV
Human Body Model1)
1)
Recommended R2=220Ω
R3>400kΩ
Clamped at 11.5V(typ)
if driven internally.
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor)
4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description.
Parameter
Symbol
Limit Values
min.
Unit
max.
VCC Supply Voltage
VCC
VCCUVLO 21
V
Junction Temperature
TJCon
-40
°C
Version 1.2
12
Remarks
125
06 Feb 2007
CCM-PFC
ICE1PCS02/G
Electrical Characteristics
4.3
Note:
4.3.1
Characteristics
The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range TJ from – 40 °C to 125°C.Typical values represent the median values, which are
related to 25°C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition.
Supply Section
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
VCC Turn-On Threshold
VCCon
10.5
11.2
11.9
V
VCC Turn-Off Threshold/
Under Voltage Lock Out
VCCUVLO
9.4
10.2
10.8
V
VCC Turn-On/Off Hysteresis
VCChy
0.8
1
1.3
V
Start Up Current
Before VCCon
ICCstart
50
100
200
µA
VVCC=VVCCon -0.1V
Operating Current with active GATE
ICCHG
9.6
13
16.3
mA
CL= 4.7nF
Operating Current during Standby
ICCStdby
1.7
2.3
2.9
mA
VVSENSE= 0.5V
4.3.2
PWM Section
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
fSW
56
65
72
kHz
fSW
60
65
70
kHz
Max. Duty Cycle
DMAX
94
97
99.3
%
Min. Duty Cycle
DMIN
0
%
VVCOMP= 0V, VVSENSE= 5V
VICOMP= 6.4V
Min. Off Time
TOFFMIN
600
ns
VVCOMP= 5V, VVSENSE= 5V
VISENSE= 0.1V
Fixed Oscillator Frequency
Version 1.2
100
13
250
max.
Tj = 25°C
06 Feb 2007
CCM-PFC
ICE1PCS02/G
Electrical Characteristics
4.3.3
System Protection Section
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
Open Loop Protection (OLP)
VSENSE Threshold
VOLP
0.77
0.81
0.86
V
Peak Current Limitation (PCL)
ISENSE Threshold
VPCL
-1.15
-1.08
-1.00
V
Soft Over Current Control (SOC)
ISENSE Threshold
VSOC
-0.79
-0.73
-0.66
V
Output Over-Voltage Protection (OVP)
VOVP
5.12
5.25
5.38
V
Input Brown-out Protection (IBOP)
High to Low Threshold
VVINSL
0.76
0.82
0.88
V
Input Brown-out Protection (IBOP)
Low to High Threshold
VVINSH
1.40
1.50
1.60
V
Input Brown-out Protection (IBOP)
VINS Bias Current
IVIN0V
-1.0
-0.2
0
µA
4.3.4
Current Loop Section
Parameter
Symbol
Limit Values
min.
OTA2 Transconductance Gain
GmOTA2
OTA2 Output Linear Range1)
IOTA2
ICOMP Voltage during OLP
VICOMPF
1)
VVINS= 0V
0.75
3.6
typ.
0.95
Unit Test Condition
max.
1.15
mS
+/- 50
µA
4.0
V
At Temp = 25°C
VVSENSE= 0.5V
The parameter is not subject to production test - verified by design/characterization
Version 1.2
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06 Feb 2007
CCM-PFC
ICE1PCS02/G
Electrical Characteristics
4.3.5
Voltage Loop Section
Parameter
Symbol
Limit Values
min.
OTA1 Reference Voltage
typ.
Unit Test Condition
max.
VOTA1
4.90
5.00
5.10
V
OTA1 Transconductance Gain
GmOTA1
31.5
42
52.5
µS
OTA1 Max. Source Current
At Startup
IOTA1SO1
21
30
38
µA VVSENSE= 4V
VVCOMP= 0V
OTA1 Max. Source Current
Under Normal Operation
IOTA1SO
21
30
38
µA
VVSENSE= 4.25V
VVCOMP= 4V
OTA1 Max. Sink Current
Under Normal Operation
IOTA1SK
21
30
38
µA
VVSENSE= 6V
VVCOMP= 4V
VHi
VLo
5.12
4.63
5.25
4.75
5.38
4.87
V
V
VSENSE Input Bias Current at 5V
IVSEN5V
0
1.5
µA
VVSENSE= 5V
VSENSE Input Bias Current at 1V
IVSEN1V
0
1
µA
VVSENSE= 1V
VVCOMPF
0
0.4
V
VVSENSE= 0.5V
IVCOMP= 0.5mA
Enhanced Dynamic Response
VSENSE High Threshold
VSENSE Low Threshold
VCOMP Voltage during OLP
Version 1.2
15
0.2
06 Feb 2007
CCM-PFC
ICE1PCS02/G
Electrical Characteristics
4.3.6
Driver Section
Parameter
Symbol
GATE Low Voltage
VGATEL
GATE High Voltage
VGATEH
Limit Values
Unit Test Condition
min.
typ.
max.
-
-
1.2
V
VCC = 5 V
IGATE = 5 mA
-
-
1.5
V
VCC = 5 V
IGATE = 20 mA
-
0.8
-
V
IGATE = 0 A
-
1.6
2.0
V
IGATE = 20 mA
-0.2
0.2
-
V
IGATE = -20 mA
-
11.5
-
V
VCC = 20V
CL = 4.7nF
-
10.5
-
V
VCC = 11V
CL = 4.7nF
-
7.5
-
V
VCC = VVCCoff + 0.2V
CL = 4.7nF
GATE Rise Time
tr
-
60
-
ns
VGate = 2V ...8V
CL = 4.7nF
GATE Fall Time
tf
-
40
-
ns
VGate = 8V ...2V
CL = 4.7nF
GATE Current, Peak,
Rising Edge
IGATE
-1.5
-
-
A
CL = 4.7nF1)
GATE Current, Peak,
Falling Edge
IGATE
-
-
1.5
A
CL = 4.7nF1)
1)
Design characteristics (not meant for production testing)
Version 1.2
16
06 Feb 2007
CCM-PFC
ICE1PCS02/G
Outline Dimension
5
Outline Dimension
PG-DIP-8-4
(Plastic Dual In-Line Package)
Dimensions in mm
Figure 15 PG-DIP-8 Outline Dimension
PG-DSO-8-13
(Plastic Dual Small Outline)
1.27
0.1
0.41 +0.1
-0.05
+0.05
-0.01
0.2
C
0.2 M A C x8
8
5
Index
Marking 1
4
5 -0.21)
8˚ MAX.
4 -0.21)
1.75 MAX.
0.1 MIN.
(1.5)
0.33 ±0.08 x 45˚
0.64 ±0.25
6 ±0.2
A
Index Marking (Chamfer)
1)
Dimensions in mm
Does not include plastic or metal protrusion of 0.15 max. per side
Figure 16 PG-DSO-8 Outline Dimension
Version 1.2
17
06 Feb 2007
Total Quality Management
Qualität hat für uns eine umfassende
Bedeutung. Wir wollen allen Ihren
Ansprüchen in der bestmöglichen
Weise gerecht werden. Es geht uns also
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For us it means living up to each and
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Geisteshaltung unserer Mitarbeiter.
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Ihnen, unserem Kunden. Unsere
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