Hitachi HM51W16400 4,194,304-word x 4-bit dynamic ram Datasheet

HM51W16400 Series
HM51W17400 Series
4,194,304-word × 4-bit Dynamic RAM
ADE-203-649C (Z)
Rev. 3.0
Feb. 27, 1997
Description
The Hitachi HM51W16400 Series, HM51W17400 Series are CMOS dynamic RAMs organized 4,194,304word × 4-bit. They employ the most advanced 0.5 µm CMOS technology for high performance and low
power. The HM51W16400 Series, HM51W17400 Series offer Fast Page Mode as a high speed access
mode. They have package variations of standard 300-mil 26-pin plastic SOJ and standard 300-mil 26-pin
plastic TSOP.
Features
•
•
•
•
•
Single 3.3 V (±0.3 V)
Access time: 50 ns/60 ns/70 ns (max)
Power dissipation
 Active mode : 324 mW/288mW/252 mW (max) (HM51W16400 Series)
: 360 mW/324 mW/288 mW (max) (HM51W17400 Series)
 Standby mode : 7.2 mW (max)
: 0.36 mW (max) (L-version)
Fast page mode capability
Long refresh period
 4096 refresh cycles : 64 ms (HM51W16400 Series)
: 128 ms (L-version)
 2048 refresh cycles : 32 ms (HM51W17400 Series)
: 128 ms (L-version)
HM51W16400 Series, HM51W17400 Series
•
•
•
4 variations of refresh
 RAS-only refresh
 CAS-before-RAS refresh
 Hidden refresh
 Self refresh (L-version)
Battery backup operation (L-version)
Test function
 16-bit parallel test mode
Ordering Information
Type No.
Access time
Package
HM51W16400S-5
HM51W16400S-6
HM51W16400S-7
50 ns
60 ns
70 ns
300-mil 26-pin plastic SOJ
(CP-26/24DB)
HM51W16400LS-5
HM51W16400LS-6
HM51W16400LS-7
50 ns
60 ns
70 ns
HM51W17400S-5
HM51W17400S-6
HM51W17400S-7
50 ns
60 ns
70 ns
HM51W17400LS-5
HM51W17400LS-6
HM51W17400LS-7
50 ns
60 ns
70 ns
HM51W16400TS-5
HM51W16400TS-6
HM51W16400TS-7
50 ns
60 ns
70 ns
HM51W16400LTS-5
HM51W16400LTS-6
HM51W16400LTS-7
50 ns
60 ns
70 ns
HM51W17400TS-5
HM51W17400TS-6
HM51W17400TS-7
50 ns
60 ns
70 ns
HM51W17400LTS-5
HM51W17400LTS-6
HM51W17400LTS-7
50 ns
60 ns
70 ns
2
300-mil 26-pin plastic TSOP II
(TTP-26/24DA)
HM51W16400 Series, HM51W17400 Series
Pin Arrangement
HM51W16400S/LS Series
HM51W16400TS/LTS Series
VCC
1
26
VSS
VCC
1
26
VSS
I/O1
2
25
I/O4
I/O1
2
25
I/O4
I/O2
3
24
I/O3
I/O2
3
24
I/O3
WE
4
23
CAS
WE
4
23
CAS
RAS
5
22
OE
RAS
5
22
OE
A11
6
21
A9
A11
6
21
A9
A10
8
19
A8
A10
8
19
A8
A0
9
18
A7
A0
9
18
A7
A1
10
17
A6
A1
10
17
A6
A2
11
16
A5
A2
11
16
A5
A3
12
15
A4
A3
12
15
A4
VCC
13
14
VSS
VCC
13
14
VSS
(Top view)
(Top view)
Pin Description
Pin name
Function
A0 to A11
Address input
— Row/Refresh address
— Column address
I/O1 to I/O4
Data input/Data output
RAS
Row address strobe
CAS
Column address strobe
WE
Read/Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
A0 to A11
A0 to A9
3
HM51W16400 Series, HM51W17400 Series
Pin Arrangement
HM51W17400S/LS Series
HM51W17400TS/LTS Series
VCC
1
26
VSS
VCC
1
26
VSS
I/O1
2
25
I/O4
I/O1
2
25
I/O4
I/O2
3
24
I/O3
I/O2
3
24
I/O3
WE
4
23
CAS
WE
4
23
CAS
RAS
5
22
OE
RAS
5
22
OE
NC
6
21
A9
NC
6
21
A9
A10
8
19
A8
A10
8
19
A8
A0
9
18
A7
A0
9
18
A7
A1
10
17
A6
A1
10
17
A6
A2
11
16
A5
A2
11
16
A5
A3
12
15
A4
A3
12
15
A4
VCC
13
14
VSS
VCC
13
14
VSS
(Top view)
(Top view)
Pin Description
Pin name
Function
A0 to A10
Address input
— Row/Refresh address
— Column address
I/O1 to I/O4
Data input/Data output
RAS
Row address strobe
CAS
Column address strobe
WE
Read/Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
4
A0 to A10
A0 to A10
HM51W16400 Series, HM51W17400 Series
Block Diagram (HM51W16400 Series)
RAS
CAS
WE
OE
Timing and control
A0
Column decoder
A1
to
Column
•
•
•
4M array
address
buffers
A9
•
•
•
Row
address
Row decoder
4M array
I/O buffers
4M array
I/O1
to
I/O4
buffers
A10
4M array
A11
5
HM51W16400 Series, HM51W17400 Series
Block Diagram (HM51W17400 Series)
RAS
CAS
WE
OE
Timing and control
A0
Column decoder
A1
to
Column
•
•
•
4M array
address
buffers
A10
•
•
•
Row
address
Row decoder
4M array
I/O buffers
4M array
buffers
4M array
6
I/O1
to
I/O4
HM51W16400 Series, HM51W17400 Series
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VT
–0.5 to VCC + 0.5 (≤ +4.6 V (max))
V
Supply voltage relative to VSS
VCC
–0.5 to +4.6
V
Short circuit output current
Iout
50
mA
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Recommended DC Operating Conditions (Ta = 0 to +70˚C)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Supply voltage
VCC
3.0
3.3
3.6
V
1, 2
Input high voltage
VIH
2.0
—
VCC + 0.3
V
1
Input low voltage
VIL
–0.3
—
0.8
V
1
Note:
1. All voltage referred to VSS .
7
HM51W16400 Series, HM51W17400 Series
DC Characteristics
(Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W16400 Series)
HM51W16400
-5
Parameter
-6
-7
Symbol
Min Max Min Max Min Max Unit
Test conditions
Operating current* , *
ICC1
—
90
—
80
—
70
mA
tRC = min
Standby current
ICC2
—
2
—
2
—
2
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
1
—
1
—
1
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
ICC2
—
100 —
100 —
100 µA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
ICC3
—
90
—
80
—
70
mA
tRC = min
ICC5
—
5
—
5
—
5
mA
RAS = VIH
CAS = VIL
Dout = enable
CAS-before-RAS refresh
current
ICC6
—
90
—
80
—
70
mA
tRC = min
Fast page mode current*1, *3
ICC7
—
80
—
70
—
60
mA
tPC = min
Battery backup current
(Standby with CBR refresh)
(L-version)
ICC10
—
300 —
300 —
300 µA
CMOS interface
Dout = High-Z, CBR
refresh: tRC = 31.3 µs
tRAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
200 —
200 —
200 µA
CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current
ILI
–10 10
–10 10
–10 10
µA
0 V ≤ Vin ≤ 4.6 V
Output leakage current
ILO
–10 10
–10 10
–10 10
µA
0 V ≤ Vin ≤ 4.6 V
Dout = disable
Output high voltage
VOH
2.4
VCC 2.4
VCC 2.4
VCC
V
High Iout = –2 mA
Output low voltage
VOL
0
0.4
0.4
0.4
V
Low Iout = 2 mA
1
2
Standby current
(L-version)
RAS-only refresh current*2
Standby current*
1
0
0
Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
8
HM51W16400 Series, HM51W17400 Series
DC Characteristics
(Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W17400 Series)
HM51W17400
-5
Parameter
-6
-7
Symbol
Min Max Min Max Min Max Unit
Test conditions
Operating current* , *2
ICC1
—
100 —
90
—
80
mA
tRC = min
Standby current
ICC2
—
2
—
2
—
2
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
1
—
1
—
1
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
ICC2
—
100 —
100 —
100 µA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
ICC3
—
100 —
90
—
80
mA
tRC = min
ICC5
—
5
5
—
5
mA
RAS = VIH
CAS = VIL
Dout = enable
CAS-before-RAS refresh
current
ICC6
—
100 —
90
—
80
mA
tRC = min
Fast page mode current*1, *3
ICC7
—
90
80
—
70
mA
tPC = min
Battery backup current
(Standby with CBR refresh)
(L-version)
ICC10
—
300 —
300 —
300 µA
CMOS interface
Dout = High-Z, CBR
refresh: tRC = 62.5 µs
tRAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
200 —
200 —
200 µA
CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current
ILI
–10 10
–10 10
–10 10
µA
0 V ≤ Vin ≤ 4.6 V
Output leakage current
ILO
–10 10
–10 10
–10 10
µA
0 V ≤ Vin ≤ 4.6 V
Dout = disable
Output high voltage
VOH
2.4
VCC 2.4
VCC 2.4
VCC
V
High Iout = –2 mA
Output low voltage
VOL
0
0.4
0.4
0.4
V
Low Iout = 2 mA
1
Standby current
(L-version)
RAS-only refresh current*2
Standby current*
1
—
—
0
0
Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
9
HM51W16400 Series, HM51W17400 Series
Capacitance (Ta = 25˚C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
Typ
Max
Unit
Notes
Input capacitance (Address)
CI1
—
5
pF
1
Input capacitance (Clocks)
CI2
—
7
pF
1
Output capacitance (Data-in, Data-out)
CI/O
—
7
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
10
HM51W16400 Series, HM51W17400 Series
AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *18, *19
Test Conditions
•
•
•
•
Input rise and fall time: 5 ns
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM51W16400/HM51W17400
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Random read or write cycle time
tRC
90
—
110
—
130
—
ns
RAS precharge time
tRP
30
—
40
—
50
—
ns
CAS precharge time
tCP
8
—
10
—
10
—
ns
RAS pulse width
tRAS
50
10000 60
10000 70
10000 ns
CAS pulse width
tCAS
13
10000 15
10000 18
10000 ns
Row address setup time
tASR
0
—
0
—
0
—
ns
Row address hold time
tRAH
8
—
10
—
10
—
ns
Column address setup time
tASC
0
—
0
—
0
—
ns
Column address hold time
tCAH
8
—
10
—
15
—
ns
RAS to CAS delay time
tRCD
18
37
20
45
20
52
ns
3
RAS to column address delay time
tRAD
13
25
15
30
15
35
ns
4
RAS hold time
tRSH
13
—
15
—
18
—
ns
CAS hold time
tCSH
50
—
60
—
70
—
ns
CAS to RAS precharge time
tCRP
5
—
5
—
5
—
ns
OE to Din delay time
tOED
13
—
15
—
18
—
ns
5
OE delay time from Din
tDZO
0
—
0
—
0
—
ns
6
CAS delay time from Din
tDZC
0
—
0
—
0
—
ns
6
Transition time (rise and fall)
tT
3
50
3
50
3
50
ns
7
11
HM51W16400 Series, HM51W17400 Series
Read Cycle
HM51W16400/HM51W17400
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Access time from RAS
tRAC
—
50
—
60
—
70
ns
8, 9, 20
Access time from CAS
tCAC
—
13
—
15
—
18
ns
9, 10, 17,
20
Access time from address
tAA
—
25
—
30
—
35
ns
9, 11, 17,
20
Access time from OE
tOEA
—
13
—
15
—
18
ns
9, 20
Read command setup time
tRCS
0
—
0
—
0
—
ns
Read command hold time to CAS
tRCH
0
—
0
—
0
—
ns
12
Read command hold time to RAS
tRRH
0
—
0
—
0
—
ns
12
Column address to RAS lead time
tRAL
25
—
30
—
35
—
ns
Column address to CAS lead time
tCAL
25
—
30
—
35
—
ns
CAS to output in low-Z
tCLZ
0
—
0
—
0
—
ns
Output data hold time
tOH
3
—
3
—
3
—
ns
Output data hold time from OE
tOHO
3
—
3
—
3
—
ns
Output buffer turn-off time
tOFF
—
13
—
15
—
15
ns
13
Output buffer turn-off to OE
tOEZ
—
13
—
15
—
15
ns
13
CAS to Din delay time
tCDD
13
—
15
—
18
—
ns
5
Write Cycle
HM51W16400/HM51W17400
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write command setup time
tWCS
0
—
0
—
0
—
ns
14
Write command hold time
tWCH
8
—
10
—
15
—
ns
Write command pulse width
tWP
8
—
10
—
10
—
ns
Write command to RAS lead time
tRWL
13
—
15
—
18
—
ns
Write command to CAS lead time
tCWL
13
—
15
—
18
—
ns
Data-in setup time
tDS
0
—
0
—
0
—
ns
15
Data-in hold time
tDH
8
—
10
—
15
—
ns
15
12
HM51W16400 Series, HM51W17400 Series
Read-Modify-Write Cycle
HM51W16400/HM51W17400
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read-modify-write cycle time
tRWC
131
—
155
—
181
—
ns
RAS to WE delay time
tRWD
73
—
85
—
98
—
ns
14
CAS to WE delay time
tCWD
36
—
40
—
46
—
ns
14
Column address to WE delay time
tAWD
48
—
55
—
63
—
ns
14
OE hold time from WE
tOEH
13
—
15
—
18
—
ns
Refresh Cycle
HM51W16400/HM51W17400
-5
Parameter
Symbol
-6
-7
Min
Max
Min
Max
Min
Max
Unit
CAS setup time (CBR refresh cycle) tCSR
5
—
5
—
5
—
ns
CAS hold time (CBR refresh cycle)
tCHR
8
—
10
—
10
—
ns
WE setup time (CBR refresh cycle) tWRP
0
—
0
—
0
—
ns
WE hold time (CBR refresh cycle)
tWRH
8
—
10
—
10
—
ns
RAS precharge to CAS hold time
tRPC
5
—
5
—
5
—
ns
Notes
Fast Page Mode Cycle
HM51W16400/HM51W17400
-5
-6
-7
Parameter
Symbol
Min Max
Min Max
Min Max
Unit
Fast page mode cycle time
tPC
35
—
40
45
ns
Fast page mode RAS pulse width
tRASP
—
100000 —
100000 —
100000 ns
16
Access time from CAS precharge
tCPA
—
30
—
35
—
40
ns
9, 17, 20
30
—
35
—
40
—
ns
RAS hold time from CAS precharge tCPRH
—
—
Notes
13
HM51W16400 Series, HM51W17400 Series
Fast Page Mode Read-Modify-Write Cycle
HM51W16400/HM51W17400
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Fast page mode read-modify-write
cycle time
tPRWC
76
—
85
—
96
—
ns
53
—
60
—
68
—
ns
14
Notes
WE delay time from CAS precharge tCPW
Notes
Test Mode Cycle *19
HM51W16400/HM51W17400
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Test mode WE setup time
tWTS
0
—
0
—
0
—
ns
Test mode WE hold time
tWTH
8
—
10
—
10
—
ns
Refresh (HM51W16400 Series)
Parameter
Symbol
Max
Unit
Notes
Refresh
tREF
64
ms
4096 cycles
Refresh (L-version)
tREF
128
ms
4096 cycles
Parameter
Symbol
Max
Unit
Notes
Refresh period
tREF
32
ms
2048 cycles
Refresh period (L-version)
tREF
128
ms
2048 cycles
Refresh (HM51W17400 Series)
14
HM51W16400 Series, HM51W17400 Series
Self Refresh Mode (L-version)
HM51W16400L/HM51W17400L
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
RAS pulse width (self refresh)
tRASS
100
—
100
—
100
—
µs
21, 22, 23,
24
RAS precharge time (self refresh)
tRPS
90
—
110
—
130
—
ns
CAS hold time (self refresh)
tCHS
–50
—
–50
—
–50
—
ns
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If
the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are
required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC .
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA .
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. (V OH = 2.0 V, VOL = 0.8 V)
10. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14. tWCS , tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥
tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at
access time) is indeterminate.
15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge
in delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in Fast page mode cycles.
17. Access time is determined by the longest among tAA , tCAC and tCPA.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
15
HM51W16400 Series, HM51W17400 Series
19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M
× 4 are don’t care during test mode. Test mode is set by performing a WE-and-CAS-before-RAS
(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1
to I/O4) and read out from each I/O.
If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read
cycle, then the device has passed. If they are not equal, data output pin is a low state, then the
device has failed.
Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh
cycles.
To get out of test mode and enter a normal operation mode, perform either a regular CAS-beforeRAS refresh cycle or RAS-only refresh cycle.
20. In a test mode read cycle, the value of tRAC , tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
21. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in
transition state from normal operation mode to self refresh mode. If tRASS > 100 µs, then RAS
precharge time should use tRPS instead of tRP.
22. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed with in 15.6 µs immediately after exiting from and before entering into
self refresh mode.
23. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 2048
cycles (4096 cycles: HM51W16400 Series, 2048 cycles: HM51W 17400 Series) of distributed
CBR refresh with 15.6 µs interval should be executed with in 64 or 32 ms (64 ms: HM51W16400
Series, 32 ms: HM51W17400 Series) immediately after exiting from and before entering into the
self refresh mode.
24. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
25. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
16
HM51W16400 Series, HM51W17400 Series
Timing Waveforms*25
Read Cycle
t RC
t RAS
t RP
RAS
t CSH
t CRP
t RCD
t RSH
t CAS
tT
CAS
t RAD
t ASR
Address
t RAH
t RAL
t ASC
t CAL
t CAH
Column
Row
t RRH
t RCH
t RCS
WE
t DZC
t CDD
High-Z
Din
t DZO
t OEA
t OED
OE
t OEZ
t CAC
t OHO
t AA
t OFF
t RAC
t CLZ
Dout
t OH
Dout
17
HM51W16400 Series, HM51W17400 Series
Early Write Cycle
t RC
t RAS
t RP
RAS
t CSH
t RCD
t CRP
t RSH
t CAS
tT
CAS
t ASR
Address
t RAH
Row
t ASC
t CAH
Column
t WCS
t WCH
WE
t DS
Din
Dout
t DH
Din
High-Z*
* t WCS
18
t WCS (min)
HM51W16400 Series, HM51W17400 Series
Delayed Write Cycle *18
t RC
t RAS
t RP
RAS
t CSH
t CRP
t RCD
t RSH
t CAS
tT
CAS
t ASR
Address
t RAH
t ASC
Row
t CAH
Column
t CWL
t RWL
t WP
t RCS
WE
t DZC
Din
t DS
High-Z
t DH
Din
t DZO
t OEH
t OED
OE
t OEZ
t CLZ
High-Z
Dout
Invalid Dout
19
HM51W16400 Series, HM51W17400 Series
Read-Modify-Write Cycle*18
t RWC
t RAS
t RP
RAS
tT
t RCD
t CAS
t CRP
CAS
t RAD
t ASR
Address
t RAH
t ASC
Row
t CAH
Column
t RCS
t CWD
t CWL
t AWD
t RWL
t RWD
t WP
WE
t DZC
t DH
t DS
High-Z
Din
Din
t OED
t DZO
t OEH
t OEA
OE
t CAC
t OEZ
t AA
t RAC
t OHO
Dout
Dout
t CLZ
20
High-Z
HM51W16400 Series, HM51W17400 Series
RAS-Only Refresh Cycle
t RC
t RAS
t RP
RAS
tT
t RPC
t CRP
#
t CRP
CAS
t ASR
Address
t RAH
Row
t OFF
Dout
High-Z
21
HM51W16400 Series, HM51W17400 Series
CAS-Before-RAS Refresh Cycle
t RC
t RP
t RAS
t RP
RAS
t CSR
t CHR
t RPC
t CRP
,
t RPC
tT
CAS
t CP
t WRP
t WRH
t CP
WE
Address
t OFF
Dout
22
High-Z
HM51W16400 Series, HM51W17400 Series
Hidden Refresh Cycle
t RC
t RAS
t RP
t RC
t RAS
t RC
t RP
t RAS
t RP
RAS
tT
t RSH
t CHR
t CRP
t RCD
CAS
t RAD
t ASR t RAH
Address
t RAL
t ASC
Row
t CAH
Column
t WRP
t RRH
t WRH
t WRP
t WRH
t RCS
WE
t DZC
t CDD
High-Z
Din
t DZO
t OED
t OEA
OE
t CAC
t AA
t RAC
t OFF
t OH
t CLZ
Dout
t OEZ
t OHO
Dout
23
HM51W16400 Series, HM51W17400 Series
Fast Page Mode Read Cycle
t RASP
t CPRH
t RP
RAS
tT
t CSH
t RCD
t PC
t CAS
t CP
t RSH
t CAS
t CP
t CRP
t CAS
CAS
t RAL
t RAD
Address
t ASR t RAH
t CAL
t ASC t CAH
t CAL
t ASC t CAH
t CAL
t ASC t CAH
Row
Column 1
Column 2
Column N
t RCS
t RCS
t RCH
t RCS
t RRH
t RCH
t RCH
WE
t DZC
t DZC
t CDD
High-Z
High-Z
t CDD
High-Z
,
Din
t DZC
t CDD
t DZO
t OED
t DZO t OED
t DZO
t OED
OE
t RAC
t AA
t OH
t OEA
24
t OHO
t OH
t OEA
t OFF t CAC
t OEZ t CLZ
t CAC
t CLZ
Dout
t CPA
t AA
Dout 1
t CPA
t AA
t OHO
t OFF
t OEZ
Dout 2
t OH
t OHO
t OEA
t CAC
t CLZ
t OFF
t OEZ
Dout N
HM51W16400 Series, HM51W17400 Series
Fast Page Mode Early Write Cycle
t RP
t RASP
RAS
tT
t CSH
t RCD
t CAS
t PC
t CP
t CAS
t CP
t RSH
t CAS
t CRP
CAS
Address
t ASR t RAH
t ASC t CAH
t ASC t CAH
t ASC t CAH
ROW
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
Din
Dout
t DH
Din 1
t DS
t DH
Din 2
t DS
t DH
Din N
High-Z*
* t WCS
t WCS (min)
25
HM51W16400 Series, HM51W17400 Series
Fast Page Mode Delayed Write Cycle *18
t RASP
t RP
RAS
tT
t CP
t CSH
t RCD
t CRP
t CP
t PC
t CAS
t RSH
t CAS
t CAS
CAS
t RAD
t ASR
t ASC
t RAH
Address
t ASC
t CAH
Row
t ASC
t CAH
Column 1
t CAH
Column 2
t CWL
Column N
t CWL
t CWL
t RWL
t RCS
t RCS
t RCS
WE
t WP
t WP
t WP
t DZC t DS
t DZC t DS
t DZC t DS
t DH
t DH
Din
1
Din
t DZO
t DH
Din
2
t DZO
t OED
Din
N
t DZO
t OED
#*
t OED
t OEH
t OEH
t OEH
OE
t CLZ
t CLZ
t OEZ
t CLZ
t OEZ
t OEZ
High-Z
Dout
Invalid Dout
26
Invalid Dout
Invalid Dout
HM51W16400 Series, HM51W17400 Series
Fast Page Mode Read-Modify-Write Cycle*18
t RASP
t RP
RAS
tT
t PRWC
t CP
t RCD
t RSH
t CP
t CAS
t CAS
t CRP
t CAS
CAS
t RAD
t ASR
Address
t ASC
t RAH
Row
t ASC
t CAH
t CAH
Column 1
t ASC
t CAH
Column 2
t RWD
t CWL
Column N
t CPW
t AWD
t CWL
t CPW
t AWD
t CWD
t RCS
t CWL
t AWD
t CWD
t RCS
t RWL
t CWD
WE
t RCS
t WP
t WP
t DZC t DS
t WP
t DZC t DS
t DZC t DS
t DH
t DH
Din
1
Din
t DZO
t OED
t DH
Din
2
t OED
t DZO
t OED
t DZO
t OEH
t OEH
#*
t OEH
Din
N
OE
t OHO
t OEA
t CAC
t OHO
t OEA
t CAC
t AA
t AA
t CPA
t RAC
t OEZ
t CLZ
t OHO
t OEA
t CAC
t AA
t CPA
t OEZ
t CLZ
t OEZ
t CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
27
HM51W16400 Series, HM51W17400 Series
Test Mode Cycle *19
Set Cycle**
*,**
Reset Cycle
Test Mode Cycle
Normal Mode
RAS
CAS
WE
* CBR or RAS-only refresh
** Address, Din, OE: H or L
Test Mode Set Cycle
t RC
t RP
t RAS
t RP
RAS
t CSR
t CHR
tT
,
CAS
t RPC
t CP
WE
t WTS
t WTH
t CP
Address
t OFF
Dout
28
t CRP
A

Á
ÃC ,ÂÀ‚€B@
t RPC
High-Z
HM51W16400 Series, HM51W17400 Series
Self Refresh Cycle (L-version)*21,*22,*23,*24
t RASS
t RP
t RPS
RAS
tT
,
,
t RPC
t CP
t CRP
t CSR
t CHS
CAS
t WRP
t WRH
$%&+,
WE
t OFF
Dout
High-Z
29
HM51W16400 Series, HM51W17400 Series
Package Dimensions
HM51W16400S/LS Series
HM51W17400S/LS Series (CP-26/24DB)
1.30 Max
0.43 ± 0.10
0.41 ± 0.08
1.27
2.54
2.65 ± 0.12
13
0.80 +0.25
–0.17
6 8
0.74
3.50 ± 0.26
1
8.51 ± 0.13
14
7.62 ± 0.13
26
16.90
17.27 Max
21 19
Unit: mm
6.71 ± 0.25
0.10
Hitachi Code
JEDEC Code
EIAJ Code
Weight
30
CP-26/24DB
MO-077-AA
SC-632-A
0.8 g
HM51W16400 Series, HM51W17400 Series
HM51W16400TS/LTS Series
HM51W17400TS/LTS Series (TTP-26/24DA)
14
7.62
26
17.14
17.54 Max
21 19
Unit: mm
6 8
1.27
0.42 ± 0.08
0.40 ± 0.06
0.21 M
13
0.80
9.22 ± 0.20
1.15 Max
0.13 ± 0.05
0.10
0.145 ± 0.05
0.125 ± 0.04
1.20 Max
0 – 5°
2.54
Hitachi Code
JEDEC Code
EIAJ Code
Weight
0.50 ± 0.10
0.68
1
TTP-26/24DA
MO-132AB
—
0.30 g
31
HM51W16400 Series, HM51W17400 Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
USA
Tel: 415-589-8300
Fax: 415-583-4207
32
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 0628-585000
Fax: 0628-778322
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16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
HM51W16400 Series, HM51W17400 Series
Revision Record
Rev.
Date
Contents of Modification
Drawn by
Approved by
1.0
Oct. 14, 1996
Initial issue
Y. Kasama
M. Mishima
2.0
Nov. 14, 1996
Addition of HM51W16400-5 Series
Y. Kasama
Y. Matsuno
Addition of HM51W17400-5 Series
Power dissipation (active)
396/360 mW(max) to 360/324/288 mW (max)
(HM51W17400 Series)
DC Characteristics (HM51W17400 Series)
ICC1 max: 110/100 mA to 100/90/80 mA
ICC3 max: 110/100 mA to 100/90/80 mA
ICC6 max: 110/100 mA to 100/90/80 mA
3.0
Feb. 27, 1997
AC Characteristics
tRRH min: 5/5/5 ns to 0/0/0 ns
33
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