ONSEMI MC14014BCP

MC14014B, MC14021B
8−Bit Static Shift Register
The MC14014B and MC14021B 8−bit static shift registers are
constructed with MOS P−channel and N−channel enhancement mode
devices in a single monolithic structure. These shift registers find primary
use in parallel−to−serial data conversion, synchronous and asynchronous
parallel input, serial output data queueing; and other general purpose
register applications requiring low power and/or high noise immunity.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
•
•
Synchronous Parallel Input/Serial Output (MC14014B)
Asynchronous Parallel Input/Serial Output (MC14021B)
Synchronous Serial Input/Serial Output
Full Static Operation
“Q” Outputs from Sixth, Seventh, and Eighth Stages
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
MC14014B Pin−for−Pin Replacement for CD4014B
MC14021B Pin−for−Pin Replacement for CD4021B
Pb−Free Packages are Available*
PDIP−16
P SUFFIX
CASE 648
MC140xxBCP
AWLYYWW
1
16
SOIC−16
D SUFFIX
CASE 751B
140xxB
AWLYWW
1
16
SOEIAJ−16
F SUFFIX
CASE 966
MAXIMUM RATINGS (Voltages Referenced to VSS)
MC140xxB
AWLYWW
1
Value
Unit
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
ORDERING INFORMATION
TL
Lead Temperature
(8−Second Soldering)
260
°C
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Symbol
VDD
Vin, Vout
Iin, Iout
Parameter
16
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
xx
A
WL, L
YY, Y
WW, W
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 5
1
Publication Order Number:
MC14014B/D
MC14014B, MC14021B
TRUTH TABLE
SERIAL OPERATION:
t
Clock DS P/S
n
n+1
n+2
n+3
Q6
t=n+6
Q7
t=n+7
Q8
t=n+8
0
1
0
1
0
0
0
0
0
1
0
1
?
0
1
0
?
?
0
1
X
0
Q6
Q7
Q8
PARALLEL OPERATION:
Clock
MC14014B MC14021B DS
X
X
X
P/S
Pn
*Qn
1
0
0
1
1
1
X
*Q6, Q7, & Q8 are available externally
X = Don’t Care
PIN ASSIGNMENT
P8
1
16
VDD
Q6
2
15
P7
Q8
3
14
P6
P4
4
13
P5
P3
5
12
Q7
P2
6
11
DS
P1
7
10
C
VSS
8
9
P/S
LOGIC DIAGRAM
P/S
DS
9
11
P1
D
C
CLOCK
P2
7
Q
D
C
P3
6
Q
P6
5
D
Q
C
P7
14
P8
15
D
Q
D
Q
D
C
Q
C
Q
C
1
Q
10
VDD = PIN 16
VSS = PIN 8
P4 = PIN 4
P5 = PIN 13
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2
Q6
2
Q7
12
3
Q8
MC14014B, MC14021B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55C
Characteristic
Symbol
25C
125C
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
“0” Level
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
(VO = 0.5 or 4.5 Vdc) “1” Level
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
− 1.3
− 3.4
– 4.2
– 0.88
– 2.25
− 8.8
−
−
−
−
– 1.7
− 0.36
– 0.9
− 2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
± 0.1
−
± 0.00001
± 0.1
−
± 1.0
Adc
Input Capacitance
(Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
−
−
−
5.0
10
15
−
−
−
0.005
0.010
0.015
5.0
10
15
−
−
−
150
300
600
Adc
IT
5.0
10
15
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
Vdc
mAdc
IT = (0.75 A/kHz) f + IDD
IT = (1.50 A/kHz) f + IDD
IT = (2.25 A/kHz) f + IDD
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk
where: IT is in A (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.0015.
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3
Adc
MC14014B, MC14021B
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SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25C)
Characteristic
Symbol
VDD
Vdc
Min
Typ
(Note 6)
Max
5.0
10
15
−
−
−
100
50
40
200
100
80
5.0
10
15
−
−
−
400
170
115
800
340
230
Unit
ns
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay Time (Clock to Q, P/S to Q)
tPHL, tPLH = (1.7 ns/pF) CL + 315 ns
tPHL, tPLH = (0.66 ns/pF) CL + 137 ns
tPHL, tPLH = (0.5 ns/pF) CL + 90 ns
tPLH,
tPHL
Clock Pulse Width
tWH
5.0
10
15
400
175
135
150
75
40
−
−
−
ns
fcl
5.0
10
15
−
−
−
3.0
6.0
8.0
1.5
3.0
4.0
MHz
Parallel/Serial Control Pulse Width
tWH
5.0
10
15
400
175
135
150
75
40
−
−
−
ns
Setup Time
P/S to Clock
tsu
5.0
10
15
200
100
80
100
50
40
−
−
−
ns
Hold Time
Clock to P/S
th
5.0
10
15
20
20
25
– 2.5
– 10
0
−
−
−
ns
Setup Time
Data (Parallel or Serial) to
Clock or P/S
tsu
5.0
10
15
350
80
60
150
50
30
−
−
−
ns
Hold Time
Clock to Ds
th
5.0
10
15
45
35
35
0
0
5
−
−
−
ns
Hold Time
Clock to Pn
th
5.0
10
15
50
45
45
25
20
20
−
−
−
ns
tr(cl)
5.0
10
15
−
−
−
−
−
−
15
5
4
s
Clock Frequency
Input Clock Rise Time
ns
5. The formulas given are for the typical characteristics only at 25C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14014B, MC14021B
VDD
PULSE
GENERATOR
P/S
C
P6
P7
P8
DS
Vout
VDD
Q6
P/S
C
P6
P7
P8
DS
PULSE
GENERATOR
Q7
IOH
Q8
EXTERNAL
POWER
SUPPLY
Vout
Q6
Q7
Q8
IOL
EXTERNAL
POWER
SUPPLY
Preset output under test to a logic “1” level.
Figure 1. Output Source Current Test Circuit
Figure 2. Output Sink Current Test Circuit
VDD
500 F
ID
P/S
C
P1
P2
P3
P4
P5
P6
P7
P8
DS
PULSE
GENERATOR 1
PULSE
GENERATOR 2
0.01 F
CERAMIC
Q6
CL
Q7
CL
Q8
VSS
CL
1
f
CLOCK
50%
DATA
Figure 3. Power Dissipation Test Circuit and Waveform
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5
MC14014B, MC14021B
SW 1
VDD
1
PULSE
GENERATOR 1
PULSE
GENERATOR 2
2
2
2
1
1
SWITCH POSITION 1 = PARALLEL IN
SWITCH POSITION 2 = SERIAL IN
VDD
P/S
C
P1
P2
P3
P4
P5
P6
P7
P8
DS
PARALLEL OR
SERIAL DATA
INPUT
Q6
20 ns
90%
50%
10%
tsu
VSS
tWH
Q7
CL
Q8
VSS
CLOCK OR P/S
INPUT
tTHL
90%
50%
10%
tWH
tPLH
Q
OUTPUT
SW 2
20 ns
VDD
VDD
VSS
tWL
tPHL
VOH
90%
50%
10%
VOL
tTHL
tTLH
tWL = tWH = 50% DUTY CYCLE
Figure 4. Switching Time Test Circuit and Waveforms
ORDERING INFORMATION
Package
Shipping†
MC14014BCP
PDIP−16
500 Units / Rail
MC14014BCPG
PDIP−16
(Pb−Free)
500 Units / Rail
MC14014BD
SOIC−16
48 Units / Rail
MC14014BDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14014BDR2
SOIC−16
2500 Units / Tape & Reel
MC14014BDR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
Device
MC14014BF
SOEIAJ−16
50 Units / Rail
MC14014BFEL
SOEIAJ−16
2000 Units / Tape & Reel
MC14021BCP
PDIP−16
500 Units / Rail
MC14021BCPG
PDIP−16
(Pb−Free)
500 Units / Rail
MC14021BD
SOIC−16
48 Units / Rail
MC14021BDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14021BDR2
SOIC−16
2500 Units / Tape & Reel
MC14021BDR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
MC14021BF
SOEIAJ−16
50 Units / Rail
MC14021BFEL
SOEIAJ−16
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
6
MC14014B, MC14021B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
SEATING
PLANE
−T−
K
H
G
D
M
J
16 PL
0.25 (0.010)
T A
M
M
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0
10 0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
10 0.51
1.01
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
http://onsemi.com
7
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.229
0.244
0.010
0.019
MC14014B, MC14021B
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966−01
ISSUE O
16
LE
9
Q1
M
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
0.10 (0.004)
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 0
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 0
0.028
0.035
−−−
0.031
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
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N. American Technical Support: 800−282−9855 Toll Free
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Order Literature: http://www.onsemi.com/litorder
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
8
For additional information, please contact your
local Sales Representative.
MC14014B/D