MOTOROLA MC74HCU04AD Hex unbuffered inverter Datasheet

SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC74HCU04A is identical in pinout to the LS04 and the MC14069UB.
The device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of six single–stage inverters. These inverters are well
suited for use as oscillators, pulse shapers, and in many other applications
requiring a high–input impedance amplifier. For digital applications, the
HC04A is recommended.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V; 2.5 to 6 V in Oscillator
Configurations
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 12 FETs or 3 Equivalent Gates
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
14
1
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
14
1
ORDERING INFORMATION
MC74HCUXXAN
MC74HCUXXAD
MC74HCUXXADT
Plastic
SOIC
TSSOP
LOGIC DIAGRAM
A1
A2
A3
1
2
3
4
5
6
9
8
11
10
13
12
PIN ASSIGNMENT
Y1
Y2
Y3
Y=A
A4
A5
Y4
A1
1
14
VCC
Y1
2
13
A6
A2
3
12
Y6
Y2
4
11
A5
A3
5
10
Y5
Y3
6
9
A4
GND
7
8
Y4
Y5
FUNCTION TABLE
A6
Y6
PIN 14 = VCC
PIN 7 = GND
3/97
 Motorola, Inc. 1997
1
REV 1
Inputs
A
Outputs
Y
L
H
H
L
MC74HCU04A
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MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: –10mW/_C from 65_ to 125_C
SOIC Package: –7mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
—
No
Limit
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.5 V*
|Iout|
20 µA
2.0
3.0
4.5
6.0
1.7
2.5
3.6
4.8
1.7
2.5
3.6
4.8
l.7
2.5
3.6
4.8
V
VIL
Maximum Low–Level Input
Voltage
Vout = VCC – 0.5 V*
|Iout|
20 µA
2.0
3.0
4.5
6.0
0.3
0.5
0.8
1.1
0.3
0.5
0.8
1.1
0.3
0.5
0.8
1.1
V
Minimum High–Level Output
Voltage
Vin = GND
|Iout|
20 µA
2.0
4.5
6.0
1.8
4.0
5.5
1.8
4.0
5.5
1.8
4.0
5.5
V
3.0
4.5
6.0
2.36
3.86
5.36
2.26
3.76
5.26
2.20
3.70
5.20
2.0
4.5
6.0
0.2
0.5
0.5
0.2
0.5
0.5
0.2
0.5
0.5
3.0
4.5
6.0
0.32
0.32
0.32
0.32
0.37
0.37
0.32
0.40
0.40
VOH
Vin = GND
VOL
Maximum Low–Level Output
Voltage
2.4 mA
4.0 mA
5.2 mA
Vin = VCC
|Iout|
20 µA
Vin = VCC
MOTOROLA
|Iout|
|Iout|
|Iout|
|Iout|
|Iout|
|Iout|
2
2.4 mA
4.0 mA
5.2 mA
V
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HCU04A
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Iin
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
ICC
VCC
V
– 55 to
25_C
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Vin = VCC or GND
Iout = 0 µA
6.0
1
10
40
µA
Test Conditions
85_C
125_C
Unit
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
* For VCC = 2.0 V, Vout = 0.2 V or VCC – 0.2 V.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to
25_C
85_C
125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
70
40
14
12
90
45
18
15
105
50
21
18
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
P
Power
Di i i C
Dissipation
Capacitance
i
(P
(Per IInverter)*
)*
15
pF
F
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
MC74HCU04A
TEST POINT
tr
90%
50%
10%
INPUT A
tPHL
90%
50%
10%
OUTPUT Y
tTHL
tf
OUTPUT
VCC
DEVICE
UNDER
TEST
GND
tPLH
tTLH
CL*
* Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
LOGIC DETAIL
(1/6 of Device Shown)
VCC
A
MOTOROLA
Y
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HCU04A
TYPICAL APPLICATIONS
Crystal Oscillator
Stable RC Oscillator
R2
1/6 HCU04
1/6 HCU04
1/6 HCU04
Vout
1/6 HCU04
R2 > > R1
C1 < C2
C
R1
R2
R1
C2
C1
Vout
Schmitt Trigger
High Input Impedance Single–Stage Amplifier
with a 2 to 6 V Supply Range
VCC
R2
1 M 1/6 HCU04
R2 > 6R1
R1
1/6 HCU04
1/6 HCU04
INPUT
Vin
OUTPUT
Vout
1M
Multi–Stage Amplifier
LED Driver
+V
VCC
1/6 HCU04
INPUT
1/6 HCU04
1/6 HCU04
1/6 HCU04
OUTPUT
For reduced power supply current, use high–efficiency
LEDs
such as the Hewlett–Packard HLMP series or equivalent.
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
MC74HCU04A
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
14
8
1
7
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
B
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
D
SEATING
PLANE
K
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
–A–
14
1
P 7 PL
0.25 (0.010)
7
G
D
0.25 (0.010)
MOTOROLA
M
T
F
J
M
K
14 PL
B
S
M
R X 45°
C
SEATING
PLANE
B
M
A
S
6
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
8
–B–
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.228 0.244
0.010 0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HCU04A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
–U–
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
–V–
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N–N
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
7
MC74HCU04A/D
MOTOROLA
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