Cypress CY62138FLL-45ZSXI 2-mbit (256k x 8) static ram Datasheet

CY62138F MoBL®
2-Mbit (256K x 8) Static RAM
Features
■
High speed: 45 ns
■
Wide voltage range: 4.5 V – 5.5 V
■
Pin compatible with CY62138V
■
Ultra low standby power
Functional Description [1]
The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE1 HIGH or CE2 LOW).
— Typical standby current: 1 A
— Maximum standby current: 5 A
■
Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE features
■
Automatic power down when deselected
■
complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 32-pin SOIC and 32-pin thin small outline
package (TSOP) II packages
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A17).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and output enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
Logic Block Diagram
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-13194 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 15, 2010
[+] Feedback
CY62138F MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics (Over the Operating Range) ... 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 4
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ........................................ 5
Data Retention Waveform................................................. 5
Switching Characteristics (Over the Operating Range) .. 6
Read Cycle 1 (Address transition controlled) ............... 7
Read Cycle No. 2 (OE controlled) ................................ 7
Write Cycle No. 1 (WE controlled)................................ 7
Document #: 001-13194 Rev. *C
Write Cycle No. 2 (CE1 or CE2 controlled) .................. 8
Write Cycle No. 3 (WE controlled, OE LOW) ............... 8
Truth Table ........................................................................ 9
Ordering Information ...................................................... 10
Ordering Code Definition ........................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 12
Documents Conventions ............................................... 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
Page 2 of 14
[+] Feedback
CY62138F MoBL®
Pin Configuration
32-Pin SOIC/TSOP II Pinout
Top View
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
32
31
2
3
4
30
29
5
6
28
27
26
25
7
8
9
10
24
23
22
11
12
13
14
15
16
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62138FLL
Speed
(ns)
Min
Typ [2]
Max
4.5 V
5.0 V
5.5 V
45
Operating ICC (mA)
f = 1MHz
f = fmax
Standby ISB2 (A)
Typ [2]
Max
Typ [2]
Max
Typ [2]
Max
1.6
2.5
13
18
1
5
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document #: 001-13194 Rev. *C
Page 3 of 14
[+] Feedback
CY62138F MoBL®
DC Input Voltage [3, 4] ......... –0.5 V to 6.0 V (VCCmax + 0.5 V)
Maximum Ratings
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage ........................................ > 2001 V
(MIL–STD–883, Method 3015)
Storage temperature ............................... –65 °C to + 150 °C
Latch-up Current .................................................... > 200 mA
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Operating Range
Supply voltage to ground
potential ............................. –0.5 V to 6.0 V (VCCmax + 0.5 V)
Device
DC voltage applied to outputs
in High-Z state [3, 4] ............. –0.5 V to 6.0 V (VCCmax + 0.5 V)
CY62138FLL
Range
Ambient
Temperature
VCC [5]
Industrial –40 °C to +85 °C 4.5 V to 5.5 V
Electrical Characteristics (Over the Operating Range)
Parameter
Description
Test Conditions
45 ns
Unit
Min
Typ [6]
2.4
–
–
V
–
–
0.4
V
Max
VOH
Output HIGH voltage
IOH = –1.0 mA
VOL
Output LOW voltage
IOL = 2.1 mA
VIH
Input HIGH voltage
VCC = 4.5 V to 5.5 V
2.2
–
VCC + 0.5
V
VIL
Input LOW voltage
VCC = 4.5 V to 5.5 V
–0.5
–
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Outputcleakage Current
GND < VO < VCC, Output disabled
–1
–
+1
A
ICC
VCC operating supply
Current
f = fmax = 1/tRC
–
13
18
mA
–
1.6
2.5
–
1
5
ISB2 [7]
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
f = 1 MHz
Automatic CE Power-down CE1 > VCC – 0.2 V or CE2 < 0.2 V
current CMOS inputs
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
A
Capacitance
Parameter[8]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter[8]
Description
JA
Thermal resistance
(Junction to Ambient)
JC
Thermal resistance
(Junction to Case)
Test Conditions
SOIC
TSOP II
Unit
Still air, soldered on a 3 × 4.5 inch two-layer printed
circuit board
44.53
44.16
C / W
24.05
11.97
C / W
Notes
3. VIL(min) = –2.0 V for pulse durations less than 20 ns.
4. VIH(max) = VCC+0.75 V for pulse durations less than 20 ns.
5. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
7. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-13194 Rev. *C
Page 4 of 14
[+] Feedback
CY62138F MoBL®
AC Test Loads and Waveforms
R1
VCC
OUTPUT
ALL INPUT PULSES
3.0V
R2
30 pF
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
GND
Rise Time = 1 V/ns
Equivalent to:
Fall Time = 1 V/ns
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
5.0 V
Unit
R1
1800

R2
990

RTH
639

VTH
1.77
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
Conditions
VCC for Data retention
[10]
VCC= VDR, CE1 > VCC 0.2V or CE2 < 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V
Data retention current
Min
Typ [9]
Max
Unit
2.0
–
–
V
–
1
5
A
tCDR [9]
Chip deselect to data
retention time
0
–
–
ns
tR [11]
Operation recovery time
45
–
–
ns
Data Retention Waveform [12]
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 2.0V
VCC(min)
tR
CE
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.Typical values are included for reference only and are not guaranteed
or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
10. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
11. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
12. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
Document #: 001-13194 Rev. *C
Page 5 of 14
[+] Feedback
CY62138F MoBL®
Switching Characteristics (Over the Operating Range)
Parameter[13]
45 ns
Description
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
tLZOE
OE LOW to Low-Z [14]
5
–
ns
tHZOE
OE HIGH to High-Z
–
18
ns
10
–
ns
[14, 15]
tLZCE
CE1 LOW and CE2 HIGH to Low Z
tHZCE
CE1 HIGH or CE2 LOW to High-Z [14, 15]
–
18
ns
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
ns
CE1 HIGH or CE2 LOW to power-down
–
45
ns
tWC
Write cycle time
45
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to High-Z [14, 15]
–
18
ns
tLZWE
WE HIGH to Low-Z [14]
10
–
ns
tPD
Write Cycle
[14]
[16]
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 5.
14. At any given temperature and voltage condition, tHZCE is less than tLZCE , tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
15. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
16. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 001-13194 Rev. *C
Page 6 of 14
[+] Feedback
CY62138F MoBL®
Switching Waveforms
Read Cycle 1 (Address transition controlled) [17, 18]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE controlled) [18, 19, 22]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
HIGH IMPEDANCE
DATA OUT
DATA VALID
tLZCE
tPD
tPU
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
50%
50%
ICC
ISB
Write Cycle No. 1 (WE controlled) [16, 20, 21, 22]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
NOTE 23
tHD
DATA VALID
tHZOE
Notes:
17. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
18. WE is HIGH for read cycle.
19. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
20. Data I/O is high impedance if OE = VIH.
21. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
22. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH
23. During this period, the I/Os are in output state. Do not apply input signals
Document #: 001-13194 Rev. *C
Page 7 of 14
[+] Feedback
CY62138F MoBL®
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 controlled) [24, 25, 26, 27]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Write Cycle No. 3 (WE controlled, OE LOW) [24, 27]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 28
tHD
DATA VALID
tHZWE
tLZWE
Notes
24. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH
25. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write
26. Data I/O is high impedance if OE = VIH.
27. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
28. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-13194 Rev. *C
Page 8 of 14
[+] Feedback
CY62138F MoBL®
Truth Table
CE1
CE2
WE
OE
H
X[29]
X
X
High Z
Inputs/Outputs
Deselect / Power-down
Mode
Standby (ISB)
Power
X[29]
L
X
X
High-Z
Deselect/Power-down
Standby (ISB)
L
H
H
L
Data out
Read
Active (ICC)
L
H
H
H
High-Z
Output disabled
Active (ICC)
L
H
L
X
Data in
Write
Active (ICC)
Note
29. The ‘X’ (Don’t care) state for the Chip enables (CE1 and CE2) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins
is not permitted
Document #: 001-13194 Rev. *C
Page 9 of 14
[+] Feedback
CY62138F MoBL®
Ordering Information
Speed
(ns)
45
Package
Diagram
Ordering Code
Package Type
CY62138FLL-45SXI
51-85081 32-pin Small Outline Integrated Circuit (Pb-free)
CY62138FLL-45ZSXI
51-85095 32-pin Thin Small Outline Package II (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definition
CY
621
3
8F
LL
45
XXX
X
Tem perature Grades
I = Industrial
Package Type = SX : SOIC (Pb-free)
ZSX : TSOP II (Pb-free)
Speed Grade
Low Power
Bus W idth = X8
F = 90nm Technology
Density = 2 M bit
M oBL SRAM Fam ily
Coim pany ID: CY = Cypress
Document #: 001-13194 Rev. *C
Page 10 of 14
[+] Feedback
CY62138F MoBL®
Package Diagrams
Figure 1. 32-pin (450 Mil) Molded SOIC, 51-85081
51-85081-*C
Document #: 001-13194 Rev. *C
Page 11 of 14
[+] Feedback
CY62138F MoBL®
Package Diagrams (continued)
Figure 2. 32-Pin TSOP II, 51-85095
51-85095-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their
respective holders.
Acronyms
Documents Conventions
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
Symbol
I/O
input/output
SRAM
Acronym
Unit of Measure
°C
degrees Celsius
static random access memory
A
microamperes
VFBGA
very fine ball grid array
mA
milliampere
TSOP
thin small outline package
MHz
megahertz
SOIC
small outline integrated circuit
Document #: 001-13194 Rev. *C
ns
nanoseconds
pF
picofarads
V
volts

ohms
W
watts
Page 12 of 14
[+] Feedback
CY62138F MoBL®
Document History Page
Document Title: CY62138F MoBL® 2-Mbit (256K x 8) Static RAM
Document Number: 001-13194
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
797956
See ECN
VKN
New Data Sheet
*A
940341
See ECN
VKN
Added footnote #7 related to ISB2 and ICCDR
*B
3055174
13/10/2010
RAME
Updated As per new template
Added Acronyms and Units of Measure table.
Added Ordering Code Definition.
Footnotes updated
Updated Package Diagram Figure 1 and Figure 2.
*C
3061313
15/10/2010
RAME
Minor change: Corrected “IO” to “I/O”
Document #: 001-13194 Rev. *C
Page 13 of 14
[+] Feedback
CY62138F MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-13194 Rev. *C
Revised October 15, 2010
Page 14 of 14
All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback
Similar pages