MC10136 Universal Hexadecimal Counter The MC10136 is a high speed synchronous counter that can count up, count down, preset, or stop count at frequencies exceeding 100 MHz. The flexibility of this device allows the designer to use one basic counter for most applications, and the synchronous count feature makes the MC10136 suitable for either computers or instrumentation. Three control lines (S1, S2, and Carry In) determine the operation mode of the counter. Lines S1 and S2 determine one of four operations; preset (program), increment (count up), decrement (count down), or hold (stop count). Note that in the preset mode a clock pulse is necessary to load the counter, and the information present on the data inputs (D0, D1, D2, and D3) will be entered into the counter. Carry Out goes low on the terminal count, or when the counter is being preset. This device is not designed for use with gated clocks. Control is via S1 and S2. • PD = 625 mW typ/pkg (No Load) • fcount = 150 MHz typ • tpd = 3.3 ns typ (C-Q) • 7.0 ns typ (C-Cout) • 5.0 ns typ (Cin-Cout) http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 MC10136L AWLYYWW 1 16 PDIP–16 P SUFFIX CASE 648 MC10136P AWLYYWW 1 1 PLCC–20 FN SUFFIX CASE 775 10136 AWLYYWW DIP PIN ASSIGNMENT VCC1 1 16 VCC2 Q2 2 15 Q1 Q3 3 14 Q0 Cout 4 13 CLOCK D3 5 12 D0 D2 6 11 D1 S2 7 10 Cin VEE 8 9 S1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). Package Shipping MC10136L CDIP–16 25 Units / Rail MC10136P PDIP–16 25 Units / Rail MC10136FN PLCC–20 46 Units / Rail FUNCTION TABLE Cin S1 S2 X L L Preset (Program) Operating Mode L L H Increment (Count Up) H L H Hold Count L H L Decrement (Count Down) H H L Hold Count X H H Hold (Stop Count) Semiconductor Components Industries, LLC, 2002 January, 2002 – Rev. 7 1 Publication Order Number: MC10136/D MC10136 LOGIC DIAGRAM S1 9 S2 7 Carry In 10 VCC1 = PIN 1 VCC2 = PIN 16 T T Q0 T Q1 Q0 C T Q1 T C T T VEE = PIN 8 T Q3 T T Q3 TT C Q2 T Q2 T C Clock 13 12D0 14Q0 11D1 15Q1 6D2 2Q2 5D3 3Q3 4 Carry Out NOTE: Flip-flops will toggle when all T inputs are low. SEQUENTIAL TRUTH TABLE* INPUTS OUTPUTS S1 S2 D0 D1 D2 D3 Carry In Clock ** Q0 Q1 Q2 Q3 Carry Out L L L L L L H L H H H H L H H H H H H L L L L L L X X X X X X H X X X X L X X X X X X H X X X X H X X X X X X L X X X X H X X X X X X L X X X X X L L L H H X X L L L L H H H H L H H H H H H H L H L H H H H H L H L H L L H H H H H H H L L H H H H H H H H L L L L H H H H H H H H L L L L H L H H L H H H L H H L H * Truth table shows logic states assuming inputs vary in sequence shown from top to bottom. ** A clock H is defined as a clock input transition from a low to a high logic level. http://onsemi.com 2 MC10136 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Power Supply Drain Current Input Current Symbol Pin Under Test IE 8 138 IinH 5,6,11,12 7 9,10 13 350 425 390 460 IinL All 0.5 –30°C Min +25°C Max Min +85°C Typ Max Max Unit 100 125 138 mAdc 220 265 245 290 220 265 245 290 µAdc 0.5 Min µAdc 0.3 Output Voltage Logic 1 VOH 14 (2.) –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc Output Voltage Logic 0 VOL 14 (2.) –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc Threshold Voltage Logic 1 VOHA 14 (2.) –1.080 Threshold Voltage Logic 0 VOLA 14 (2.) Propagation Delay Clock Input t13+14+ t13+14– t13+4+ t13+4– 14 14 4 4 0.8 0.8 2.0 2.0 4.8 4.8 10.9 10.9 1.0 1.0 2.5 2.5 3.3 3.3 7.0 7.0 4.5 4.5 10.5 10.5 1.4 1.4 2.4 2.4 5.0 5.0 11.5 11.5 Carry In to Carry Out t10–4– t10+4+ 4 (3.) 4 1.6 1.6 7.4 7.4 1.6 1.6 5.0 5.0 6.9 6.9 1.9 1.9 7.5 7.5 Data Inputs t12+13+ t12–13+ 14 14 3.5 3.5 3.5 3.5 3.5 3.5 Select Inputs t9+13+ t7+13+ 14 14 6.0 6.0 6.0 6.0 6.0 6.0 Carry In Input t10–13+ t10+13+ 14 14 2.5 1.5 2.5 1.5 3.0 1.5 Data Inputs t13+12+ t13+12– 14 14 0 0 0 0 0 0 Select Inputs t13+9+ t13+7+ 14 14 –1.0 –1.0 –1.0 –1.0 –1.0 –1.0 Carry In Input t13+10– t13+10+ 14 14 0 0 0 0 0 0 fcountup fcountdown 14 14 125 125 125 125 150 150 Switching Times Setup Time Hold Time –0.980 –0.910 –1.655 –1.630 Vdc –1.595 (50Ω Load) Counting Frequency Vdc ns 125 125 MHz Rise Time (20 to 80%) t4+ t14+ 4 14 0.9 0.9 3.3 3.3 1.1 1.1 2.0 2.0 3.3 3.3 1.1 1.1 3.5 3.5 Fall Time (20 to 80%) t4– t14– 4 14 0.9 0.9 3.3 3.3 1.1 1.1 2.0 2.0 3.3 3.3 1.1 1.1 3.5 3.5 ns 1. Individually test each input; apply VILmin to pin under test. VIH appears at clock input (Pin 13). 2. Measure output after clock pulse VIL 3. Before test set all Q outputs to a logic high. 4. To preserve reliable performance, the MC10136 (plastic packaged device only) is to be operated in ambient temperatures above 70°C only when 500lfpm blown air or equivalent heat sinking is provided. http://onsemi.com 3 MC10136 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Power Supply Drain Current Input Current Pin Under Test IE 8 IinH 5,6,11,12 7 9,10 13 IinL All VOH 14 (2.) TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VEE (VCC) Gnd 8 1, 16 8 8 8 8 1, 16 1, 16 1, 16 1, 16 Note 1. 8 1, 16 7, 9 8 1, 16 8 1, 16 8 1, 16 VILmin Logic 1 Output Voltage Logic 0 VOL 14 (2.) 7, 9 Threshold Voltage Logic 1 VOHA 14 (2.) 7, 9 Logic 0 VOLA 14 (2.) Switching Times (50Ω Load) Propagation Delay Clock Input VILAmax 5,6,11,12 7 9,10 13 Output Voltage Threshold Voltage VIHAmin 12 12 7, 9 +1.11V 12 8 1, 16 Pulse In Pulse Out –3.2 V +2.0 V 13 13 13 13 14 14 4 4 8 8 8 8 1, 16 1, 16 1, 16 1, 16 13 13 10 10 4 4 8 8 1, 16 1, 16 7, 9 7, 9 12, 13 12, 13 14 14 8 8 1, 16 1, 16 9, 13 7, 13 14 14 8 8 1, 16 1, 16 9 9 10, 13 10, 13 14 14 8 8 1, 16 1, 16 7, 9 7, 9 12, 13 12, 13 14 14 8 8 1, 16 1, 16 9, 13 7, 13 14 14 8 8 1, 16 1, 16 10, 13 10, 13 14 14 8 8 1, 16 1, 16 +0.31V t13+14+ t13+14– t13+4+ t13+4– 14 14 4 4 12 Carry In to Carry Out t10–4– t10+4+ 4 (3.) 4 7 7 Data Inputs t12+13+ t12–13+ 14 14 Select Inputs t9+13+ t7+13+ 14 14 Carry In Inputs t10–13+ t10+13+ 14 14 Data Inputs t13+12+ t13+12– 14 14 Select Inputs t13+9+ t13+7+ 14 14 Carry In Inputs t13+10– t13+10+ 14 14 7 7 fcountup fcountdown 14 14 7 9 13 13 14 14 8 8 1, 16 1, 16 Setup Time Hold Time Counting Frequency 7 7 7 7 9 Rise Time (20 to 80%) t4+ t14+ 4 14 7 7 13 13 4 14 8 8 1, 16 1, 16 Fall Time (20 to 80%) t4– t14– 4 14 7 7 13 13 4 14 8 8 1, 16 1, 16 1. Individually test each input; apply V ILmin to pin under test. VIH appears at clock input (Pin 13). 2. Measure output after clock pulse VIL 3. Before test set all Q outputs to a logic high. 4. To preserve reliable performance, the MC10136 (plastic packaged device only) is to be operated in ambient temperatures above 70°C only when 500lfpm blown air or equivalent heat sinking is provided. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. http://onsemi.com 4 MC10136 SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C VCC1 = VCC2 = +2.0 VDC VIN NOTE: tsetup is the minimum time before the positive transition of the clock pulse (C) that information must be present at the input D or S. thold is the minimum time after the positive tran sition of the clock pulse (C) that information must remain unchanged at the input D or S. INPUT PULSE T+ = T- = 2.0 ±0.2 NS (20 TO 80%) Clock Q Output C COAX 25 µF 1 +1.11 V 50% tC+Q+ tC+Q- 80% 50% 20% tQ+ tQ- TPin +0.31 V 16 Q1 Q2 Q3 TPout COUT 0.1 µF VEE = -3.2 VDC +1.11 V thold H +0.31 V thold L 50ohm termination to ground lo cated in each scope channel input. 50% tsetup H All input and output cables to the scope are equal lengths of 50ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TPout to output pin. tsetup L Q Unused outputs are connected to a 50ohm resistor to ground. CARRY IN SET UP AND HOLD TIMES Carry in tset (L) thold (L) tset (N) C http://onsemi.com 5 thold (N) COAX Q0 8 50% D or S 0.1 µF CIN C D0 D1 D2 D3 S1 S2 CLOCK INPUT VOUT MC10136 APPLICATIONS INFORMATION The MC10136 may also be used as a programmable counter. The configuration of Figure 3 requires no additional gates, although maximum frequency is limited to about 50 MHz. The divider modulus is equal to the program input plus one (M = N + 1), therefore, the counter will divide by a modulus varying from 1 to 16. A second programmable configuration is also illustrated in Figure 4. A pulse swallowing technique is used to speed the counter operation up to 110 MHz typically. The divider modulus for this figure is equal to the program input (M = N). The minimum modulus is 2 because of the pulse swallowing technique, and the modulus may vary from 2 to 15. This programmable configuration requires an additional gate, such as 1/2MC10109 and a flip-flop such as 1/ MC10131. 2 To provide more than four bits of counting capability several MC10136 counters may be cascaded. The Carry In input overrides the clock when the counter is either in the increment mode or the decrement mode of operation. This input allows several devices to be cascaded in a fully synchronous multistage counter as illustrated in Figure 1. The carry is advanced between stages as shown with no external gating. The Carry In of the first device may be left open. The system clock is common to all devices. The various operational modes of the counter make it useful for a wide variety of applications. If used with MECL III devices, prescalers with input toggle frequencies in excess of 300 MHz are possible. Figure 2 shows such a prescaler using the MC10136 and MC1670. Use of the MC10231 in place of the MC1670 permits 200 MHz operation. Figure 1. 12 BIT SYNCHRONOUS COUNTER Figure 2. 300 MHz PRESCALER MSB LSB Cout Cin Cout Cin MC10136 Cin S1 D C C C Logic High Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Input Frequency S2 C Q C Q3 Input Frequency 32 Q MC1670 System Clock NOTE: S1 and S2 are set either for increment or decrement operation. Figure 3. 50 MHz PROGRAMMABLE COUNTER Figure 4. 100 MHz PROGRAMMABLE COUNTER Program Input Program Input fin C fin C D0 D1 D2 D3 Cin S2 S1 Cout fout D0 D1 D2 D3 S2 MC10136 S1 Q0 Q2 Q3 D 1fout = 1/2MC10109 fin Program Input + 1 1/2MC10131 C 2fmax ≅ 50 MHz Typ. 3Divide Ratio is from 1 to 16. 1fout = fin Program Input 2fmax ≅ 110 MHz Typ. 3Divide Ratio is from 2 to 15. http://onsemi.com 6 Q Q fout MC10136 PACKAGE DIMENSIONS PLCC–20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) B Y BRK –N– M T L-M 0.007 (0.180) U M N S T L-M S G1 0.010 (0.250) S N S D –L– –M– Z W 20 D 1 X V S T L-M S N S VIEW D–D A 0.007 (0.180) M T L-M S N S R 0.007 (0.180) M T L-M S N S Z 0.007 (0.180) H M T L-M S N S K1 K C E F 0.004 (0.100) G J –T– VIEW S G1 0.010 (0.250) S T L-M S N S 0.007 (0.180) M T L-M S VIEW S SEATING PLANE NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 7 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2 10 0.310 0.330 0.040 --- MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2 10 7.88 8.38 1.02 --- N S MC10136 –A– 16 9 1 8 –B– CDIP–16 L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE T C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M S T A M INCHES MIN MAX 0.750 0.785 0.240 0.295 --0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0 15 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 8 MC10136/D