SN74LS221 Dual Monostable Multivibrators with Schmitt-Trigger Inputs Each multivibrator of the LS221 features a negative-transitiontriggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. Schmitt-trigger input circuitry for B input allows jitter-free triggering for inputs as slow as 1 volt / second, providing the circuit with excellent noise immunity. A high immunity to VCC noise is also provided by internal latching circuitry. Once triggered, the outputs are independent of further transitions of the inputs and are a function of the timing components. The output pulses can be terminated by the overriding clear. Input pulse width may be of any duration relative to the output pulse width. Output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. With Rext = 2.0 kΩ and Cext = 0, a typical output pulse of 30 nanoseconds is achieved. Output rise and fall times are independent of pulse length. Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability will only be limited by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCC ranges for greater than six decades of timing capacitance (10 pF to 10 µF), and greater than one decade of timing resistance (2.0 to 100 kΩ for the SN74LS221). Pulse width is defined by the relationship: tw(out) = CextRext ln 2.0 ≈ 0.7 Cext Rext; where tW is in ns if Cext is in pF and Rext is in kΩ. If pulse cutoff is not critical, capacitance up to 1000 µF and resistance as low as 1.4 kΩ may be used. The range of jitter-free pulse widths is extended if VCC is 5.0 V and 25°C temperature. http://onsemi.com LOW POWER SCHOTTKY 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B • SN74LS221 is a Dual Highly Stable One-Shot • Overriding Clear Terminates Output Pulse • Pin Out is Identical to SN74LS123 ORDERING INFORMATION GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Device Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current – High – 0.4 mA IOL Output Current – Low 8.0 mA Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Package Shipping SN74LS221N 16 Pin DIP 2000 Units/Box SN74LS221D 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS221/D SN74LS221 (TOP VIEW) VCC 16 1 Rext/ 1 Cext Cext 15 14 1Q 2Q 2 CLR 2B 2A 13 12 11 10 9 Q Q CLR 1 1A 2 1B 3 1 CLR CLR Q Q 4 1Q 5 2Q 6 2 Cext 8 7 2 Rext/ GND Cext Positive logic: Low input to clear resets Q low and Positive logic: Q high regardless of dc levels at A Positive logic: or B inputs. VCC Rext + Cext R/C FUNCTION TABLE (EACH MONOSTABLE) INPUTS OUTPUTS CLEAR A B Q Q L X X H H X H X L ± X X L ° H L L L H H H *° L H *See operational notes — Pulse Trigger Modes TYPE SN74LS221 TYPICAL POWER DISSIPATION 23 mW MAXIMUM OUTPUT PULSE LENGTH 70 s http://onsemi.com 2 SN74LS221 OPERATIONAL NOTES Once in the pulse trigger mode, the output pulse width is determined by tW = RextCextIn2, as long as Rext and Cext are within their minimum and maximum valves and the duty cycle is less than 50%. This pulse width is essentially independent of VCC and temperature variations. Output pulse widths varies typically no more than ±0.5% from device to device. t If the duty cycle, defined as being 100 @ W where T is the T period of the input pulse, rises above 50%, the output pulse width will become shorter. If the duty cycle varies between low and high valves, this causes the output pulse width to vary in length, or jitter. To reduce jitter to a minimum, Rext should be as large as possible. (Jitter is independent of Cext). With Rext = 100K, jitter is not appreciable until the duty cycle approaches 90%. Although the LS221 is pin-for-pin compatible with the LS123, it should be remembered that they are not functionally identical. The LS123 is retriggerable so that the output is dependent upon the input transitions once it is high. This is not the case for the LS221. Also note that it is recommended to externally ground the LS123 Cext pin. However, this cannot be done on the LS221. The SN74LS221 is a dual, monolithic, non-retriggerable, high-stability one shot. The output pulse width, tW can be varied over 9 decades of timing by proper selection of the external timing components, Rext and Cext. Pulse triggering occurs at a voltage level and is, therefore, independent of the input slew rate. Although all three inputs have this Schmitt-trigger effect, only the B input should be used for very long transition triggers (≥1.0 µV/s). High immunity to VCC noise (typically 1.5 V) is achieved by internal latching circuitry. However, standard VCC bypassing is strongly recommended. The LS221 has four basic modes of operation. Clear Mode: If the clear input is held low, irregardless of the previous output state and other input states, the Q output is low. Inhibit Mode: If either the A input is high or the B input is low, once the Q output goes low, it cannot be retriggered by other inputs. Pulse Trigger Mode: A transition of the A or B inputs as indicated in the functional truth table will trigger the Q output to go high for a duration determined by the tW equation described above; Q will go low for a corresponding length of time. The Clear input may also be used to trigger an output pulse, but special logic preconditioning on the A or B inputs must be done as follows: Following any output triggering action using the A or B inputs, the A input must be set high OR the B input must be set low to allow Clear to be used as a trigger. Inputs should then be set up per the truth table (without triggering the output) to allow Clear to be used a trigger for the output pulse. If the Clear pin is routinely being used to trigger the output pulse, the A or B inputs must be toggled as described above before and between each Clear trigger event. Once triggered, as long as the output remains high, all input transitions (except overriding Clear) are ignored. Overriding Clear Mode: http://onsemi.com 3 If the Q output is high, it may be forced low by bringing the clear input low. SN74LS221 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VT+ VT– VT+ Parameter Min Positive-Going Threshold Voltage at C Input Negative-Going Threshold Voltage at C Input 0.7 Positive-Going Threshold Voltage at B Input Negative-Going Threshold Voltage at B Input 0.8 VIH Input HIGH Voltage 2.0 VIL Input LOW Voltage VIK Input Clamp Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current Input A Input B Clear IOS Short Circuit Current (Note 1) Power Supply Current Quiescent Triggered Max Unit 1.0 2.0 V 0.8 1.0 VT– ICC Typ V 2.0 0.9 V VCC = MIN VCC = MIN VCC = MIN VCC = MIN V Guaranteed Input HIGH Voltage for A Input V Guaranteed Input LOW Voltage for A Input V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX 0.5 V IOL = 8.0 mA 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 4.7 11 mA VCC = MAX 19 27 0.8 – 1.5 2.7 V Test Conditions 3.4 0.35 – 0.4 – 0.8 – 0.8 – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. http://onsemi.com 4 VCC = MIN SN74LS221 AC CHARACTERISTICS (VCC = 5.0 V, TA = 25°C) From (Input) To (Output) A Limits Typ Max Q 45 70 B Q 35 55 A Q 50 80 B Q 40 65 tPHL Clear Q 35 55 ns tPLH Clear Q 44 65 ns 70 120 150 20 47 70 600 670 750 6.0 6.9 7.5 Symbol tPLH tPHL tW(out) ( ) Min Unit Test Conditions ns Cext = 80 pF, pF Rext = 2.0 20Ω ns A or B CL = 15 pF, See Figure 1 Cext = 80 pF, Rext = 2.0 Ω Cext = 0, Rext = 2.0 kΩ ns Q or Q Cext = 100 pF, Rext = 10 kΩ Cext = 1.0 µF, Rext = 10 kΩ ms AC SETUP REQUIREMENTS (VCC = 5.0 V, TA = 25°C) Limits Symbol Min Parameter Typ Max Unit Rate of Rise or Fall of Input Pulse dv/dt Schmitt, B 1.0 V/s Logic Input, A 1.0 V/µs A or B, tW(in) 40 ns Clear, tW (clear) 40 Input Pulse Width tW ts Clear-Inactive-State Setup Time 15 ns Rext External Timing Resistance 1.4 100 kΩ Cext External Timing Capacitance 0 1000 µF RT = 2.0 kΩ 50 % RT = MAX Rext 90 Output Duty Cycle http://onsemi.com 5 SN74LS221 AC WAVEFORMS tW(in) 3V B INPUT 1.3 V 0V ≥60 ns 3V CLEAR tPLH 0V tPHL VOH Q OUTPUT tPHL VOL tPLH VOH Q OUTPUT VOL A INPUT IS LOW. TRIGGER FROM B, THEN CLEAR — CONDITION 1 3V B INPUT 0V ≥ 60 ns 3V 1.3 V CLEAR 0V VOH Q OUTPUT VOL A INPUT IS LOW. TRIGGER FROM B, THEN CLEAR — CONDITION 2 3V B INPUT ≥ 50 ns ≥0 ts CLEAR 0V 3V 0V TRIGGERED VOH Q OUTPUT NOT TRIGGERED A INPUT IS LOW. tW(out) VOL CLEAR OVERRIDING B, THEN TRIGGER FROM B 3V B INPUT ≥ 50 ns CLEAR ≥ 50 ns 1.3 V 0V 3V 0V VOH Q OUTPUT VOL A INPUT IS LOW. TRIGGERING FROM POSITIVE TRANSITION OF CLEAR Figure 1. http://onsemi.com 6 SN74LS221 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C DIM A B C D F G H J K L M S L S SEATING PLANE –T– K H G D M J 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 SN74LS221 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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