MC1741C Internally Compensated, High Performance Operational Amplifier The MC1741C was designed for use as a summing amplifier, integrator, or amplifier with operating characteristics as a function of the external feedback components. • No Frequency Compensation Required • Short Circuit Protection • Offset Voltage Null Capability • Wide Common Mode and Differential Voltage Ranges • Low Power Consumption • No Latch Up http://onsemi.com MARKING DIAGRAMS 8 PDIP–8 P1 SUFFIX CASE 626 8 MC1741CP1 AWL YYWW 1 1 8 SO–8 D SUFFIX CASE 751 8 1 1741C ALYW 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week PIN CONNECTIONS Equivalent Circuit Schematic (1/4 of Circuit Shown) G Noninverting Input 1 Inv. Input 2 Noninv. Input 3 VEE 4 VCC 39k 25 50 50k 1.0k 5.0k Semiconductor Components Industries, LLC, 2000 April, 2000 – Rev. 6 50k N.C. 7 VCC 6 Output 5 Offset Null ORDERING INFORMATION 30pF 7.5k Output Offset Null + 8 (Top View) 4.5k Inverting Input 1.0k Offset Null 50 VEE 1 Device Package Shipping MC1741CD SO–8 98 Units/Rail MC1741CDR2 SO–8 2500 Tape & Reel PDIP–8 50 Units/Rail MC1741CP1 Publication Order Number: MC1741C/D MC1741C MAXIMUM RATINGS Rating Symbol Value Unit VCC, VEE ±18 Vdc VID ±30 V Input Common Mode Voltage (Note 1.) VICM ±15 V Output Short Circuit Duration (Note 2.) tSC Continuous – Operating Ambient Temperature Range TA 0 to +70 °C Storage Temperature Range Tstg –55 to +125 °C Power Supply Voltage Input Differential Voltage 1. For supply voltages less than +15 V, the absolute maximum input voltage is equal to the supply voltage. 2. Supply voltage equal to or less than 15 V. ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Input Offset Voltage (RS ≤ 10 k) VIO – 2.0 6.0 mV Input Offset Current IIO – 20 200 nA Input Bias Current IIB – 80 500 nA Input Resistance ri 0.3 2.0 – MΩ Input Capacitance Ci – 1.4 – pF Offset Voltage Adjustment Range VIOR – ±15 – mV Common Mode Input Voltage Range VICR ±12 ±13 – V Large Signal Voltage Gain (VO = ±10 V, RL ≥ 2.0 k) AVOL 20 200 – V/mV ro – 75 – Ω Common Mode Rejection (RS ≤ 10 k) CMR 70 90 – dB Supply Voltage Rejection (RS ≤ 10 k) PSR 75 – – dB ±12 ±10 ±14 ±13 – – Output Resistance Output Voltage Swing (RL ≥ 10 k) (RL ≥ 2.0 k) VO V Output Short Circuit Current ISC – 20 – mA Supply Current ID – 1.7 2.8 mA Power Consumption PC – 50 85 mW Transient Response (Unity Gain, Noninverting) (VI = 20 mV, RL ≥ 2.0 k, CL ≤ 100 pF) Rise Time (VI = 20 mV, RL ≥ 2.0 k, CL ≤ 100 pF) Overshoot (VI = 10 V, RL ≥ 2.0 k, CL ≤ 100 pF) Slew Rate tTLH os SR – – – 0.3 15 0.5 – – – µs % V/µs ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh, unless otherwise noted.)* Characteristic Symbol Min Typ Max Unit Input Offset Voltage (RS ≤ 10 kΩ) VIO – – 7.5 mV Input Offset Current (TA = 0° to +70°C ) IIO – – 300 nA Input Bias Current (TA = 0° to +70°C ) IIB – – 800 nA Supply Voltage Rejection (RS ≤ 10 k) PSR 75 – – dB VO ±10 ±13 – V AVOL 15 – – V/mV Output Voltage Swing (RL ≥ 2.0 k) Large Signal Voltage Gain (RL ≥ 2.0 k, VO = ±10 V) * Tlow = 0°C Thigh = 70°C http://onsemi.com 2 MC1741C 100 BW = 1.0 Hz to 1.0 kHz en, INPUT NOISE ( µVpk) en, INPUT NOISE ( µVpk) 1000 100 10 0 10 100 1.0 k 10 k RS, SOURCE RESISTANCE (Ω) 100 k 1.0 0.1 1.0 M Figure 1. Burst Noise versus Source Resistance 100 1.0 10 k 100 k RS, SOURCE RESISTANCE (Ω) 1.0 M 14.0 e n, INPUT NOISE ( nV/ √ Hz ) en, OUTPUT NOISE (mVrms) 10 Figure 2. RMS Noise versus Source Resistance 10 AV = 1000 1.0 100 10 0.1 1.0 0.01 BW = 1.0 Hz to 1.0 kHz 10 10 100 1.0 k 10 k 100 k 12.0 AV = 10, RS = 100 k Ω 10.0 8.0 6.0 4.0 2.0 0 10 1.0 M 100 RS, SOURCE RESISTANCE (Ω) 1.0 k 100 k + 100 k Figure 4. Spectral Noise Density Positive Threshold Voltage 100 k 100 k 10 k f, FREQUENCY (Hz) Figure 3. Output Noise versus Source Resistance - 1.0 k x500 Operational Amplifier Under Test + To Pass / Fail Indicator x2 + Low Pass Filter 1.0 Hz to 1.0 kHz - Negative Threshold Voltage Unlike conventional peak reading or RMS meters, this system was especially designed to provide the quick response time essential to burst (popcorn) noise testing. The test time employed is 10 sec and the 20 mV peak limit refers to the operational amplifier input thus eliminating errors in the closed loop gain factor of the operational amplifier. Figure 5. Burst Noise Test Circuit http://onsemi.com 3 28 120 24 100 Avol , VOLTAGE GAIN (dB) VO, OUTPUT VOLTAGE (Vpp ) MC1741C 20 16 12 (Voltage Follower) THD < 5% 8.0 60 40 20 0 4.0 0 80 10 100 1.0 k f, FREQUENCY (Hz) 10 k -20 100 k 1.0 11 VO, OUTPUT VOLTAGE (Vpp ) ±15 V Supplies 100 k ±12 V 9.0 ±9.0 V 7.0 5.0 ±6.0 V 3.0 100 200 500 700 1.0 k 2.0 k -13 1.0 M 10 M ±12 V -9.0 -7.0 ±9.0 V -5.0 ±6.0 V -3.0 -1.0 5.0 k 7.0 k 10 k ±15 V Supplies -11 100 200 500 700 1.0 k 2.0 k 5.0 k 7.0 k 10 RL, LOAD RESISTANCE (Ω) RL, LOAD RESISTANCE (Ω) Figure 8. Positive Output Voltage Swing versus Load Resistance VO, OUTPUT VOLTAGE SWING (Vpp ) 10 k -15 13 28 26 24 22 20 18 16 14 12 10 8.0 6.0 4.0 2.0 0 1.0 k Figure 7. Open Loop Frequency Response 15 VO, OUTPUT VOLTAGE (Vpp ) 100 f, FREQUENCY (Hz) Figure 6. Power Bandwidth (Large Signal Swing versus Frequency) 1.0 10 Figure 9. Negative Output Voltage Swing versus Load Resistance 30 V Supply 27 V 24 V 100 µF 21 V 10 k 1.0 k 18 V 15 V 12 V 0 9.0 V 6.0 V 5.0 V 1.0 2.0 VCC Vin 200 k 50 k 2 50 k 3.0 4.0 5.0 6.0 7.0 RL, LOAD RESISTANCE (kΩ) 8.0 9.0 200 k 10 Figure 10. Output Voltage Swing versus Load Resistance (Single Supply Operation) 3 + 7 4 100 µF MC1741 RL Figure 11. Single Supply Inverting Amplifier http://onsemi.com 4 MC1741C 5.0 V/DIV Output Input 10 µs/DIV Figure 12. Noninverting Pulse Response To Scope (Input) - To Scope (Output) + RL CL Figure 13. Transient Response Test Circuit 105 AV, VOLTAGE GAIN (dB) 100 95 90 85 80 75 70 0 2.0 4.0 6.0 8.0 10 12 14 16 VCC, |VEE|, SUPPLY VOLTAGES (V) Figure 14. Open Loop Voltage Gain versus Supply Voltage http://onsemi.com 5 18 20 MC1741C PACKAGE DIMENSIONS PDIP–8 P1 SUFFIX CASE 626–05 ISSUE K 8 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 –B– 1 4 DIM A B C D F G H J K L M N F –A– NOTE 2 L C J –T– MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10 0.030 0.040 N SEATING PLANE D M K G H 0.13 (0.005) M T A M B M SO–8 D SUFFIX CASE 751–06 ISSUE T D A 8 E 5 0.25 H 1 M B M 4 h B e X 45 A C SEATING PLANE L 0.10 A1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C B 0.25 M C B S A S http://onsemi.com 6 DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0 7 MC1741C Notes http://onsemi.com 7 MC1741C ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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