Cypress CY2277APVI-12 6x86, k6 clock synthesizer/driver for desktop mobile pcs with intel 82430tx and 2 dimms or 3 so-dimm Datasheet

7A
CY2277A
Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/
Mobile PCs with Intel® 82430TX and 2 DIMMs or 3 SO-DIMMs
Features
• Mixed 2.5V and 3.3V operation
• Complete clock solution to meet requirements of Pentium®, Pentium® II, 6x86, or K6 motherboards
— Four CPU clocks at 2.5V or 3.3V
— Up to eight 3.3V SDRAM clocks
— Seven 3.3V synchronous PCI clocks, one free
running
— Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable
by serial interface
— One 2.5V IOAPIC clock at 14.318 MHz
— Two 3.3V Ref. clocks at 14.318 MHz
• Factory-EPROM programmable CPU, PCI, and USB/IO
clock frequencies for custom configuration
• Factory-EPROM programmable output drive and slew
rate for EMI customization
• MODE Enable pin for CPU_STOP and PCI_STOP
• SMBus serial configuration interface
• Available in space-saving 48-pin SSOP and TSSOP
packages.
Functional Description
The CY2277A is a Clock Synthesizer/Driver for Pentium, Pentium II, 6X86, and K6 portable PCs designed with the Intel®
82430TX or similar chipsets. There are three available options
as shown in the selector guide
The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up
to nine selectable frequencies. There are up to eight 3.3V
SDRAM clocks and seven PCI clocks, running at one half the
CPU clock frequency. One of the PCI clocks is free-running.
Additionally, the part outputs two 3.3V USB/IO clocks at 48
MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and
two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,
USB, and IO clock frequencies are factory-EPROM programmable for easy customization with fast turnaround times.
The CY2277A has power-down, CPU stop and PCI stop pins
for power management control. The CPU stop and PCI stop
are controlled by the MODE pin. They are multiplexed with
SDRAM clock outputs, and are selected when the MODE pin
is driven LOW. Additionally, these inputs are synchronized
on-chip, enabling glitch-free transitions. When the
CPU_STOP input is asserted, the CPU outputs are driven
LOW. When the PCI_STOP input is asserted, the PCI outputs
(except the free-running PCI clock) are driven LOW. Finally,
when the PWR_DWN pin is asserted, the reference oscillator
and PLLs are shut down, and all outputs are driven LOW.
The CY2277A outputs are designed for low EMI emission.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate enable optimal configurations for EMI control.
CY2277A Selector Guide
-1/-1M
-3
-7M
-12/
-12M/
-12I
CPU (60, 66.6 MHz)
4
--
4
4
CPU (33.3, 66.6 MHz)
--
4
--
--
CPU (SMBus selectable)
--
--
--
--
PCI (CPU/2)
7[1]
7[1]
7[1]
7[1]
SDRAM
6/8
6/8
6/8
6/8
2
2
2
2
Clock Outputs
USB/IO (48 or 24 MHz)
IOAPIC (14.318 MHz)
1
1
1
1
Ref (14.318 MHz)
2
2
2
2
<1 ns
1–4 ns
CPU-PCI delay
1–6 ns 1–6 ns
Note:
1. One free-running PCI clock.
Pin Configuration
Logic Block Diagram
VDDQ2
XTALIN
XTALOUT
14.318
MHz
OSC.
STOP
LOGIC
CPU
PLL
SEL
EPROM
MODE
SYS
PLL
/2
Delay
PWR_DWN
SCLK
SDATA
REF1
REF0
VSS
XTALIN
CPUCLK[0–3]
XTALOUT
MODE
VDDQ3
VDDCPU
PCICLK_F
PCICLK0
SDRAM[0–5]
VSS
PCICLK1
SDRAM6/CPU_STOP
PCICLK2
PCICLK3
PCICLK4
SDRAM7/PCI_STOP
VDDQ3
PCICLK5
VSS
SEL
PCI[0–5]
SDATA
SCLK
PCICLK_F
VDDQ3
USBCLK/IOCLK[0:1] USBCLK/IOCLK
USBCLK/IOCLK
VSS
REF [0–1]
(14.318)
STOP
LOGIC
SERIAL
INTERFACE
CONTROL
LOGIC
Cypress Semiconductor Corporation
Document #: 38-07332 Rev. *A
Divide and
Mux Logic
•
3901 North First Street
•
San Jose
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CY2277A-1,-1M,-3,-7M,-12,-12M,-12I
SSOP
Top View
IOAPIC (14.318 MHz)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AVDD
PWR_SEL
VDDQ2
IOAPIC
PWR_DWN
VSS
CPUCLK0
CPUCLK1
VDDCPU
CPUCLK2
CPUCLK3
VSS
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDDQ3
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
AVDD
CA 95134 • 408-943-2600
Revised December 7, 2002
CY2277A
Pin Summary
Name
Pins
Description
VDDQ3
7, 15, 21, 28, 34
3.3V Digital voltage supply
VDDQ2
46
IOAPIC Digital voltage supply, 2.5V
VDDCPU
40
CPU Digital voltage supply, 2.5V or 3.3V
AVDD
25, 48
3.3V Analog voltage supply
VSS
3, 10, 17, 24, 31, 37, 43 Ground
XTALIN[2]
4
Reference crystal input
XTALOUT[2]
5
Reference crystal feedback
MODE
6
Mode select input, enables power management features
SEL
18
Select input to enable 66.66 MHz or 60 MHz CPU clock (See Function
tables.)
SDATA
19
SMBus serial data input for serial configuration port
SCLK
20
SMBus serial clock input for serial configuration port
PWR_DWN
44
Active low control input to put osc., PLLs, and outputs in power down state
PWR_SEL
47
Power select input, indicates whether VDDCPU is at 2.5V or 3.3V
HIGH = 3.3V, LOW=2.5V (internal pull-up to VDD)
SDRAM7/PCI_STOP
26
SDRAM clock output. Also, active LOW control input to stop PCI clocks,
enabled when MODE is LOW
SDRAM6/CPU_STOP
27
SDRAM clock output. Also, active LOW control input to stop CPU clocks,
enabled when MODE is LOW
SDRAM[0:5]
36, 35, 33, 32, 30, 29
SDRAM clock outputs, have same frequency as CPU clocks
CPUCLK[0:3]
42, 41, 39, 38
CPU clock outputs
PCICLK[0:5]
9, 11, 12, 13, 14, 16
PCI clock outputs
PCICLK_F
8
PCI clock output, free-running
IOAPIC
45
IOAPIC clock output
REF[0:1]
1, 2
Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load
USBCLK/IOCLK
22, 23
USB or IO clock outputs, frequency selected by serial word
Note:
2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
Document #: 38-07332 Rev. *A
Page 2 of 19
CY2277A
Function Table (-1, -1M, -7M, -12, -12M, -12I)
SEL
CPUCLK[0:3]
SDRAM[0:7]
XTALIN
PCICLK[0:5]
PCICLK_F
REF[0:1]
IOAPIC
USBCLK / IOCLK[3]
0
14.318 MHz
60.0 MHz
30.0 MHz
14.318 MHz
48.0 MHz / 24.0 MHz
1
14.318 MHz
66.67 MHz
33.33 MHz
14.318 MHz
48.0 MHz / 24.0 MHz
Function Table (-3)
SEL
CPUCLK[0:3]
SDRAM[0:7]
XTALIN
PCICLK[0:5]
PCICLK_F
REF[0:1]
IOAPIC
USBCLK / IOCLK[3]
0
14.318 MHz
33.33 MHz
16.67 MHz
14.318 MHz
48.0 MHz / 24.0 MHz
1
14.318 MHz
66.67 MHz
33.33 MHz
14.318 MHz
48.0 MHz / 24.0 MHz
Actual Clock Frequency Values (-1, -1M, -3, -7M,
-12, -12M, -12I)
Clock Output
Target
Frequency
(MHz)
Actual
Frequency
(MHz)
CPU and PCI Clock Driver Strengths
• Matched impedances on both rising and falling edges on
the output drivers
• Output impedance: 25Ω (typical) measured at 1.5V
PPM
CPUCLK,
SDRAM
66.67
66.654
–195
CPUCLK,
SDRAM
60.0
60.0
0
USBCLK[4]
48.0
48.008
167
IOCLK
24.0
24.004
167
Notes:
3. On power-up, the default frequency on these outputs is 48 MHz.
4. Meets Intel USB clock requirements.
Document #: 38-07332 Rev. *A
Page 3 of 19
CY2277A
Power Management Logic
CPU_STOP
PCI_STOP
PWR_DWN
CPUCLK
X
X
0
LOW
0
0
1
0
1
1
1
0
1
1
PCICLK
PCICLK_F
Other Clocks
LOW
Stopped
Stopped
Off
Off
LOW
LOW
Running
Running
Running
Running
LOW
33/30 MHz
Running
Running
Running
Running
1
66/60 MHz
LOW
Running
Running
Running
Running
1
66/60 MHz
33/30 MHz
Running
Running
Running
Running
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• SMBus Address for the CY2277A is:
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
----
Osc.
PLLs
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit
Pin #
Description
Bit 7 --
(Reserved) drive to ‘0’
Bit 6 --
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M, -12,
-12M, -12I
Bit 5 --
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M, -12,
-12M, -12I
Bit 4 --
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M, -12,
-12M, -12I
Bit 3 23
48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz
Bit 2 22
48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz
Bit 1 -Bit 0
Bit 1
1
1
0
0
Bit 0
1 - Three-State (see table below)
0 - N/A
1 - Test Mode (see table below)
0 - Normal Operation
Select Functions
Outputs
Functional Description
CPU
PCI, PCI_F
SDRAM
Ref
IOAPIC
IOCLK
USBCLK
Three-State
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Test Mode
TCLK/2[5]
TCLK/4
TCLK/2
TCLK
TCLK
TCLK/4
TCLK/2
Note:
5. TCLK supplied on the XTALIN, PIN 4.
Document #: 38-07332 Rev. *A
Page 4 of 19
CY2277A
Byte 1: CPU, 24/48 MHz Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Byte 2: PCI Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
23
48/24 MHz (Active/Inactive)
Bit 7
--
(Reserved) drive to ‘0’
Bit 6
22
48/24 MHz (Active/Inactive)
Bit 6
8
PCICLK_F (Active/Inactive)
Bit 5
--
(Reserved) drive to ‘0’
Bit 5
16
PCICLK5 (Active/Inactive)
Bit 4
N/A
Not Used, drive 0
Bit 4
14
PCICLK4 (Active/Inactive)
Bit 3
38
CPUCLK3 (Active/Inactive)
Bit 3
13
PCICLK3 (Active/Inactive)
Bit 2
39
CPUCLK2 (Active/Inactive)
Bit 2
12
PCICLK2 (Active/Inactive)
Bit 1
41
CPUCLK1 (Active/Inactive)
Bit 1
11
PCICLK1 (Active/Inactive)
Bit 0
42
CPUCLK0 (Active/Inactive)
Bit 0
9
PCICLK0 (Active/Inactive)
Byte 3: SDRAM Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Byte 4: SDRAM Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7 26
SDRAM7 (Active/Inactive)
Bit 7
N/A
Not used, drive to ‘0’
Bit 6 27
SDRAM6 (Active/Inactive)
Bit 6
N/A
Not used, drive to ‘0’
Bit 5 29
SDRAM5 (Active/Inactive)
Bit 5
N/A
Not used, drive to ‘0’
Bit 4 30
SDRAM4 (Active/Inactive)
Bit 4
N/A
Not used, drive to ‘0’
Bit 3 32
SDRAM3 (Active/Inactive)
Bit 3
N/A
Not used, drive to ‘0’
Bit 2 33
SDRAM2 (Active/Inactive)
Bit 2
N/A
Not used, drive to ‘0’
Bit 1 35
SDRAM1 (Active/Inactive)
Bit 1
N/A
Not used, drive to ‘0’
Bit 0 36
SDRAM0 (Active/Inactive)
Bit 0
N/A
Not used, drive to ‘0’
Byte 5: Peripheral Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Byte 6: Reserved, for future use
Description
Bit 7
--
(Reserved) drive to ‘0’
Bit 6
--
(Reserved) drive to ‘0’
Bit 5
--
(Reserved) drive to ‘0’
Bit 4
45
IOAPIC (Active/Inactive)
Bit 3
--
(Reserved) drive to ‘0’
Bit 2
--
(Reserved) drive to ‘0’
Bit 1
1
REF1 (Active/Inactive)
Bit 0
2
REF0 (Active/Inactive)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Junction Temperature............................................... +150°C
Supply Voltage ..................................................–0.5 to +7.0V
Package Power Dissipation.............................................. 1W
Input Voltage ............................................ –0.5V to VDD + 0.5
Static Discharge Voltage............................................ >2000V
(per MIL-STD-883, Method 3015, like VDD pins tied together)
Storage Temperature (Non-Condensing) .... –65°C to +150°C
Document #: 38-07332 Rev. *A
Page 5 of 19
CY2277A
Operating Conditions[6]
Parameter
AVDD, VDDQ3
VDDCPU
VDDQ2
TA
TA
CL
f(REF)
tPU
Description
Analog and Digital Supply Voltage
2.5V CPU Supply Voltage (-1,-1M, -3, -7M)
2.5V CPU Supply Voltage (-12, -12M, -12I)
3.3V CPU Supply Voltage
2.5V IOAPIC Supply Voltage (-1,-1M, -3, -7M)
2.5V IOAPIC Supply Voltage (-12, -12M, -12I)
3.3V IOAPIC Supply Voltage
Operating Temperature, Commercial
Operating Temperature, Industrial
Max. Capacitive Load on
CPUCLK, USBCLK/IOCLK, REF1, IOAPIC
PCICLK, SDRAM
REF0
Reference Frequency, Oscillator Nominal Value
Power-up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
Min.
3.135
2.375
2.375
3.135
2.375
2.375
3.135
0
–40
Max.
3.465
2.9
2.625
3.465
2.9
2.625
3.465
70
85
Unit
V
V
10
30, 20
20
14.318
20
30
45
14.318
MHz
0.05
50
ms
V
°C
°C
pF
Electrical Characteristics (-1, -3, -12)
Parameter
Description
Test Conditions
Min. Max. Unit
VIH
High-level Input Voltage
Except Crystal Inputs
VIL
Low-level Input Voltage
Except Crystal Inputs
0.8
V
VILiic
Low-level Input Voltage
SMBus inputs only
0.7
V
VOH
High-level Output
Voltage[7]
VDDQ2 = VDDCPU = 2.375V
2.0
IOH = 18 mA CPUCLK
V
2.0
V
IOH = 18 mA IOAPIC
VOL
Low-level Output Voltage[7]
VDDQ2 = VDDCPU = 2.375V
IOL = 29 mA CPUCLK
0.4
V
IOL = 29 mA IOAPIC
VOH
High-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V
IOH = 32 mA CPUCLK
2.4
V
IOH = 36 mA SDRAM
IOH = 32 mA PCICLK
IOH = 26 mA USBCLK
IOH = 26 mA IOCLK
IOH = 36 mA REF0
IOH = 26 mA REF1
VOL
Low-level Output Voltage[7]
VDDQ3, AVDD, VDDCPU = 3.135V
IOL = 24 mA CPUCLK
0.4V
V
IOL = 29 mA SDRAM
IOL = 26 mA PCICLK
IOL = 21 mA USBCLK
IOL = 21 mA IOCLK
IOL = 29 mA REF0
IOL = 21 mA REF1
IIH
Input High Current
VIH = VDD
IIL
Input Low Current
VIL = 0V, except PWR_SEL
IIL
Input Low Current
VIL = 0V, PWR_SEL only
IOZ
Output Leakage Current
Three-state
Current[7, 8]
–10
–10
+10
µA
10
µA
100
µA
+10
µA
IDD
Power Supply
VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz
250
mA
IDD
Power Supply Current[7, 8]
VDD = 3.465V, VIN = 0 or VDD, Unloaded Outputs
120
mA
IDDS
Power-down Current
Current draw in power-down state, PWR_SEL = VDD
150
µA
Document #: 38-07332 Rev. *A
Page 6 of 19
CY2277A
Electrical Characteristics (-1, -3, -12)
Parameter
Description
Test Conditions
Min. Max. Unit
Test Conditions
Min. Max. Unit
Notes:
6. Electrical parameters are guaranteed with these operating conditions.
7. Guaranteed by design and characterization. Not 100% tested in production.
8. Power supply current will vary with number of outputs which are running.
Electrical Characteristics (-1M, -7M, -12M)
Parameter
Description
VIH
High-level Input Voltage
Except Crystal Inputs
VIL
Low-level Input Voltage
Except Crystal Inputs
VILiic
Low-level Input Voltage
SMBus inputs only
VOH
High-level Output Voltage[7] VDDQ2 = VDDCPU = 2.375V
IOH = 12.6 mA CPUCLK 1.75
VOL
Low-level Output Voltage[7]
IOL = 18.2 mA CPUCLK
VOH
High-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V
2.0
IOH = 16.7mA
VDDQ2 = VDDCPU = 2.375V
V
0.8
V
0.7
V
V
IOAPIC
0.4
V
IOL = 23.1 mA IOAPIC
IOH = 32.2 mA SDRAM
2.4
V
IOH = 32.2 mA PCICLK
IOH = 32.2 mA USBCLK
IOH = 32.2 mA IOCLK
IOH = 32.2 mA REF0
IOH = 32.2 mA REF1
VOL
Low-level Output Voltage
[7]
VDDQ3, AVDD, VDDCPU = 3.135V
IOL = 23.8 mA SDRAM
0.8V
V
+10
µA
10
µA
IOL = 23.8 mA PCICLK
IOL = 23.8 mA USBCLK
IOL = 23.8 mA IOCLK
IOL = 23.8 mA REF0
IOL = 23.8 mA REF1
IIH
Input High Current
VIH = VDD
IIL
Input Low Current
VIL = 0V, except PWR_SEL
IIL
Input Low Current
VIL = 0V, PWR_SEL only
IOZ
Output Leakage Current
Three-state
IDD
Power Supply Current[7, 8]
IDD
Power Supply Current[7, 8]
IDDS
Power-down Current
Document #: 38-07332 Rev. *A
–10
100
µA
+10
µA
VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz
250
mA
VDD = 3.465V, VIN = 0 or VDD, Unloaded Outputs
120
mA
Current draw in power-down state, PWR_SEL = VDD
150
µA
–10
Page 7 of 19
CY2277A
Electrical Characteristics (-12I)
Parameter
Description
Test Conditions
Min. Max. Unit
VIH
High-level Input Voltage
Except Crystal Inputs
VIL
Low-level Input Voltage
Except Crystal Inputs
0.8
V
VILiic
Low-level Input Voltage
SMBus inputs only
0.7
V
VOH
High-level Output Voltage[7] VDDQ2 = VDDCPU = 2.375V
IOH = 18 mA
CPUCLK
IOH = 18 mA
IOAPIC
VOL
Low-level Output Voltage[7]
IOL = 29 mA
CPUCLK
IOL = 29 mA
IOAPIC
VOH
High-level Output Voltage[7] VDDQ3, AVDD, VDDCPU = 3.135V
IOH = 32 mA
CPUCLK
VOL
Low-level Output
Voltage[7]
VDDQ2 = VDDCPU = 2.375V
VDDQ3, AVDD, VDDCPU = 3.135V
2.0
IOH = 36 mA
SDRAM
IOH = 32 mA
PCICLK
IOH = 26 mA
USBCLK
IOH = 26 mA
IOCLK
IOH = 36 mA
REF0
IOH = 26 mA
REF1
IOH = 24mA
CPUCLK
IOH = 29 mA
SDRAM
IOH = 26 mA
PCICLK
IOL = 21 mA
USBCLK
IOH = 21 mA
IOCLK
IOL = 29mA
REF0
IOH = 21 mA
REF1
V
1.75
V
0.4
2.4
V
0.8V
V
+20
µA
IIH
Input High Current
VIH = VDD
IIL
Input Low Current
VIL = 0V, except PWR_SEL
10
µA
IIL
Input Low Current
VIL = 0V, PWR_SEL only
100
µA
IOZ
Output Leakage Current
+10
µA
[7, 8]
Three-state
–20
V
–10
IDD
Power Supply Current
VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.67 MHz
250
mA
IDD
Power Supply Current[7, 8]
VDD = 3.465V, VIN = 0 or VDD, Unloaded Outputs
120
mA
IDDS
Power-down Current
Current draw in power-down state, PWR_SEL = VDD
150
µA
Document #: 38-07332 Rev. *A
Page 8 of 19
CY2277A
Switching Characteristics (-1, -3)[9, 10, 11]
Parameter
Output
Description
Test Conditions
[12]
t1 = t1A ÷ t1B
Min.
Typ.
Max.
Unit
45
50
55
%
40
50
t1
CPUCLK
SDRAM
USBCLK
IOCLK
REF [0,1]
IOAPIC
Output Duty Cycle
t1
PCI
Output Duty Cycle[12]
t1 = t1A ÷ t1B
55
%
t2
CPUCLK,
IOAPIC
CPU and IOAPIC Clock
Rising and Falling Edge
Rate
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
CPU clocks at 66.66 MHz
0.75
0.75
4.0
4.0
V/ns
t2
PCI
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.75
4.0
V/ns
t2
USBCLK,
IOCLK,
REF0
USB, I/O, REF0 Clock
Rising and Falling Edge
Rate
Between 0.4V and 2.4V
0.8
4.0
V/ns
t2
SDRAM
SDRAM Rising and Falling Edge Rate
Between 0.4V and 2.4V
SDRAM clocks at 66.66 MHz
1.0
4.0
V/ns
t2
REF1
REF1 Rising and Falling
Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.0
ns
t3
USBCLK,
IOCLK
USB Clock and I/O Clock
Rise Time
Between 0.4V and 2.4V
2.5
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
Between 2.4V and 0.4V, VDDCPU = 3.3V
2.13
2.0
ns
t4
USBCLK,
IOCLK
USB Clock and I/O Clock
Fall Time
Between 2.4V and 0.4V
2.5
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
100
400
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
(-1, -3)
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
2.0
6.0
ns
t7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, VDDCPU = 2.5V
775
ps
t8
CPUCLK
Cycle-Cycle Clock Jitter
Measured at 1.25V for 2.5V clocks and
at 1.5V for 3.3V clocks
450
ps
t8
SDRAM
Cycle-Cycle Clock Jitter
Measured at 1.5V for 3.3V clocks
650
ps
t8
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
500
ps
t8
USBCLK,
IOCLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
1.3
ns
t9
CPUCLK,
PCICLK,
SDRAM
Power-up Time
CPU, PCI, and SDRAM clock stabilization from power-up
3
ms
t10
CPU, PCI,
SDRAM
Frequency Slew Rate
Rate of change of frequency
0.4
0.5
1.0
2
MHz/
ms
Notes:
9. All parameters specified with loaded outputs.
10. Over the operating range unless otherwise specified.
11. Parameters specified with: VDDCPU = 2.5V, VDDQ2 = 2.5V, VDDQ3 = 3.3V.
12. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V.
Document #: 38-07332 Rev. *A
Page 9 of 19
CY2277A
Switching Characteristics (-1M, -7M, -12M)[9, 10, 11]
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
45
50
55
%
45
50
t1
CPUCLK
SDRAM
USBCLK
REF [0,1]
IOAPIC
Output Duty Cycle[12]
t1 = t1A ÷ t1B
t1
PCI
Output Duty Cycle[12]
t1 = t1A ÷ t1B
55
%
t2
CPUCLK,
IOAPIC
CPU and IOAPIC Clock
Rising and Falling Edge
Rate
Between 0.4V and 2.0V, VDDCPU = 2.5V
CPU clocks at 66.66 MHz
0.60
4.0
V/ns
t2
PCI
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.0V, VDDCPU = 2.5V
0.65
4.0
V/ns
t2
USBCLK,
REF0
USB, REF0 Clock Rising
and Falling Edge Rate
Between 0.4V and 2.4V
0.65
4.0
V/ns
t2
SDRAM
SDRAM Rising and Falling Edge Rate
Between 0.4V and 2.4V
SDRAM clocks at 66.66 MHz
0.70
4.0
V/ns
t2
REF1
REF1 Rising and Falling
Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
0.4
2.4
ns
t3
USBCLK
USB Clock Rise Time
Between 0.4V and 2.0V
2.5
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
2.4
ns
t4
USBCLK
USB Clock Fall Time
Between 2.0V and 0.4V
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
t5
PCICLK
PCI-PCI Clock Skew
t5
SDRAM
t6
0.4
2.5
ns
250
ps
Measured at 1.5V
400
ps
SDRAM-SDRAM Clock
Skew
Measured at 1.5V
300
ps
CPUCLK,
PCICLK
CPU-PCI Clock Skew
-1M, -12M
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
6.0
ns
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
-7M
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
750
ps
t7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, VDDCPU = 2.5V
600
ps
t8
CPUCLK
Cycle-Cycle Clock Jitter
Measured at 1.25V for 2.5V clocks
525
ps
t8
SDRAM
Cycle-Cycle Clock Jitter
Measured at 1.5V
600
ps
t8
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
400
ps
t8
USBCLK,
IOCLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
900
ps
t9
CPUCLK,
PCICLK,
SDRAM
Power-up Time
CPU, PCI, and SDRAM clock stabilization from power-up
3
ms
t10
CPU, PCI,
SDRAM
Frequency Slew Rate
Rate of change of frequency
Document #: 38-07332 Rev. *A
100
1.0
2.0
2
MHz/
ms
Page 10 of 19
CY2277A
Switching Characteristics (-12)[9, 10, 11]
Parameter
Output
Description
Test Conditions
Min.
Typ.
50
Max.
Unit
t1
All Clocks
Output Duty Cycle
t1 = t1A ÷ t1B
45
55
%
t2
CPUCLK,
IOAPIC
CPU and IOAPIC Clock
Rising and Falling Edge
Rate
Between 0.6V and 1.8V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
CPU clocks at 66.6 MHz
1.0
1.0
4.0
4.0
V/ns
t2
PCI
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V, VDDCPU = 3.3V
1.0
4.0
V/ns
t2
REF0
REF0 Clock Rising and
Falling Edge Rate
Between 0.8V and 2.4V, VDDCPU = 3.3V
1.0
4.0
V/ns
t2
SDRAM
SDRAM Rising and Falling Edge Rate
Between 0.5V and 2.0V
SDRAM clocks at 66.6 MHz
1.5
4.0
V/ns
t2
REF1
USBCLK
IOCLK
REF1, USB and IO Rising
and Falling Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.4
0.4
2.0
2.0
ns
t3
USBCLK,
IOCLK
USB Clock and I/O Clock
Rise Time
Between 0.4V and 2.4V
1.0
4.0
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
Between 2.4V and 0.4V, VDDCPU = 3.3V
0.4
0.4
2.0
2.0
ns
t4
USBCLK,
IOCLK
USB Clock and I/O Clock
Fall Time
Between 2.4V and 0.4V
1.0
4.0
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
250
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
(-12)
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
4.0
ns
t7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, VDDCPU = 2.5V
500
ps
t8
CPUCLK
Cycle-Cycle Clock Jitter
Measured at 1.25V for 2.5V clocks and
at 1.5V for 3.3V clocks
250
ps
t8
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
500
ps
t9
CPUCLK,
PCICLK,
SDRAM
Power-up Time
CPU, PCI, and SDRAM clock stabilization from power-up
3
ms
t10
CPU, PCI,
SDRAM
Frequency Slew Rate
Rate of change of frequency
Document #: 38-07332 Rev. *A
[12]
100
1.0
2
MHz/
ms
Page 11 of 19
CY2277A
Switching Characteristics (-12I)[9, 10, 11]
Parameter
Output
Description
Test Conditions
Min.
Typ.
50
Max.
Unit
t1
All Clocks
Output Duty
t1 = t1A ÷ t1B
45
55
%
t2
CPUCLK,
IOAPIC
CPU and IOAPIC Clock
Rising and Falling Edge
Rate
Between 0.6V and 1.8V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
CPU clocks at 66.6 MHz
1.0
.8
4.0
4.0
V/ns
t2
PCI
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V, VDDCPU = 3.3V
.9
4.0
V/ns
t2
REF0
REF0 Clock Rising and
Falling Edge Rate
Between 0.8V and 2.4V, VDDCPU = 3.3V
1.0
4.0
V/ns
t2
SDRAM
SDRAM Rising and Falling Edge Rate
Between 0.5V and 2.0V
SDRAM clocks at 66.6 MHz
1
4.0
V/ns
t2
REF1
USBCLK
IOCLK
REF1, USB and IO Rising
and Falling Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.4
0.4
3.0
2.0
ns
t3
USBCLK,
IOCLK
USB Clock and I/O Clock
Rise Time
Between 0.4V and 2.4V
1.0
4.0
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
Between 2.4V and 0.4V, VDDCPU = 3.3V
0.4
0.4
3.0
2.0
ns
t4
USBCLK,
IOCLK
USB Clock and I/O Clock
Fall Time
Between 2.4V and 0.4V
1.0
4.0
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
(-12)
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
t7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew
t8
CPUCLK
t8
t9
t10
Cycle[12]
250
ps
4.0
ns
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, VDDCPU = 2.5V
625
ps
Cycle-Cycle Clock Jitter
Measured at 1.25V for 2.5V clocks and
at 1.5V for 3.3V clocks, VDDCPU =2.5V
350
ps
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
500
ps
CPUCLK,
PCICLK,
SDRAM
Power-up Time
CPU, PCI, and SDRAM clock stabilization from power-up
3
ms
CPU, PCI,
SDRAM
Frequency Slew Rate
Rate of change of frequency
Document #: 38-07332 Rev. *A
100
1.0
2
MHz/
ms
Page 12 of 19
CY2277A
Timing Requirement for the SMBus
Parameter
Description
t10
SCLK Clock Frequency
Min.
Max.
Unit
0
100
kHz
4.7
µs
4
µs
The LOW period of the clock.
4.7
µs
The HIGH period of the clock.
4
µs
4.7
µs
t11
Time the bus must be free before a new transmission can start
t12
Hold time start condition. After this period the first clock pulse is generated.
t13
t14
t15
Setup time for start condition. (Only relevant for a repeated start condition.)
t16
Hold time DATA
for CBUS compatible masters.
for SMBus devices
t17
DATA input set-up time
t18
Rise time of both SDATA and SCLK inputs
t19
Fall time of both SDATA and SCLK inputs
t20
Set-up time for stop condition
µs
5
0
250
ns
1
300
4.0
µs
ns
µs
Switching Waveforms
Duty Cycle Timing
t1A
t1B
CPUCLK Outputs HIGH/LOW Time
t1C
VDD
OUTPUT
0V
t1D
All Outputs Rise/Fall Time
VDD
OUTPUT
0V
t2
t3
Document #: 38-07332 Rev. *A
t2
t4
Page 13 of 19
CY2277A
Switching Waveforms (continued)
CPU-CPU Clock Skew
CLK
CLK
t5
CPU-SDRAM Clock Skew
CPUCLK
SDRAM
t7
CPU-PCI Clock Skew
CPUCLK
PCICLK
t6
CPU_STOP
[13, 14]
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
CPU_STOP
CPUCLK
(External)
Notes:
13. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles.
14. CPU_STOP may be applied asynchronously. It is synchronized internally.
Document #: 38-07332 Rev. *A
Page 14 of 19
CY2277A
Switching Waveforms (continued)
PCI_STOP [15, 16]
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
PCI_STOP
PCICLK
(External)
PWR_DOWN
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN#
CPUCLK
(External)
PCICLK
(External)
VCO
Crystal
Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Timing Requirements for the SMBus
SDA
t11
t19
t18
t12
SCL
t12
t13
t16
t14
t17
t15
t20
Notes:
15. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK.
16. PCI_STOP may be applied asynchronously. It is synchronized internally.
Document #: 38-07332 Rev. *A
Page 15 of 19
CY2277A
Application Information
Clock traces must be terminated with either series or parallel termination, as is normally done.
Application Circuit
Summary
• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of
this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different
CLOAD is used. Footprints can be laid out for flexibility.
• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF.
In some cases, smaller value capacitors may be required.
• The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance
of the trace, Rout is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating
resistor.
Rseries > Rtrace – Rout
• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor
as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
• A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers
greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout
and Termination Techniques for Cypress Clock Generators” for more details.
• If a Ferrite Bead is used, a 10 µF– 22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor
prevents power supply droop during current surges.
Document #: 38-07332 Rev. *A
Page 16 of 19
CY2277A
Test Circuit
VDDQ3
48
3
0.1 µF
46
0.1 µF
7
0.1 µF
VDDQ2
43
10
40
0.1 µF
VDDCPU
37
15
0.1 µF
0.1 µF
34
17
31
21
28
24
25
0.1 µF
0.1 µF
0.1 µF
OUTPUTS
CLOAD
Note: All capacitors should be placed as close to each pin as possible.
Ordering Information
Ordering Code
Package
Name
Operating
Range
Package Type
CY2277APVC-1
O48
48-Pin SSOP
Commercial
CY2277APAC-1M
Z48
48-Pin TSSOP
Commercial
CY2277APVC-3
O48
48-Pin SSOP
Commercial
CY2277APAC-7M
Z48
48-Pin TSSOP
Commercial
CY2277APVC-12
O48
48-Pin SSOP
Commercial
CY2277APAC-12M
Z48
48-Pin TSSOP
Commercial
CY2277APVI-12
O48
48-Pin SSOP
Industrial
Intel and Pentium are registered trademarks of Intel Corporation. All product or company names mentioned in this document are
the trademarks of their respective holders.
Document #: 38-07332 Rev. *A
Page 17 of 19
CY2277A
Package Diagrams
48-Lead Shrunk Small Outline Package O48
51-85061-C
48-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z48
51-85059-B
Document #: 38-07332 Rev. *A
Page 18 of 19
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2277A
Document Title: CY2277A Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/Mobile PCs with Intel® 82430TX
and 2 DIMMs or 3 SO-DIMMs
Document Number: 38-07332
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
111731
12/15/01
DSG
*A
121855
12/14/02
RBI
Document #: 38-07332 Rev. *A
Description of Change
Change from Spec number: 38-00612 to 38-07332
Power up requirements added to Operating Conditions Information
Page 19 of 19
Similar pages