MCNIX MX27C8111PC-12 8m-bit [1m x8/512k x16] cmos otp rom with page mode Datasheet

PRELIMINARY
MX27C8111
8M-BIT [1M x8/512K x16] CMOS OTP ROM
WITH PAGE MODE
FEATURES
•
•
•
•
•
•
•
•
•
•
With Page Mode function, 8-word/16-byte page
1M x 8 or 512K x 16 organization
+12.5V programming voltage
Fast access time:90/100/120/150 ns
Page mode access time 50/60/75 ns
Totally static operation
Completely TTL compatible
Operating current: 60mA
Standby current: 100uA
Package type:
- 42 pin plastic DIP
- 44 pin SOP
GENERAL DESCRIPTION
The MX27C8111 is a 8M-bit, One Time Programmable
Read Only Memory with page mode. It is organized as
1M x 8 or 512K x 16, operates from a single + 5 volt
supply, has a static standby mode, and features fast
single address location programming. All programming
signals are TTL levels, requiring a single pulse. For
programming outside from the system, existing
EPROM programmers may be used. The MX27C8111
supports a intelligent fast programming algorithm which
can result in programming time of less than two minutes.
MX27C8111 provides Page Read Access Mode which
can greatly reduce the read access time. Normal read
access time and Page Mode read access time is as fast
as 90/50ns. It is designed to be compatible with all
microprocessors and similar applications in which high
perofmrance, large bit storage and simple interfacing
are important design considerations.
This One Time Programmable Read Only Memory is
packaged in industry standard 42 pin dual-in-line plastic
package and 44 pin SOP packages.
PIN CONFIGURATIONS
P/N: PM0329
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
MX27C8111
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
MX27C8111
SOP
PDIP
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
REV. 2.6, AUG. 22, 2001
MX27C8111
PIN DESCRIPTION
SYMBOL
BLOCK DIAGRAM
PIN NAME
CE
A0~A18
Address Input
Q0~Q14
Data Input/Output
CE
Chip Enable Input
OE
Output Enable Input
BYTE/VPP
Word/Byte Selection
OE
BYTE/VPP
.
Q15(Word mode)/
A0~A18
.
ADDRESS
INPUTS
.
.
LSB addr. (Byte mode)
VCC
Power Supply Pin (+5V)
GND
Ground Pin
OUTPUT
Q0~Q14
LOGIC
BUFFERS
Q15/A-1
Y-DECODER
.
.
/Program Supply Voltage
Q15/A-1
CONTROL
.
.
Y-SELECT
.
.
X-DECODER
.
.
.
.
.
.
8M BIT
CELL
MAXTRIX
VCC
GND
TRUTH TABLE OF BYTE FUNCTION
BYTE MODE(BYTE = GND)
CE
OE
Q15/A-1
MODE
Q0-Q7
SUPPLY CURRENT
H
X
X
Non selected
High Z
Standby(ICC2)
L
H
X
Non selected
High Z
Operating(ICC1)
L
L
A-1 input
Selected
DOUT
Operating(ICC1)
WORD MODE(BYTE = VCC)
CE
OE
Q15/A-1
MODE
Q0-Q14
SUPPLY CURRENT
H
X
High Z
Non selected
High Z
Standby(ICC2)
L
H
High Z
Non selected
High Z
Operating(ICC1)
L
L
DOUT
Selected
DOUT
Operating(ICC1)
NOTE : X = H or L
P/N: PM0329
REV. 2.6, AUG. 22, 2001
2
MX27C8111
FUNCTIONAL DESCRIPTION
at VIH, VPP at its programming voltage.
THE PROGRAMMING OF THE MX27C8111
AUTO IDENTIFY MODE
When the MX27C8111 is delivered, the chip has all
8M bits in the "ONE" or HIGH state. "ZEROs" are loaded
into the MX27C8111 through the procedure of
programming.
The auto identify mode allows the reading out of a binary
code from an One Time Programmable Read Only
Memory that will identify its manufacturer and device
type. This mode is intended for use by programming
equipment for the purpose of automatically matching the
device to be programmed with its corresponding
programming algorithm. This mode is functional in the
25°C± 5°C ambient temperature range that is required
when programming the MX27C8111.
For programming, the data to be programmed is applied
with 16 bits in parallel to the data pins.
Vcc must be applied simultaneously or before Vpp, and
removed simultaneously or after Vpp. When
programming an MXIC One Time Programmable Read
Only Memory, a 0.1uF capacitor is required across Vpp
and ground to suppress spurious voltage transients
which may damage the device.
To activate this mode, the programming equipment
must force 12.0 ± 0.5 V on address line A9 of the device.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
auto identify mode.
FAST PROGRAMMING
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For the
MX27C8111, these two identifier bytes are given in the
Mode Select Table. All identifiers for manufacturer and
device codes will possess odd parity, with the MSB
(Q15) defined as the parity bit.
The device is set up in the fast programming mode when
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and OE = VIH (Algorithm is shown in
Figure 1). The programming is achieved by applying a
single TTL low level 50us pulse to the CE input after
addresses and data line are stable. If the data is not
verified, an additional pulse is applied for a maximum of
25 pulses. This process is repeated while sequencing
through each address of the device. When the
programming mode is completed, the data in all address
is verified at VCC = VPP = 5V ± 10%.
READ MODE
The MX27C8111 provides page mode with 8 words/16
bytes per page. In order to get the benefit of fast page
read, the user should keep chip enable(CE) low and
toggle address A0~A2 in word mode or A-1~A2 in byte
mode. Page Read access time(tPA) is equal to the delay
from address stable to data output. It is twice as fast as
normal tACC and is highly recommended.
PROGRAM INHIBIT MODE
Programming of multiple MX27C8111's in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C8111 may be common. A
TTL low-level program pulse applied to an MX27C8111
CE input with VPP = 12.5 ± 0.5 V will program the
MX27C8111. A high-level CE input inhibits the other
MX27C8111s from being programmed.
WORD-WIDE MODE
With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present
data Q0-7 and outputs Q8-15 present data Q8-15, after
CE and OE are appropriately enabled.
PROGRAM VERIFY MODE
BYTE-WIDE MODE
Verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verification should be performed with OE at VIL, CE
With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tristated. If Q15/A-1 = VIH, outputs Q0-7 present data bits
P/N: PM0329
REV. 2.6, AUG. 22, 2001
3
MX27C8111
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits
Q0-7.
STANDBY MODE
The MX27C8111 has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is
placed in CMOS standby when CE is at VCC ± 0.3 V.
The MX27C8111 also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.
SYSTEM CONSIDERATIONS
During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
Vcc and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on One Time
Programmable Read Only Memory arrays, a 4.7 uF bulk
electrolytic capacitor should be used between VCC and
GND for each eight devices. The location of the
capacitor should be close to where the power supply is
connected to the array.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a twoline control function is provided to allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not
occur.
It is recommended that CE be decoded and used as the
MODE SELECT TABLE
BYTE/
MODE
CE
OE
A9
A0
Q15/A-1
VPP(5)
Q8-14
Q0-7
Read (Word)
VIL
VIL
X
X
Q15 Out
VCC
Q8-14 Out
Q0-7 Out
Read (Upper Byte)
VIL
VIL
X
X
VIH
GND
High Z
Q8-15 Out
Read (Lower Byte)
VIL
VIL
X
X
VIL
GND
High Z
Q0-7 Out
Output Disable
VIL
VIH
X
X
High Z
X
High Z
High Z
Standby
VIH
X
X
X
High Z
X
High Z
High Z
Program
VIL
VIH
X
X
Q15 In
VPP
Q8-14 In
Q0-7 In
Program Verify
VIH
VIL
X
X
Q15 Out
VPP
Q8-14 Out
Q0-7 Out
Program Inhibit
VIH
VIH
X
X
High Z
VPP
High Z
High Z
Manufacturer Code(3)
VIL
VIL
VH
VIL
0B
VCC
00H
C2H
Device Code(3)
VIL
VIL
VH
VIH
1B
VCC
38H
16H
4. See DC Programming Characteristics for VPP voltages.
5. BYTE/VPP is intended for operation under DC Voltage conditions
only.
6. Manufacture code = 00C2H
Device code = B816H
NOTES: 1. VH = 12.0V ± 0.5V
2. X = Either VIH or VIL.
3. A1-A8, A10-A18 = VIL(for auto select)
P/N: PM0329
REV. 2.6, AUG. 22, 2001
4
MX27C8111
FIGURE 1. FAST PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 6.25V
VPP = 12.75V
X=0
PROGRAM ONE 50us PULSE
INCREMENT X
INTERACTIVE
SECTION
YES
X = 25?
NO
FAIL
VERIFY WORD
?
PASS
NO
LAST ADDRESS
INCREMENT ADDRESS
FAIL
YES
VCC = VPP = 5.25V
VERIFY SECTION
VERIFY ALL WORDS
?
FAIL
DEVICE FAILED
PASS
DEVICE PASSED
P/N: PM0329
REV. 2.6, AUG. 22, 2001
5
MX27C8111
SWITCHING TEST CIRCUITS
DEVICE
UNDER
TEST
1.8K ohm
+5V
DIODES = IN3064
OR EQUIVALENT
CL
6.2K ohm
CL = 100 pF including jig capacitance
SWITCHING TEST WAVEFORMS
2.0V
2.0V
TEST POINTS
AC driving levels
0.8V
0.8V
OUTPUT
INPUT
AC TESTING: AC driving levels are 2.4V/0.4V.
Input pulse rise and fall times are < 10ns.
P/N: PM0329
REV. 2.6, AUG. 22, 2001
6
MX27C8111
ABSOLUTE MAXIMUM RATINGS
NOTICE:
Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended period may affect reliability.
RATING
VALUE
Ambient Operating Temperature
0oC to 70oC
Storage Temperature
-65oC to 125oC
Applied Input Voltage
-0.5V to 7.0V
Applied Output Voltage
-0.5V to VCC + 0.5V
VCC to Ground Potential
-0.5V to 7.0V
A9 & VPP
-0.5V to 13.5V
NOTICE:
Specifications contained within the following tables are subject to
change.
DC/AC Operating Conditions for Read Operation
MX27C8111
Operating Temperature
Commercial
Vcc Power Supply
-90
-10
-12
-15
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
5V ± 5%
5V ± 10%
5V ± 10%
5V ± 10%
DC CHARACTERISTICS
SYMBOL
PARAMETER
VOH
Output High Voltage
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
MIN.
MAX.
UNIT
CONDITIONS
V
IOH = -0.4mA
0.4
V
IOL = 2.1mA
2.0
VCC + 0.5
V
Input Low Voltage
-0.3
0.8
V
ILI
Input Leakage Current
-10
10
uA
VIN = 0 to 5.5V
ILO
Output Leakage Current
-10
10
uA
VOUT = 0 to 5.5V
ICC3
VCC Power-Down Current
100
uA
CE = VCC ± 0.3V
ICC2
VCC Standby Current
1.5
mA
CE = VIH
ICC1
VCC Active Current
60
mA
CE = VIL, f=5MHz, Iout = 0mA
IPP
VPP Supply Current Read
10
uA
CE = OE = VIL, VPP = 5.5V
2.4
CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)
SYMBOL
PARAMETER
TYP.
MAX.
UNIT
CONDITIONS
CIN
Input Capacitance
8
12
pF
VIN = 0V
COUT
Output Capacitance
8
12
pF
VOUT = 0V
CVPP
VPP Capacitance
18
25
pF
VPP = 0V
P/N: PM0329
REV. 2.6, AUG. 22, 2001
7
MX27C8111
AC CHARACTERISTICS
27C8111-90
SYMBOL PARAMETER
MIN.
MAX.
27C8111-10
MIN.
27C8111-12
MAX.
MIN.
MAX.
27C8111-15
MIN.
MAX.
UNIT CONDITIONS
tACC
Address to Output Delay
90
100
120
150
ns
CE = OE = VIL
tCE
Chip Enable to Output Delay
90
100
120
150
ns
OE = VIL
tPA
Page Address to Output Delay
50
50
60
75
ns
CE = OE =VIL
tOE
Output Enable to Output Delay
45
45
50
65
ns
CE = VIL
tDF
OE High to Output Float,
30
0
0
30
0
35
0
50
ns
or CE High to Output Float
tOH
Output Hold from Address,
0
0
0
0
ns
90
100
120
150
ns
CE or OE which ever occurred first
tBHA
BYTE Access Time
tOHB
BYTE Output Hold Time
tBHZ
BYTE Output Delay Time
tBLZ
BYTE Output Set Time
0
0
0
70
10
0
70
10
ns
70
70
10
ns
10
ns
DC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5oC
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VOH
Output High Voltage
2.4
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
CONDITIONS
V
IOH = -0.40mA
0.4
V
IOL = 2.1mA
2.0
VCC + 0.5
V
Input Low Voltage
-0.3
0.8
V
ILI
Input Leakage Current
-10
10
uA
VH
A9 Auto Select Voltage
11.5
12.5
V
ICC3
VCC Supply Current (Program & Verify)
50
mA
IPP2
VPP Supply Current(Program)
30
mA
VCC1
Fast Programming Supply Voltage
6.00
6.50
V
VPP1
Fast Programming Voltage
12.5
13.0
V
VIN = 0 to 5.5V
CE = VIL, OE = VIH
AC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5oC
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
tAS
Address Setup Time
2.0
tOES
OE Setup Time
2.0
us
tDS
Data Setup Time
2.0
us
tAH
Address Hold Time
0
us
tDH
Data Hold Time
2.0
us
us
tDFP
Chip Enable to Output Float Delay
0
tVCS
VCC Setup Time
2.0
130
us
tVPS
BYTE/VPP Setup Time
2.0
us
tPW
CE initial Program Pulse Width
tOE
Data valid from OE
50
us
150
P/N: PM0329
ns
ns
REV. 2.6, AUG. 22, 2001
8
MX27C8111
WAVEFORMS
NORMAL READ CYCLE(WORD MODE)
ADDRESS
INPUTS
DATA ADDRESS
tACC
CE
tCE
OE
tDF
DATA
OUT
VALID DATA
tOE
tOH
PAGE MODE READ CYCLE
A4-A18
VALID ADDRESS
A0~A2 (Word mode)
A-1~A2 (Byte mode)
tACC
CE
tPA
tPA
tPA
OE
tOH
tDF
tOE
DATA OUT
P/N: PM0329
REV. 2.6, AUG. 22, 2001
9
MX27C8111
WAVEFORMS
NORMAL READ CYCLE(BYTE MODE)
HIGH-Z
A-1
HIGH-Z
tACC
tOH
BYTE/VPP
Q0-Q7
VALID DATA
VALID DATA
tBHA
tOHB
VALID DATA
Q15-Q8
tBHZ
tBLZ
FAST PROGRAMMING ALGORITHM WAVEFORM
VERIFY
PROGRAM
VIH
Addresses
VALID ADDRESS
VIL
tAH
tAS
DATA OUT VALID
DATA SET
DATA
tDS
tDFP
tDH
VPP1
BYTE/VPP
VCC
tVPS
VCC1
VCC
VCC
tVCS
VIH
CE
VIL
tPW
tOES
tOE
VIH
OE
VIL
P/N: PM0329
REV. 2.6, AUG. 22, 2001
10
MX27C8111
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
ACCESS TIME
OPERATING CURRENT
STANDBY CURRENT
(ns)
MAX.(mA)
MAX.(uA)
MX27C8111MC-90
90
60
100
44 PIn SOP (ROM pin out)
MX27C8111MC-10
100
60
100
44 PIn SOP (ROM pin out)
MX27C8111MC-12
120
60
100
44 Pin SOP(ROM pin out)
MX27C8111MC-15
150
60
100
44 Pin SOP(ROM pin out)
MX27C8111PC-90
90
60
100
42 PIn PDIP (ROM pin out)
MX27C8111PC-10
100
60
100
42 PIn PDIP(ROM pin out)
MX27C8111PC-12
120
60
100
42 Pin PDIP(ROM pin out)
MX27C8111PC-15
150
60
100
42 Pin PDIP(ROM pin out)
P/N: PM0329
PACKAGE
REV. 2.6, AUG. 22, 2001
11
MX27C8111
PACKAGE INFORMATION
42-PIN PLASTIC DIP(600 mil)
P/N: PM0329
REV. 2.6, AUG. 22, 2001
12
MX27C8111
44-PIN PLASTIC SOP
P/N: PM0329
REV. 2.6, AUG. 22, 2001
13
MX27C8111
Revision History
Revision No. Description
2.0
1) Eliminate Interactive Programming Mode.
2) Programming pulse change, from 100us to 50us
2.1
IPP : 100uA---->10uA
2.2
Add 100ns speed grade.
2.3
Add 90ns speed grade.
2.4
90ns speed grade VCC=5V±10%-->5V±5%
2.5
Correct 42PIN plastic DIP package information error
2.6
To modify Package Information
P/N: PM0329
Page
P12
P12,13
Date
5/30/1997
8/8/1997
1/31/1998
4/07/1998
5/06/1998
MAR/02/2000
AUG/22/2001
REV. 2.6, AUG. 22, 2001
14
MX27C8111
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
15
Similar pages