Fujitsu MB86612PBT Ieee 1394 bus controller (for mpeg, dvc) Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-22001-1E
ASSP Communication Control
IEEE 1394 Bus Controller
(for MPEG, DVC)
MB86612
■ DESCRIPTION
The MB86612 is 1394 serial bus controller exclusively for MPEG and DVC data transfer, compatible with the
IEEE 1394 “FireWire” standard (IEEE Standard 1394-1995). Two built-in ports plus a differential transceiver and
comparator are provided to enable formation of networks in a 1394 cable environment. The MB86612 supports
s100 data transfer speeds.
By integrating the physical layer and link layer on one chip, The MB86612 is designed to reduce mounting area
as well as power consumption.
The MB86612 has an exclusive data port for isochronous transfer, provides automatic packetizing and separation
of header and data units, and is optimized for continuity of transfer processing.
The MB86612 supports MPEG and DVC AV/C protocols, and includes the necessary built-in automatic
operations and CSR’s for providing the necessary operations for MPEG and DVC data transfer.
■ FEATURES
•
•
•
•
•
•
•
Compatible with IEEE 1394 high-performance serial bus standards
Physical layer and link layer integrated on one chip
2 cable ports
Supports s100 transfer speed (98.304 Mbit/sec)
3.3V single power supply operation
Built-in PLL (for crystal oscillator) for internal clock signal generation
Power saving modes
1) Forced sleep mode at instruction from MPU
2) Automatic sleep mode for non-connected ports
• Header and data units automatically separated at receiving and automatic packetizing for sending
• Supports cycle master functions
(Continued)
■ PACKAGES
100-pin plastic LQFP
120-pin plastic FBGA
(FPT-100P-M05)
(BGA-120P-M01)
MB86612
(Continued)
• Built-in CSR's to provide isochronous resource manager functions
• 32-bit CRC generation and check functions
• General purpose port for asynchronous transfer and control (16-bit MPU bus)
• Exclusive built-in ports for isochronous transfer (8-bit bus)
• Built-in CRS's and automatic processes to support AV/C protocol (MPEG, DVC)
1) Automatic separation of CIP headers at receiving, and automatic packetizing at sending.
2) Automatic generation of source packet headers (time stamp).
3) Source packet header (time stamp) match detection
4) DBC area automatic increment function
5) Empty packet sending and receiving
6) On-chip PCR (input/output 1 channel each)
7) Each CSR with automatic C&S lock processing and read processing
8) Automatic processing of late packet generation
• Compatible with 4-core or 6-core cables
• Packages: LQFP-100, FBGA-120
2
MB86612
■ PIN ASSIGNMENTS
MODE0
LINKON
TS
IERR
IV
ILWRE
IDIR
ICLK
VDD
VSS
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
BUSRST
PWR3
VSS
VDD
PWR2
PWR1
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
100 MODE1
1. LQFP-100
3
73 TPA0
VSS
4
72 TPB0
ALE
5
71 TPA0
D15
6
70 TPB0
D14
7
69 AVDD
D13
8
68 AVSS
D12
9
67 TPBIAS0
D11
10
66 AVDD
D10
11
65 AVSS
D9
12
64 RO0
D8
13
63 AVSS
VDD
14
62 AVDD
VSS
15
61 TPA1
D7
16
60 TPB1
D6
17
59 TPA1
AD5
18
58 TPB1
AD4
19
57 AVSS
AD3
20
56 AVDD
AD2
21
55 TPBIAS1
AD1
22
54 AVSS
D0
23
53 AVDD
VDD
24
52 RO1
VSS
25
51 N.C.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
PMODE
CTR
OCLK
VDD
VSS
X0
X1
TESTP
AVSS
AVDD
VCOIN
CHPO
ROP
AVSS
AVDD
74 AVSS
27
28
29
30
31
32
33
34
35
2
WR (DS) 26
75 AVDD
INT
RD (R/W)
VDD
VSS
CS
A5
A4
A3
A2
A1
RESET 1
3
MB86612
2. FBGA-120
13
12
11
10
9
8
7
6
5
4
3
2
1
N.C.
AVDD
AVSS
VCOIN
TESTP
XO
OCLK
PMODE
A3
A5
VDD
N.C.
WR
(DS)
N
N.C.
RO1
N.C.
CHPO
AVSS
X1
VDD
CTR
A2
A4
VSS
RD
(R/W)
VSS
M
AVDD
AVSS
TPBIAS1
ROP
AVDD
N.C.
VSS
N.C.
A1
N.C.
CS
N.C.
VDD
L
AVSS
AVSS
TPB1
D0
AD1
AD2
K
TPA1
TPB1
N.C.
AD3
AD4
AD5
J
TPA1
AVDD
AVSS
D6
N.C.
D7
I
N.C.
RO0
AVSS
VSS
VDD
D8
H
AVDD
TPBIAS0
N.C.
N.C.
D9
D10
G
AVSS
AVDD
TPB0
D11
D12
N.C.
E
TPA0
TPB0
N.C.
D13
D14
D15
D
TPA0
AVSS
PWR3
ID7
ID4
ID1
VSS
IDIR
IV
LINKON
ALE
VSS
VDD
C
AVDD
PWR2
VSS
N.C.
ID5
ID2
ID0
ICLK
N.C.
TS
N.C.
INT
N.C.
B
PWR1
N.C.
VDD
BUSRST
ID6
ID3
N.C.
VDD
ILWRE
IERR
TOP VIEW
MODE0 MODE1 RESET A
1 pin
4
MB86612
■ PIN LIST
1. LQFP-100
NO.
I/O
Pin Name
NO.
I/O
Pin Name
1
ID
RESET
34
36
ID
IU
PMODE
A2
2
O
INT
35
37
ID
O
CTR
A1
3
—
VDD
36
38
IU
O
PMODE
OCLK
4
—
VSS
37
39
—
O
CTR
VDD
5
ID
ALE
38
40
—
O
OCLK
VSS
6
ID/O
D15
39
41
I/O
—
V
X0
DD
7
ID/O
D14
40
42
—
I
V
X1
SS
8
ID/O
D13
41
43
I/O
—
TESTP
X0
9
ID/O
D12
42
44
—
I
AV
X1SS
10
ID/O
D11
43
45
—
TESTP
AVDD
11
ID/O
D10
44
46
—
I
VCOIN
AVSS
12
ID/O
D9
45
47
—
O
CHPO
AVDD
13
ID/O
D8
46
48
O
I
VCOIN
ROP
14
—
VDD
47
49
—
O
CHPO
AVSS
15
—
VSS
48
50
—
O
AV
ROP
DD
16
ID/O
D7
49
51
—
AV
N.C.
SS
17
ID/O
D6
50
52
—
O
AV
RO1
DD
18
ID/O
AD5
51
53
—
AV
N.C.
DD
19
ID/O
AD4
52
54
—
O
AV
RO1
SS
20
ID/O
AD3
53
55
—
O
TPBIAS1
AVDD
21
ID/O
AD2
54
56
—
AVDD
SS
22
ID/O
AD1
55
57
—
O
TAPBIAS1
AVSS
23
ID/O
D0
56
58
I/O
—
TPB1
AVDD
24
—
VDD
57
59
I/O
—
TPA1
AVSS
25
—
VSS
58
60
I/O
TPB1
26
ID
WR
WR(XDS)
(DS)
59
61
I/O
TPA1
27
ID
RD (R/W)
60
62
I/O
—
TPB1
AVDD
28
—
VDD
61
63
I/O
—
TPA1
AVSS
29
—
VSS
62
64
—
O
RO0
30
ID
CS
63
65
—
AVDD
SS
31
ID
A5
64
66
—
O
AVDD
SS
32
ID
A4
65
67
—
O
TPBIAS0
RO0
33
ID
A3
66
68
—
AVDD
SS
34
—
ID
V
A2
DD
57
69
—
AVDD
35
—
ID
V
A1
SS
58
70
I/O
TPB1
TPB0
(Continued)
5
MB86612
(Continued)
6
NO.
I/O
Pin Name
NO.
I/O
Pin Name
71
I/O
TPA0
86
ID/O
ID3
72
I/O
TPB0
87
ID/O
ID2
73
I/O
TPA0
88
ID/O
ID1
74
—
AVSS
89
ID/O
ID0
75
—
AVDD
90
—
VSS
76
I
PWR1
91
—
VDD
77
I
PWR2
92
ID
ICLK
78
—
VDD
93
ID
IDIR
79
—
VSS
94
O
ILWRE
80
I
PWR3
95
ID
IV
81
I
BUSRST
96
O
IERR
82
ID/O
ID7
97
ID/O
TS
83
ID/O
ID6
98
O
LINKON
84
ID/O
ID5
99
ID
MODE0
85
ID/O
ID4
100
ID
MODE1
MB86612
2. FBGA-120
Pin
No.
Ball
No.
I/O
Pin Name
Pin
No.
Ball
No.
I/O
Pin Name
Pin
No.
Ball
No.
I/O
Pin Name
1
A1
ID
RESET
37
N4
ID
A5
73
H13
I/O
TPA1
2
B1
—
N.C.
38
M4
ID
A4
74
H12
—
AVDD
3
B2
O
INT
39
L4
—
N.C.
75
H11
—
AVSS
4
C1
—
VDD
40
N5
ID
A3
76
G13
—
N.C.
5
C2
—
VSS
41
M5
ID
A2
77
G12
—
RO0
6
C3
ID
ALE
42
L5
ID
A1
78
G11
—
AVSS
7
D1
ID/O
D15
43
N6
IU
PMODE
79
F13
—
AVDD
8
D2
ID/O
D14
44
M6
O
CTR
80
F12
—
TPBIAS0
9
D3
ID/O
D13
45
L6
—
N.C.
81
F11
—
N.C.
10
E1
—
N.C.
46
N7
O
OCLK
82
E13
—
AVSS
11
E2
ID/O
D12
47
M7
—
VDD
83
E12
—
AVDD
12
E3
ID/O
D11
48
L7
—
VSS
84
E11
I/O
TPB0
13
F1
ID/O
D10
49
N8
I/O
X0
85
D13
I/O
TPA0
14
F2
ID/O
D9
50
M8
I
X1
86
D12
I/O
TPB0
15
F3
—
N.C.
51
L8
—
N.C.
87
D11
—
N.C.
16
G1
ID/O
D8
52
N9
O
TESTP
88
C13
I/O
TPA0
17
G2
—
VDD
53
M9
—
AVSS
89
C12
—
AVSS
18
G3
—
VSS
54
L9
—
AVDD
90
B13
—
AVDD
19
H1
ID/O
D7
55
N10
I
VCOIN
91
A13
I
PWR1
20
H2
—
N.C.
56
M10
O
CHPO
92
A12
—
N.C.
21
H3
ID/O
D6
57
L10
O
ROP
93
B12
I
PWR2
22
J1
ID/O
AD5
58
N11
—
AVSS
94
A11
—
VDD
23
J2
ID/O
AD4
59
M11
—
N.C.
95
B11
—
VSS
24
J3
ID/O
AD3
60
N12
—
AVDD
96
C11
I
PWR3
25
K1
ID/O
AD2
61
N13
—
N.C.
97
A10
I
BUSRST
26
K2
ID/O
AD1
62
M13
—
N.C.
98
B10
—
N.C.
27
K3
ID/O
D0
63
M12
O
RO1
99
C10
ID/O
ID7
28
L1
—
VDD
64
L13
—
AVDD
100
A9
ID/O
ID6
29
L2
—
N.C.
65
L12
—
AVSS
101
B9
ID/O
ID5
30
M1
—
VSS
66
L11
O
TPBIAS1
102
C9
ID/O
ID4
31
N1
ID
WR (DS)
67
K13
—
AVDD
103
A8
ID/O
ID3
32
N2
—
N.C.
68
K12
—
AVSS
104
B8
ID/O
ID2
33
M2
ID
RD (R/W)
69
K11
I/O
TPB1
105
C8
ID/O
ID1
34
N3
—
VDD
70
J13
I/O
TPA1
106
A7
—
N.C.
35
M3
—
VSS
71
J12
I/O
TPB1
107
B7
ID/O
ID0
36
L3
ID
CS
72
J11
—
N.C.
108
C7
—
VSS
(Continued)
7
MB86612
(Continued)
8
Pin
No.
Ball
No.
I/O
Pin Name
Pin
No.
Ball
No.
I/O
Pin Name
Pin
No.
Ball
No.
I/O
Pin Name
109
A6
—
VDD
113
B5
—
N.C.
117
C4
O
LINKON
110
B6
ID
ICLK
114
C5
ID
IV
118
A3
ID
MODE0
111
C6
ID
IDIR
115
A4
O
IERR
119
B3
—
N.C.
112
A5
O
ILWRE
116
B4
ID/O
TS
120
A2
ID
MODE1
MB86612
■ PIN DESCRIPTION
1. 1394 Interface
Pin name
I/O
Function
TPA0
I/O
Cable port 0 TPA positive signal I/O pin
TPA0
I/O
Cable port 0 TPA negative signal I/O pin
TPB0
I/O
Cable port 0 TPB positive signal I/O pin
TPB0
I/O
Cable port 0 TPB negative signal I/O pin
TPA1
I/O
Cable port 1 TPA positive signal I/O pin
TPA1
I/O
Cable port 1 TPA negative signal I/O pin
TPB1
I/O
Cable port 1 TPB positive signal I/O pin
TPB1
I/O
Cable port 1 TPB negative signal I/O pin
TPBIAS0
O
Cable port 0 common voltage reference voltage output pin
TPBIAS1
O
Cable port 1 common voltage reference voltage output pin
RO0
O
Connect to GND through 4.7 kΩ resistance
RO1
O
Connect to GND through 4.7 kΩ resistance
2. Isochronous-data Interface
Pin name
I/O
Function
Isochronous data interface CLK signal input pin (DC to 16 MHz).
ICLK
IDIR
I
I
Note: When this clock is stopped, transfer is stopped. Also the “Data FIFO init
(63h)” instruction (operand: 21) is invalid.
Isochronous transfer sending/receiving switching signal input pin.
0 input: Clear ISO FIFO, go to sending mode.
Sending starts after receiving 1 packet of data.
1 input: Clear ISO FIFO, go to receiving mode. If a ‘1’ signal is entered during
packet sending, receiving mode begins after sending of the current packet.
The ILWRE signal is asserted after receiving 1 packet.
Note: This signal should normally be left at ‘1’, and switched to ‘0’ only when
sending.
ILWRE
O
Isochronous FIFE access enable signal output pin.
Sending: Asserted when 1 or more empty source packets are present in ISO
FIFO.
When negated, the data output up to the leading edge for the next ICLX.
Receiving: Asserted when receiving of 1 source packet of data is completed.
Negate conditions for this signal are determined by the ilwre-mode bit (bit 11) in
the mode-control register.
ID7 to ID0
I/O
Isochronous transfer data input/output bits. (MSB is ID7, LSB is ID0)
IV
I
ID7 to ID0 enable signal input pin.
Sending: While this signal is active, data from the ID7 to ID0 pins is loaded into
ISO FIFO memory at the rising edge of the ICLK signal.
Receiving: While this signal is active, data from ISO FIFO memory is sent to the
ID7 to ID0 pins. Data is switched at the falling edge of the ICLK signal.
(Continued)
9
MB86612
(Continued)
Pin name
I/O
Function
I/O
Sending: DVC mode time stamp trigger signal input pin.
(Input) The cycle timer value when this signal is asserted is added to the sending
offset value and becomes the sending time stamp.
Receiving: Time stamp match detect signal.
(output) In MPEG mode, this signal is negative after reading 1 source packet of
data.
In DVC mode, this signal is asserted for the duration of 32 ticlk (32 periods of the
ICLK signal).
If an error is detected in a receiving isochronous packet this signal is not output.
IERR
O
This signal is output when an error is detected in a receiving isochronous packet.
When an error is detected the TS signal is not output, so that this signal should
be used to trigger reading of the receiving packet.
If an error such as causing discarding of received packets within a device, this
signal is not output.
CTR
O
This signal is output when the cycle timer value is changed.
This signal may be output or not output, according to the CTR bit (bit 0) in the
mode-control register.
OCLK
O
Cycle timer clock output (24.576 MHz).
This signal may be output or not output, according to the CTR bit (bit 0) in the
mode-control register.
TS
3. System Interface
10
Pin name
I/O
Function
CS
I
Input pin for signals used by the MPU to select the MB86612 as an I/O device.
A5 to A1
I
Address input pins for internal register selection.
Valid only in non-multiplexed mode.
If multiplexed mode is selected these pins should be fixed at ‘0’.
D15 to D6, D0
I/O
16-bit data bus input/output pins (MSB is D15, LSB is D0).
AD5 to AD1
I/O
16-bit data bus input/output pins (MSB is AD5, LSB is AD1). Used for address
input signals when multiplexed mode is selected.
RD (R/W)
I
80-series mode: Read strobe signal input pin, used to output data from the
MB86612 to the data bus.
68-series mode: Control signal input pin, used for data input/output operations to
the MB86612.
WR (DS)
I
80-series mode: Write strobe signal input pin, used to input data from the data
bus to the MB86612.
68-series mode: DS signal input pin, output when data bus is enabled.
ALE
I
ALE signal input pin, for signal output when addresses are enabled in multiplexed
mode. In non-multiplexed mode, this signal should be fixed at ‘0’.
INT
O
Interrupt output pin.
MB86612
4. Other
Pin name
I/O
X0
I/O
X1
I
VCOIN
I
VCO input pin for internal PLL.
CHPO
O
Charge pump output pin for internal PLL.
ROP
O
Connect to GND through 4.7 kΩ resistance.
RESET
I
Reset signal input pin.
This signal should be set to ‘0’ when the system power supply is off.
MODE0
I
Input ‘0’ for 80-series mode.
Input ‘1’ for 68-series mode.
MODE1
I
Input ‘0’ for non-multiplexed mode.
Input ‘1’ for multiplexed mode.
PMODE
I
For cable power supply, set to ‘0’ for power startup.
Set to ‘1’ when cable power supply is off or until system power is on.
I
When operating from cable power supply, these pins determine the value of the
‘POWER_CLASS’ area of Self-ID packets.
When operating from system power supply, these pins correspond to the power
bit in the Self-ID-PKT-param setting register.
BUSRST
I
When the MB86612 is started from the power supply this bit determines whether
a bus reset is applied automatically.
Input ‘0’ for no bus reset.
Input ‘1’ for bus reset.
When this bit is set to ‘1’, a bus reset is executed 200 µs after the int-reset bit (bit
9) in the flag & status register (address 02h) is set to ‘1’.
LINKON
O
Link-on packet receiving detection pin. Outputs an ‘H’ signal for 1 to 2 tclk (1 to 2
cycles of the crystal oscillator input signal) when a link-0n packet is received.
When this signal is not used, leave it open.
AVDD
—
Analog power supply
AVSS
—
Analog ground
VDD
—
Digital power supply
VSS
—
Digital ground
TESTP
—
Test pin. Do not connect.
PWR1 to PWR3
Function
External crystal connection pins for oscillator circuits.
11
MB86612
■ BLOCK DIAGRAM
IDIR
ISO
sending
packet
control
IV
TS
IERR
Isochronous interface
ID7 to ID0
CTR
ISO sending/receiving FIFO (4kB)
ILWRE
TPA0
1394 interface (Port 0)
ICLK
LINK
layer
control
circuit
ASYNC
sending
packet
processing
ASYNC
receive-only
FIFO
(128 byte)
ASYNC
receiving
packet
processing
A5 to A1
AD5 to AD1
RD (R/W)
WR (DS)
ALE
System & asynchronous interface
D15 to D6, D0
Cycle mask
Transaction circuit block
PLL circuit
INT
Register block
12
TPB0
TPBIAS0
TPA1
1394 interface (Port 1)
CS
ASYNC
send-only
FIFO
(128 byte)
TPB0
PHY
layer
control
circuit
ISO
receiving
packet
control
OCLK
TPA0
CSR
TPA1
TPB1
TPB1
TPBIAS1
MB86612
■ BLOCK DESCRIPTIONS
• PHY Layer Control Circuit
This block contains the IEEE 1394 physical layer control circuits.
Both asynchronous transfer and isochronous transfer in a cable environment are supported.
The transfer speed is 98.304 Mbit/sec.
Two analog transceiver/receiver ports are built-in.
This block provides bus status monitoring initialization operation after a bus reset is applied, as well as
arbitration and encoding/decoding functions for data sending and receiving.
• LINK Layer Control Circuit
This block controls the generation and transfer of IEEE 1394 standard packets.
32-bit CRC generation and checking is performed for packet headers and data.
A 32-bit cycle timer register is built-in to provide cycle master functions.
• Sending/Receiving FIFO
Contains built-in 4-byte FIFO areas, used for isochronous smoothing and rate conversion for both sending
and receiving.
Contains independent sending and receiving 128-byte FIFO areas for asynchronous transfer.
• Packet Processing
Sending: Performs packetizing of headers, data and CRC. Automatically generates and attaches CRC.
Receiving: Separates 1394 packet headers and data, strips CRC.
• Special Transaction Circuits
These circuits operate with the packet processing block in handling data from the isochronous interface,
packetizing for MPEG and DVC transfer as well as rebuilding receiving data for the isochronous interface.
• Register Block
This block contains various device control registers, as well as registers for setting parameters required for
1394 transfer, AVC protocol registers and CSR.
The built-in CSR provides isochronous resource manager functions.
• PLL Circuit
This block uses the reference clock signal generated by the crystal oscillator circuit to create internal operating
clock and transfer clock signals.
Reference oscillator frequency: 8.192 MHz.
13
MB86612
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Unit
Min.
Max.
VDD
VSS – 0.5
4.0
V
Input voltage*1
VI
VSS – 0.5
VDD + 0.5
V
Output voltage*1
VO
VSS – 0.5
VDD + 0.5
V
Tst
–55
+125
°C
Top
–40
+85
°C
IO
–14
+14
mA
—
—
VDD + 1.0
V
—
—
VSS – 1.0
V
Power supply voltage*1
Strage temperature
Operating temperature*
Output current*
Overshoot*
3
4
Undershoot*
*1:
*2:
*3:
*4:
2
4
Voltage values are based on Vss = 0 V.
Not warranted for continuous operation.
Normal output current flow (Minimum at Vo = 0 V, maximum at Vo = VDD).
50 ns or less.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Power supply voltage*
Value
Unit
Min.
Max.
VDD
3.0
3.6
V
“H” level input voltage
CMOS input
VIH
VDD × 0.65
VDD
V
“L” level input voltage
CMOS input
VIL
VSS
VDD × 0.25
V
Differential input voltage
(for data transfer)
Cable input
VID
142
260
mV
Differential input voltage
(for arbitration)
Cable input
VIDA
173
260
mV
Common mode input voltage
Cable input
VCM
1.165
2.515
V
Receiving input jitter
Cable input
—
—
1.08
ns
Receiving input skew
Cable input
—
—
0.8
ns
CMOS output
IOH/IOL
–4
4
mA
TPBIAS
Iot
–2
10
mA
Ta
0
+70
°C
Output current
Operating temperature
* : Voltage values are based on Vss = 0 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
14
MB86612
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
1.1 System Interface, etc
Parameter
(VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70°C)
Value
Unit
Min.
Typ.
Max.
Symbol
Conditions
“H” level input voltage
VIH
CMOS
VDD × 0.65
—
VDD
V
“L” level input voltage
VIL
CMOS
VSS
—
VDD × 0.25
V
“H” level output voltage
VOH
IOH = –4 mA
VDD – 0.5
—
VDD
V
“L” level output voltage
VOL
IOL = –4 mA
VSS
—
0.4
V
–5
—
5
µA
–5
—
5
µA
Input pins
Input leak current
ILI
3-state pin
input
ILZ
Input pull-up/pull down resistance
Power supply current
VI = 0V to VDD
Rp
VIH = VDD
25
50
200
kΩ
IDDS0
No port
connected*1
—
—
220
mA
IDDS1
1 port
connected*1
—
—
270
mA
IDDS2
2 ports
connected*1
—
—
300
mA
IDDSS
Forced
sleep*1
—
—
50
mA
IDDCN
Non
repeating*2
—
—
220
mA
IDDCR
Repeating*2
—
—
240
mA
*1: Operating from system power supply
*2: Operating from cable power supply
1.2 1394 Interface Driver
Parameter
Symbol
(VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70°C)
Value
Conditions
Unit
Min.
Max.
Differential output voltage
VOD
R1 = 56 Ω
172
265
mV
Common phase current
ICM
Driver enabled
–0.81
0.44
mA
VOFF
Driver disabled
—
20
mV
VO
—
1.665
2.015
V
Off state voltage
TPBIAS output voltage
15
MB86612
1.3 1394 Interface - Comparator
Parameter
IIC
Driver disabled
–20
20
µA
Arbitration comparator “H” level
threshold voltage
VSCH
Driver disabled
168
—
mV
Arbitration comparator “Z” level
threshold voltage
VSEZ
Driver disabled
–30
30
mV
Arbitration comparator “L” level
threshold voltage
VSCL
Driver disabled
—
–168
mV
Port status comparator disconnection
detect voltage
VSD
Driver disabled
0.6
—
V
Port status comparator connection
detect voltage
VSC
Driver disabled
—
1.0
V
Common phase input current
16
Symbol
(VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70°C)
Value
Conditions
Unit
Min.
Max.
MB86612
2. AC Characteristics
2.1 System Clock
Parameter
Value
Symbol
Min.
Typ.
Max.
Unit
Clock frequency
fC
—
8.192
—
MHz
Clock cycle time
tCLF
—
1/fc
—
ns
Clock pulse width
tCLCH
tCLCL
50
—
—
ns
Clock rise/fall time
tCR
tCF
—
—
5
ns
tCLCH
tCLF
tCF
tCR
0. 65 VDD
0. 25 VDD
CLK
tCLCL
2.2 System Reset
Parameter
Symbol
Reset (RESET) “L” level pulse width
tWRSL
Value
Min.
Max.
4 tclf
—
Unit
ns
tWRSL
RESET
17
MB86612
2.3 Driver
Parameter
Value
Min.
Max.
Unit
Sending jitter
tJT
—
±0.8
ns
Sending skew
tSK
—
±0.8
ns
Sending rise time*
tDR
—
3.2
ns
Sending fall time*
tDF
—
3.2
ns
* : 10 to 90% value.
18
Symbol
MB86612
2.4 System Interface
(1) 68-Series Register Write Operation (multiplexed)
Parameter
Symbol
Value
Min.
Unit
Max.
Address setup time
tAWSM
10
—
ns
Address hold time
tAWHM
5
—
ns
CS setup time
tCWSM
10
—
ns
CS hold time
tCWHM
5
—
ns
Data setup time
tDWSM
10
—
ns
Data hold time
tDWHM
0
—
ns
R/W setup time
tRWSM
5
—
ns
R/W hold time
tRWHM
5
—
ns
ALE fall to DS fall time
tDWD
10
—
ns
DS rise to ALE rise time
tLWD
5
—
ns
ALE “H” level pulse width
tALE
10
—
ns
DS “L” level pulse width
tDSM
20
—
ns
tCWSM
tCWHM
CS
tRWHM
tRWSM
R/W
tALE
tLWD
tDWD
ALE
tDSM
DS
tAWSM
D15 to D6, D0
AD5 to AD1
Address
tAWHM
tDWSM
tDWHM
Data
19
MB86612
(2) 68-System Register Read Operation (multiplexed)
Parameter
Symbol
Value
Min.
Max.
Unit
Address setup time
tARSM
10
—
ns
Address hold time
tARHM
5
—
ns
CS setup time
tCRSM
10
—
ns
CS hold time
tCRHM
5
—
ns
Data output definition time
tRLDM
—
15
ns
Data output disabled time
tRHDM
0
—
ns
R/W setup time
tRWSM
5
—
ns
R/W hold time
tRWH
5
—
ns
ALE fall to DS fall time
tDRD
10
—
ns
DS rise to ALE rise time
tLRD
5
—
ns
ALE “H” level pulse width
tALE
10
—
ns
DS “L” level pulse width
tDSM
20
—
ns
tCRSM
tCRHM
CS
tRWSM
tRWH
R/W
tALE
tLRD
tDRD
ALE
tDSM
DS
tARSM
D15 to D6, D0
AD5 to AD1
20
Address
tARHM
tRLDM
tRHDM
Defined data
MB86612
(3) 68-Series Register Write Operation (non-multiplexed)
Parameter
Value
Symbol
Min.
Max.
Unit
Address setup time
tAWS
5
—
ns
CS setup time
tCWS
5
—
ns
CS hold time
tCWH
5
—
ns
Data setup time
tDWS
10
—
ns
Data hold time
tDWH
0
—
ns
DS “L” level pulse width
tDS
20
—
ns
R/W setup time
tRWS
5
—
ns
R/W hold time
tRWH
5
—
ns
DS rise to address hold time
tAWH
5
—
ns
tCWS
tCWH
tRWS
tRWH
CS
R/W
tDS
DS
tAWS
A5 to A0
tAWH
Address
tDWS
D15 to D6, D0
AD5 to AD1
tDWH
Data
21
MB86612
(4) 68-Series Register Read Operation (non-multiplexed)
Parameter
Value
Symbol
Min.
Max.
Unit
Address setup time
tARS
5
—
ns
CS setup time
tCRS
5
—
ns
CS hold time
tCRH
5
—
ns
Data output definition time
tRLD
—
15
ns
Data output disabled time
tRHD
0
—
ns
DS “L” level pulse width
tDS
20
—
ns
R/W setup time
tRWS
5
—
ns
R/W hold time
tRWH
5
—
ns
Address hold time
tARH
5
—
ns
tCRS
tCRH
tRWS
tRWH
CS
R/W
tDS
DS
tARS
A5 to A0
tARH
Address
tRLD
D15 to D6, D0
AD5 to AD1
22
tRHD
Defined data
MB86612
(5) 80-Series Register Write Operation (multiplexed)
Parameter
Symbol
Value
Min.
Max.
Unit
Address setup time
tAWSM
10
—
ns
Address hold time
tAWHM
5
—
ns
CS setup time
tCWSM
10
—
ns
CS hold time
tCWHM
5
—
ns
Data setup time
tDWSM
10
—
ns
Data hold time
tDWHM
0
—
ns
ALE fall to WR fall time
tDWD
10
—
ns
WR rise to ALE rise time
tLWD
5
—
ns
ALE “H” level pulse width
tALE
10
—
ns
WR “L” level pulse width
tWRM
20
—
ns
tCWSM
tCWHM
CS
tALE
tDWD
tLWD
ALE
tWRM
WR
tAWSM
D15 to D6, D0
AD5 to AD1
Address
tAWHM
tDWSM
tDWHM
Data
23
MB86612
(6) 80-Series Register Read Operation (multiplexed)
Parameter
Symbol
Value
Min.
Max.
Unit
Address setup time
tARSM
10
—
ns
Address hold time
tARAHM
5
—
ns
CS setup time
tCRSM
10
—
ns
CS hold time
tCRHM
5
—
ns
Data output definition time
tRLDM
—
15
ns
Data output disabled time
tRHDM
0
—
ns
ALE fall to RD fall time
tDRD
10
—
ns
RD rise to ALE rise time
tLRD
5
—
ns
ALE “H” level pulse width
tALE
10
—
ns
RD “L” level pulse width
tRDM
20
—
ns
tCRSM
tCRHM
CS
tALE
tDRD
tLRD
ALE
tRDM
RD
tARSM
D15 to D6, D0
AD5 to AD1
24
Address
tARAHM
tRLDM
tRHDM
Defined data
MB86612
(7) 80-Series Register Write Operation (non-multiplexed)
Parameter
Value
Symbol
Min.
Max.
Unit
Address setup time
tAWS
5
—
ns
CS setup time
tCWS
5
—
ns
CS hold time
tCWH
5
—
ns
Data setup time
tDWS
10
—
ns
Data hold time
tDWH
0
—
ns
WR “L” level pulse width
tWR
20
—
ns
Address hold time
tAWH
5
—
ns
tCWS
tCWH
CS
tWR
WR
tAWS
tAWH
A5 to A0
Address
tDWS
D15 to D6, D0
AD5 to AD1
tDWH
Data
25
MB86612
(8) 80-Series Register Read Operation (non-multiplexed)
Parameter
Value
Symbol
Min.
Max.
Unit
Address setup time
tARS
5
—
ns
CS setup time
tCRS
5
—
ns
CS hold time
tCRH
5
—
ns
Data output definition time
tRLD
—
15
ns
Data output disabled time
tRHD
0
—
ns
RD “L” level pulse width
tRD
20
—
ns
Address hold time
tARH
5
—
ns
tCRS
tCRH
CS
tRD
RD
tARS
tARH
A5 to 0
Address
tRLD
D15 to D6, D0
AD5 to AD1
26
tRHD
Defined data
MB86612
2.5 Isochronous Interface
2.5.1 ICLK
Parameter
Symbol
Value
Min.
Max.
Unit
Clock frequency
—
DC
16
MHz
Clock cycle time
tICLK
62.5
∞
ns
Clock pulse width
tICLH
tICLL
10
—
ns
Clock rise/fall time
tICR
tICF
—
10
ns
tICLK
tICLH
tICF
tICR
0. 65 VDD
0. 25 VDD
ICLK
tICLL
27
MB86612
2.5.2 Sending Operation
(1) Start Sending Operation
Parameter
Value
Symbol
Min.
Max.
Unit
IDIR fall to ILWRE fall
tDLLL
—
4 ticlk + 10
ns
ICLK rise to ILWRE fall
tCHLL
—
40
ns
ILWRE fall to IV fall
tLLVL
1 ticlk + 10
—
ns
IV fall to ICLK rise
tVLCH
20
—
ns
Data setup time
tIDS
20
—
ns
Data hold time
tIDH
0
—
ns
TS input setup time*
tTSS
20
1 ticlk – 10
ns
TS input hold time*
tTSH
20
1 ticlk – 10
ns
ICLK
IDIR
tCHLL
tDLLL
ILWRE
tLLVL
tVLCH
IV
tTSS
tTSH
TS
tIDS
ID7 to ID0
1
tIDH
2
* : Specifications tIDH and tTSS are valid in DVC mode only. TS input is not used in MPEG mode.
28
3
MB86612
(2) End Sending Operation
Parameter
Value
Symbol
Min.
Max.
Unit
ICLK rise to ILWRE rise
tCHLH
—
40
ns
ILWRE rise to IV rise
tLHVH
1 ticlk + 10
—
ns
ILWR negate time*
tLWH
2 ticlk – 10
—
ns
ICLK
IDIR
tCHLH
tLWH
ILWRE
tLHVH
IV
ID7 to ID0
N-2
N-1
N
1
* : The MB86612 operates in ‘negate mode’, in which the ILWRE signal is negated for each source packet received,
as well as ‘assert mode’, in which the ILWRE signal is continuously asserted as long as ISO sending and receiving
FIFO writing are enabled. The above timing chart shows operation in negate mode. If there one or more packets
of empty space are present in the sending or receiving FIFO area, the ILWRE signal is again asserted.Note that
even in assert mode, if writing to the ISO sending or receiving FIFO areas is disabled, the ILWRE signal is negated
according to the timing shown above, and re-asserted when writing is again enabled.
29
MB86612
(3) IV Temporary Negation in Sending Operation
Parameter
Symbol
Value
Max.
tCHVH
0
1 ticlk – 20
ns
Date setup time
tIDS
20
—
ns
Data hold time
tIDH
0
—
ns
ICLK rise to IV rise
ICLK
IDIR
ILWRE
tCHVH
IV
tIDS
ID7 to ID0
30
Unit
Min.
N−1
tIDH
N
N+1
MB86612
2.5.3 Receiving Operation
(1) Start Receiving Operation
Parameter
Value
Symbol
Unit
Min.
Max.
tCHLL
—
40
ns
tLLEL
—
1 ticlk + 10
ns
ILWRE fall to IV fall
tLLVL
1 ticlk + 10
—
ns
IV fall to ICLK rise
tVLCH
20
—
ns
Data output definition time
tVLIDV
—
20
ns
Data output disable time
tCLIDX
0
10
ns
TS output assert time*2
tTSWL
32 ticlk – 10
—
ns
ICLK rise to ILWRE fall
1
ILWRE fall to IERR fall*
ICLK
IDIR
tCHLL
ILWRE
tLLEL
IERR
tTSWL
TS*
3
tLLVL
tVLCH
IV
tCLIDX
tVLIDV
ID7 to ID0
Hi − Z
1
2
*1: The IERR signal is output when an error is detected in receiving data.
*2: Specification tD is valid only in DVC mode. It does not apply to MPEG mode.
*3: The TS signal is output in synchronization with the rise of the ICLK pulse at the time the receiving packet time
stamp match is detected.
31
MB86612
(2) End Receiving Operation
Parameter
Value
Symbol
Min.
Max.
Unit
ICLK rise to ILWRE rise
tCHLH
—
40
ns
ILWRE rise to IV rise
tLHVH
1 ticlk + 10
—
ns
Final data output disable time
tVHIDX
—
20
ns
tLWH
2 ticlk – 10
—
ns
1
ILWRE negate time*
ICLK
IDIR
tCHLH
tLWH
ILWRE
IERR*
TS*
2
2
tLHVH
IV
tVHIDX
ID7 to ID0
N-2
N-1
N
Hi − Z
*1: The MB86612 operates in ‘negate mode’, in which the ILWRE signal is negated for each source packet received,
as well as ‘assert mode’, in which the ILWRE signal is continuously asserted as long as ISO sending and
receiving FIFO writing are enabled. The above timing chart shows operation in negate mode. If there one or
more packets of empty space are present in the sending or receiving FIFO area, the ILWRE signal is again
asserted.Note that even in assert mode, if writing to the ISO sending or receiving FIFO areas is disabled, the
ILWRE signal is negated according to the timing shown above, and re-asserted when writing is again enabled.
*2: The TS (in MPEG mode) and IERR signals are negated in synchronization with the ILWRE signal.
32
MB86612
(3) IV Temporary Negation in Receiving Operation
Parameter
Value
Symbol
IV rise to ICLK rise
tVHCH
Min.
Max.
40
—
Unit
ns
ICLK
IDIR
ILWRE
tVHCH
IV
ID7 to ID0
N−1
N
Hi − Z
N+1
33
MB86612
■ INTERNAL REGISTERS
The MB86612 internal registers have 3-bank construction, with 16-bit access to all registers.
Bank 0 contains registers necessary for IEEE 1394 settings and transfer, bank 1 contains registers necessary
for AV/C (MPEG, DVC) operation, and bank 2 contains CSR’s.
In addition each bank has registers used in common for MB86612 device control.
1. Bank Common Registers
The following registers can be accessed in any bank from bank 0 to bank 2.
Address
34
Write operation
Read operation
0
mode-control register
←
0
1
(reserved)
flag & status register
0
1
0
instruction fetch register
←
0
0
1
1
interrupt mask register
interrupt code register
0
0
1
0
0
(reserved)
Receiving acknowledge display
register
0A
0
0
1
0
1
ASYNC data port (sending)
ASYNC data port (receiving)
0C
0
0
1
1
0
(reserved)
←
0E
0
0
1
1
1
(reserved)
←
3E
1
1
1
1
1
bank select register
←
HEX
A5
A4
A3
A2
A1
00
0
0
0
0
02
0
0
0
04
0
0
06
0
08
MB86612
2. Bank 0 Registers
Bank 0 contains the registers required for 1394 settings and transfers.
Access to this bank is enabled by writing ‘0000h’ to the bank select register (3Eh).
Address
Write operation
Read operation
0
Sending ISO PKT header
setting register (high)
Receiving ISO PKT header
display register (high)
0
1
Sending ISO PKT header
setting register (low)
Receiving ISO PKT header
display register (low)
0
1
0
Sending ASYNC des ID
setting register
(reserved)
1
0
1
1
Sending ASYNC PKT param
setting register
Receiving ASYNC PKT param
display register
0
1
1
0
0
Sending ASYNC data length
setting register
Receiving ASYNC data length
display register
1A
0
1
1
0
1
Sending ASYNC ex tcode
setting register
Receiving ASYNC ex tcode
display register
1C
0
1
1
1
0
Sending ASYNC source ID
setting register
Receiving ASYNC source ID
display register
1E
0
1
1
1
1
Sending ASYNC resp param
setting register
Receiving ASYNC resp param
display register
20
1
0
0
0
0
Sending ASYNC des offset
setting register (high)
Receiving ASYNC des offset
display register (high)
22
1
0
0
0
1
Sending ASYNC des offset
setting register (middle)
Receiving ASYNC des offset
display register (middle)
24
1
0
0
1
0
Sending ASYNC des offset
setting register (low)
Receiving ASYNC des offset
display register (low)
26
1
0
0
1
1
(reserved)
←
28
1
0
1
0
0
(reserved)
PHY ID display register
2A
1
0
1
0
1
(reserved)
NODE config display register
2C
1
0
1
1
0
(reserved)
PORT config display register (port0)
HEX
A5
A4
A3
A2
A1
10
0
1
0
0
12
0
1
0
14
0
1
16
0
18
2E
1
0
1
1
1
(reserved)
PORT config display register (port1)
30
1
1
0
0
0
state clear setting register
root ID display register
32
1
1
0
0
1
Self ID PKT param setting register
ISO resource manager ID
display register
34
1
1
0
1
0
(reserved)
←
36
1
1
0
1
1
(reserved)
←
38
1
1
1
0
0
(reserved)
cycle timer monitor
display register (high)
3A
1
1
1
0
1
(reserved)
cycle timer monitor
display register (low)
3C
1
1
1
1
0
(reserved)
←
35
MB86612
3. Bank 1 Registers
Bank 1 contains the registers required for AV/C (MPEG, DVC) protocols.
Access to this bank is enabled by writing ‘0001h’ to the bank select register (3Eh).
Address
36
Write operation
Read operation
0
Sending time stamp offset
setting register
Receiving time stamp
display register (high)
0
1
Sending time stamp offset
setting register
Receiving time stamp
display register (low)
0
1
0
Sending CIP header
setting register (highest)
Receiving CIP header
display register (highest)
1
0
1
1
Sending CIP header
setting register (high)
Receiving CIP header
display register (high)
0
1
1
0
0
Sending CIP header
setting register (low)
Receiving CIP header
display register (low)
1A
0
1
1
0
1
Sending CIP header
setting register (lowest)
Receiving CIP header
display register (lowest)
1C
0
1
1
1
0
OMPR (high)
←
1E
0
1
1
1
1
OMPR (low)
←
20
1
0
0
0
0
OPCR0 (high)
←
22
1
0
0
0
1
OPCR0 (low)
←
24
1
0
0
1
0
(reserved)
←
26
1
0
0
1
1
(reserved)
←
28
1
0
1
0
0
(reserved)
←
2A
1
0
1
0
1
(reserved)
←
2C
1
0
1
1
0
IMPR (high)
←
2E
1
0
1
1
1
IMPR (low)
←
30
1
1
0
0
0
IPCR0 (high)
←
32
1
1
0
0
1
IPCR0 (low)
←
34
1
1
0
1
0
(reserved)
←
36
1
1
0
1
1
(reserved)
←
HEX
A5
A4
A3
A2
A1
10
0
1
0
0
12
0
1
0
14
0
1
16
0
18
38
1
1
1
0
0
(reserved)
←
3A
1
1
1
0
1
(reserved)
←
3C
1
1
1
1
0
AV mode setting register
AV status register
MB86612
4. Bank 2 Registers
Bank 2 contains CSR’s.
Access to this bank is enabled by writing ‘0002h’ to the bank select register (3Eh).
Address
Write operation
Read operation
0
bus manager ID register (high)
←
0
1
bus manager ID register (low)
←
0
1
0
bandwidth available register (high)
←
1
0
1
1
bandwidth available register (low)
←
0
1
1
0
0
channels available high register (high)
←
1A
0
1
1
0
1
channels available high register (low)
←
1C
0
1
1
1
0
channels available low register (high)
←
1E
0
1
1
1
1
channels available low register (low)
←
20
1
0
0
0
0
(reserved)
←
22
1
0
0
0
1
(reserved)
←
24
1
0
0
1
0
(reserved)
←
26
1
0
0
1
1
(reserved)
←
28
1
0
1
0
0
(reserved)
←
2A
1
0
1
0
1
(reserved)
←
2C
1
0
1
1
0
(reserved)
←
2E
1
0
1
1
1
(reserved)
←
30
1
1
0
0
0
(reserved)
←
32
1
1
0
0
1
(reserved)
←
34
1
1
0
1
0
(reserved)
←
36
1
1
0
1
1
(reserved)
←
38
1
1
1
0
0
(reserved)
←
3A
1
1
1
0
1
(reserved)
←
3C
1
1
1
1
0
(reserved)
←
HEX
A5
A4
A3
A2
A1
10
0
1
0
0
12
0
1
0
14
0
1
16
0
18
37
MB86612
■ ORDERING INFORMATION
Partnumber
38
Package
MB86612PFV
100-pin plastic LQFP
(FPT-100P-M05)
MB86612PBT
120-pin plastic FBGA
(BGA-120P-M01)
Remarks
MB86612
■ PACKAGE DIMENSIONS
100-pin plastic LQFP
(FPT-100P-M05)
+0.20
16.00±0.20(.630±.008)SQ
75
1.50 −0.10
+.008
.059 −.004
51
14.00±0.10(.551±.004)SQ
76
(Mounting height)
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
100
0.15(.006)
26
0.15(.006)MAX
LEAD No.
"B"
25
1
0.40(.016)MAX
"A"
0.50(.0197)TYP
+0.08
0.18 −0.03
+.003
.007 −.001
+0.05
0.08(.003)
0.127 −0.02
+.002
.005 −.001
M
Details of "B" part
0.10±0.10
(STAND OFF)
(.004±.004)
0.50±0.20(.020±.008)
0.10(.004)
C
0~10˚
Dimensions in mm (inches)
1995 FUJITSU LIMITED F100007S-2C-3
120-pin plastic FBGA
(BGA-120P-M01)
12.00±0.10(.472±.004)SQ
+0.20
+.008
1.25 –0.10 .049 –.004
(Mounting height)
0.38±0.10(.015±.004)
(Stand off)
9.60(.378)REF
0.80(.031)TYP
13
12
11
10
9
8
7
6
0.10(.004)
5
4
3
INDEX
2
1
N M L K J H G F E D C B A
C0.80(.031)
C
1998 FUJITSU LIMITED B120001S-1C-1
120-Ø0.45±0.10
(120-Ø.018±.004)
0.08(.003)
M
Dimensions in mm (inches)
39
MB86612
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9901
 FUJITSU LIMITED Printed in Japan
40
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
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