IDT IDT74FCT841ATPYB Fast cmos bus interface latch Datasheet

IDT54/74FCT841AT/BT/CT/DT
FAST CMOS
BUS INTERFACE
LATCHES
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Common features:
– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT841T:
– A, B, C and D speed grades
– High drive outputs (-15mA IOH, 48mA IOL)
– Power off disable outputs permit “live insertion”
The FCT8xxT series is built using an advanced dual metal
CMOS technology.
The FCT8xxT bus interface latches are designed to eliminate the extra packages required to buffer existing latches
and provide extra data width for wider address/data paths or
buses carrying parity. The FCT841T are buffered, 10-bit wide
versions of the popular FCT373T function. They are ideal for
use as an output port requiring high IOL/IOH.
All of the FCT8xxT high-performance interface family can
drive large capacitive loads, while providing low-capacitance
bus loading at both inputs and outputs. All inputs have clamp
diodes to ground and all outputs are designed for low-capacitance bus loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
D8
D9
D
D
D
D
D
D
D
D
LE Q
LE Q
LE Q
LE Q
LE Q
LE Q
LE Q
LE Q
LE
OE
Y0
Y1
Y2
Y3
Y4
Y5
Y8
Y9
2571 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
JUNE 1996
6.22
2571/6
1
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
LE
D2
D3
D4
NC
D5
D6
D7
4 3 2
1 28 27 26
25
5
24
6
23
7
8
22
L28-1
9
21
20
10
19
11
1213 14 15 16 17 18
Y2
Y3
Y4
NC
Y5
Y6
Y7
D8
D9
GND
NC
LE
Y9
Y8
24
23
22
21
20
19
18
17
16
15
14
13
D1
D0
OE
NC
VCC
Y0
Y1
1
2
3
4 P24-1
5 D24-1
SO24-2
6
SO24-7
7
SO24-8
8
&
9 E24-1
10
11
12
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
LE
YI
OE
I/O
I
I
O
I
Description
The latch data inputs.
The latch enable input. The latches are
transparent when LE is HIGH. Input data
is latched on the HIGH-to-LOW
transition.
The 3-state latch outputs.
The output enable control. When OE is
LOW, the outputs are enabled. When OE
is HIGH, the outputs V I are in highimpedance (off) state.
2571 tbl 01
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Commercial
VTERM(2) Terminal Voltage
–0.5 to +7.0
with Respect to
GND
(3)
VTERM
Terminal Voltage
–0.5 to
with Respect to
VCC +0.5
GND
TA
Operating
0 to +70
Temperature
TBIAS
Temperature
–55 to +125
Under Bias
TSTG
Storage
–55 to +125
Temperature
PT
Power Dissipation
0.5
I OUT
DC Output
Current
2571 drw 03
FUNCTION TABLE(1)
PIN DESCRIPTION
Name
DI
LCC
TOP VIEW
2571 drw 02
–60 to +120
OE
Inputs
LE
Internal Output
QI
YI
DI
H
H
L
L
Z
High Z
H
H
H
H
Z
High Z
H
L
X
NC
Z
Latched (High Z)
L
H
L
L
L
Transparent
L
H
H
H
H
Transparent
L
L
X
NC
NC
Function
Latched
NOTE:
2571 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, Z = High Impedance
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Military
–0.5 to +7.0
Unit
V
–0.5 to
VCC +0.5
V
–55 to +125
°C
–65 to +135
°C
–65 to +150
°C
0.5
W
–60 to +120
mA
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
Conditions
VIN = 0V
Typ.
6
VOUT = 0V
8
Max. Unit
10
pF
12
NOTE:
1. This parameter is measured at characterization but not tested.
pF
2571 lnk 04
NOTES:
2571 lnk 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
6.22
2
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2.0
Typ.(2)
—
Max.
—
Unit
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
II H
Input HIGH Current(4)
VCC = Max.
VI = 2.7V
—
—
±1
µA
II L
Input LOW Current (4)
VI = 0.5V
—
—
±1
I OZH
High Impedance Output Current
I OZL
(3-State Output pins) (4)
II
Input HIGH Current(4)
VCC = Max., VI = VCC (Max.)
VIK
Clamp Diode Voltage
VH
Input Hysteresis
I CC
Quiescent Power Supply Current
VO = 2.7V
—
—
±1
VO = 0.5V
—
—
±1
—
—
±1
VCC = Min., IIN = –18mA
—
–0.7
–1.2
V
—
—
200
—
mV
—
0.01
1
VCC = Max.
VCC = Max., VIN = GND or VCC
µA
µA
mA
2571 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT841T
VOL
Output LOW Voltage
I OS
Short Circuit Current
Test Conditions(1)
VCC = Min.
I OH = –6mA MIL.
VIN = VIH or V IL
I OH = –8mA COM'L.
I OH = –12mA MIL.
I OH = –15mA COM'L.
VCC = Min.
I OL = 32mA MIL.
VIN = VIH or V IL
I OL = 48mA COM'L.
VCC = Max., VO = GND (3)
I OFF
Input/Output Power Off Leakage(5)
VCC = 0V, VIN or V O ≤ 4.5V
Symbol
VOH
Parameter
Output HIGH Voltage
Min.
2.4
Typ.(2)
3.3
Max.
—
Unit
V
2.0
3.0
—
V
—
0.3
0.5
V
–60
–120
–225
mA
—
—
±1
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
6.22
µA
2571 lnk 06
3
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆ICC
ICCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current (4)
IC
Total Power Supply Current (6)
Test Conditions(1)
VCC = Max.
VIN = 3.4V(3)
VCC = Max.
Outputs Open
OE = GND
LE = VCC
One Input Toggling
50% Duty Cycle
VCC = Max.
Min.
—
Typ.(2)
0.5
Max.
2.0
Unit
mA
VIN = VCC
VIN = GND
—
0.15
0.25
mA/
MHz
VIN = VCC
—
1.5
3.5
mA
VIN = 3.4
VIN = GND
—
1.8
4.5
VIN = VCC
—
3.0
6.0 (5)
—
5.0
14.0 (5)
Outputs Open
fi = 10MHz
50% Duty Cycle
OE = GND
LE = VCC
One Bit Toggling
VCC = Max.
VIN = GND
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE = GND
LE = VCC
Eight Bits Toggling
VIN = GND
VIN = 3.4
VIN = GND
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.22
2571 tbl 07
4
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841AT
Com'l.
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Parameter
Propagation Delay
DI to YI (LE = HIGH)
Propagation Delay
LE to YI
Output Enable Time OE to YI
Output Disable Time OE to Y
tSU
Data to LE Set-up Time
tH
Data to LE Hold Time
tW
LE Pulse Width HIGH(3)
I
Conditions(1)
Min.(2)
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 5pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
1.5
RL = 500Ω
FCT841BT
Mil.
Max.
Min.(2)
9.0
1.5
1.5
13.0
1.5
Com'l.
Max.
Min.(2)
10.0
1.5
1.5
15.0
12.0
1.5
1.5
16.0
1.5
Mil.
Max.
Min.(2)
Max.
6.5
1.5
7.5
1.5
13.0
1.5
15.0
13.0
1.5
8.0
1.5
10.5
1.5
20.0
1.5
15.5
1.5
18.0
11.5
1.5
13.0
1.5
8.0
1.5
8.5
1.5
23.0
1.5
25.0
1.5
14.0
1.5
15.0
1.5
7.0
1.5
9.0
1.5
6.0
1.5
6.5
1.5
8.0
1.5
10.0
1.5
7.0
1.5
7.5
2.5
—
2.5
—
2.5
—
2.5
—
Unit
ns
ns
ns
ns
ns
2.5
—
3.0
—
2.5
—
2.5
—
ns
4.0
—
5.0
—
4.0
—
4.0
—
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2571 tbl 08
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841CT
Com'l.
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Parameter
Propagation Delay
DI to YI (LE = HIGH)
Propagation Delay
LE to YI
Output Enable Time OE to YI
Output Disable Time OE to Y
tSU
Data to LE Set-up Time
tH
Data to LE Hold Time
tW
LE Pulse Width HIGH(3)
I
Conditions(1)
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 5pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
Min.(2)
RL = 500Ω
FCT841DT
Mil.
Max. Min.(2)
Com'l.
Max. Min.(2)
Mil.
Max.
Min.(2)
Max.
Unit
ns
1.5
5.5
1.5
6.3
1.5
4.2
—
—
1.5
13.0
1.5
15.0
1.5
8.0
—
—
1.5
6.4
1.5
6.8
1.5
4.0
—
—
1.5
15.0
1.5
16.0
1.5
8.0
—
—
1.5
6.5
1.5
7.3
1.5
4.8
—
—
1.5
12.0
1.5
13.0
1.5
9.0
—
—
1.5
5.7
1.5
6.0
1.5
4.0
—
—
1.5
6.0
1.5
6.3
1.5
4.0
—
—
2.5
—
2.5
—
1.5
—
—
—
ns
2.5
—
2.5
—
1.0
—
—
—
ns
4.0
—
4.0
—
3.0
—
—
—
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
ns
ns
ns
2571 tbl 09
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
6.22
5
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
V CC
500Ω
Switch
Open Drain
Disable Low
Closed
Enable Low
V OUT
VIN
Pulse
Generator
Test
7.0V
Open
All Other Tests
D.U.T.
50pF
RT
2571 lnk 11
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
CL
2571 drw 04
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tH
tSU
tREM
tSU
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
tH
2571 drw 06
2571 drw 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
DISABLE
3V
1.5V
0V
CONTROL
INPUT
tPZL
VOH
1.5V
VOL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
tPLZ
tPZH
OUTPUT
NORMALLY
HIGH
2571 drw 07
SWITCH
OPEN
3.5V
3.5V
1.5V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
2571 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.22
6
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
FCT
IDT
XX
XXXX
Temp. Range
Device Type
X
Package
X
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
D
E
L
SO
PY
Q
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
841AT
841BT
841CT
841DT
10-Bit Non-Inverting Latch
54
74
–55°C to +125°C
0°C to +70°C
2571 drw 09
6.22
7
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