ONSEMI NCP1606BDR2G

NCP1606
Cost Effective Power Factor
Controller
The NCP1606 is an active power factor controller specifically
designed for use as a pre−converter in electronic ballasts, ac−dc
adapters and other medium power off line converters (typically up to
300 W). It embeds a Critical Conduction Mode (CRM) scheme that
substantially exhibits unity power factor across a wide range of input
voltages and power levels. Housed in a DIP8 or SOIC−8 package, the
NCP1606 minimizes the number of external components. Its
integration of comprehensive safety protection features makes it an
excellent driver for rugged PFC stages.
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•
•
•
•
•
SO−8
D SUFFIX
CASE 751
“Unity” Power Factor
No Need for Input Voltage Sensing
Latching PWM for Cycle by Cycle On Time Control (Voltage Mode)
High Precision Voltage Reference (±1.5% over the VCC and Temp.
Ranges)
Very Low Startup Current Consumption (≤ 40 mA)
Low Typical Operating Current (2.1 mA)
−500 mA / +800 mA Totem Pole Gate Driver
Undervoltage Lockout with Hysteresis
Pin to Pin Compatible with Industry Standards
NCP1606x
AWL
YYWWG
1
DIP−8
P SUFFIX
CASE 626
x
A
L, WL
Y, YY
W, WW
G or G
Programmable Overvoltage Protection
Protection against Open Loop (Undervoltage Protection)
Accurate and Programmable On Time Limitation
Overcurrent Limitation
1606x
ALYW
G
1
8
Safety Features
•
•
•
•
8
1
General Features
•
•
•
•
MARKING
DIAGRAMS
8
= A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTION
Feedback
Control
Ct
CS
VCC
Drive
Ground
ZCD/STDWN
(Top View)
Typical Applications
• Electronic Light Ballast
• AC Adapters, TVs, Monitors
• All Off Line Appliances Requiring Power Factor Correction
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 20 of this data sheet.
LBOOST
VOUT
DBOOST
LOAD
(Ballast,
SMPS, etc.)
RZCD
+
AC Line
EMI
Filter
Cin
ROUT1
1
Ccomp
ROUT2
2
3
4
Ct
NCP1606
FB V
CC
Ctrl DRV
Ct
GND
CS ZCD
VCC
8
+
CBULK
7
6
5
RSENSE
Figure 1. Typical Application
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 3
1
Publication Order Number:
NCP1606/D
NCP1606
VCC
Shutdown
VOUT
nPOK
+
FB
(Enable EA)
E/A −
ESD +
IEAsink
VDD
Enable
VCONTROL
Control
ESD
LBOOST
Ct
Fault
nPOK
270 mA
PWM
−
+
Add VEAL
Offset
ESD
S Q
DRV
CS
RSENSE
VDD Reg
Static OVP
VEAL
Clamp Static OVP is triggered
when clamp is activated.
VDD
Ct
VDD
VDDGD
VEAH
Clamp
LEB
ESD
+
+
−
ZCD
RZCD
+
VCL(POS)
Clamp
2.3 V
+
−
+
VCL(NEG)
Active
Clamp
−
+
R Q
OCP
VCC
VCS(limit)
VDD
+
AC IN
UVLO
Isink>Iovp
2.5 V
CCOMP
+
−
Dynamic OVP
Measure
+
DBOOST
ROUT2
ESD
300
mV
+
ROUT1
CBULK
VCC
UVP
−
+
1.6 V
+
−
S Q
Demag
DRV
S Q
RQ
RQ
Off Timer
Reset
Shutdown
200 mV
VDDGD
S Q
VDDGD
GND
RQ
S Q
POK
RQ
nPOK
*All SR Latches are Reset Dominant
*All values shown are typical only. Refer to the “Electrical Characteristics”
for complete specifications.
Figure 2. Block Diagram
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NCP1606
PIN FUNCTION DESCRIPTION
Pin Number
Name
Function
1
Feedback (FB)
2
Control
3
Ct
4
Current Sense
(CS)
5
Zero Current
Detection (ZCD)
6
Ground (GND)
7
Drive (DRV)
The powerful integrated driver is suitable to effectively switch a high gate charge power MOSFET.
8
VCC
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 12 V (typ)
and turns off when VCC goes below 9.5 V (typ). After startup, the operating range is 10.3 V to 20 V.
The FB pin makes available the inverting input of the internal error amplifier. A simple resistor divider
scales and delivers the output voltage to the FB pin to maintain regulation. The feedback information
is also used for the programmable overvoltage and undervoltage protections.
The regulation block output is available on this pin. A compensation network is placed between FB
and Control to set the loop bandwidth low enough to yield a high power factor ratio and a low THD.
The Ct pin sources a 270 mA current to charge an external timing capacitor. The circuit controls the power
switch on time by comparing the Ct voltage to an internal voltage derived from the regulation block.
This pin limits the pulse by pulse current through the switch MOSFET when connected as show in
Figure 1. When the voltage exceeds 1.7 V (A version) or 0.5 V (B version), the drive turns off. The
maximum switch current can be adjusted by changing the sense resistor.
The voltage of an auxiliary winding should be applied to this pin to detect the moment when the coil is
demagnetized for critical conduction mode operation. Ground ZCD to shutdown the part.
Connect this pin to the pre−converter ground.
MAXIMUM RATINGS
Pin
Rating
Symbol
Value
Unit
IDRV(source)
IDRV(sink)
+500
−800
mA
mA
7
Output Drive Capability
7
Maximum DRV Pin Voltage
VDRV
−0.3, +20
V
8
Power Supply Input
VCC
−0.3, +20
V
Input Voltage
VIN
−0.3, +9
V
PD(DIP)
RqJA(DIP)
800
100
mW
°C/W
PD(SO)
RqJA(SO)
450
178
mW
°C/W
TJ
−25 to +125
°C
Maximum Junction Temperature
TJmax
150
°C
Storage Temperature Range
TSmax
−65 to 150
°C
Lead Temperature (Soldering, 10 s)
TLmax
300
°C
1, 2, 3, 4, 5
Power Dissipation and Thermal Characteristics
P suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance Junction−to−Air
D suffix, Plastic Package, Case 751
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance Junction−to−Air
Operating Junction Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1−8 (except pin 7): Human Body Model 2000 V per Mil−Std−883, Method 3015. Machine Model Method 200 V
Pin 7: Human Body Model 2000 V per Mil−Std−883, Method 3015. Machine Model Method 170 V
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1606
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified: For typical values, TJ = 25°C. For min/max values, TJ = −25°C to +125°C, VCC = 12 V, FB = 2.4 V, CDRV =
1 nF, Ct = 1 nF, CS = 0 V, Control = open, ZCD = open)
Symbol
Rating
Min
Typ
Max
Unit
VCC UNDERVOLTAGE LOCKOUT SECTION
VCC(on)
VCC Startup Threshold (Undervoltage Lockout Threshold, Vcc rising)
11
12
13
V
VCC(off)
VCC Disable Voltage after Turn On (Undervoltage Lockout Threshold, VCC falling)
8.7
9.5
10.3
V
HUVLO
Undervoltage Lockout Hysteresis
2.2
2.5
2.8
V
Icc consumption during startup: 0 V < VCC < VCC(on) − 200 mV
−
20
40
mA
ICC1
Icc consumption after turn on at VCC = 12 V, No Load, 70 kHz switching
−
1.4
2.0
mA
ICC2
Icc consumption after turn on at VCC = 12 V, 1 nF Load, 70 kHz switching
−
2.1
3
mA
Icc consumption after turn on at VCC = 12 V, 1 nF Load, no switching
(such as during OVP fault, UVP fault, or grounding ZCD)
−
1.2
1.6
mA
2.475
2.465
2.50
2.50
2.525
2.535
V
Vref Line Regulation from VCC(on) + 200 mV < VCC < 20 V, @ TJ = 25°C
−2
−
2
mV
Error Amplifier Current Capability:
Sink (Control = 4 V, VFB = 2.6 V):
Source (Control = 4 V, VFB = 2.4 V):
8.0
−2
17
−6.0
−
−
DEVICE CONSUMPTION
ICC(startup)
ICC(fault)
REGULATION BLOCK (ERROR AMPLIFIER)
VREF
VREF(line)
IEA
Voltage Reference @ TJ = 25 °C
over temperature range (−25°C to +125°C)
mA
GOL
Open Loop, Error Amplifier Gain (Note 3)
−
80
−
dB
BW
Unity Gain Bandwidth (Note 3)
−
1
−
MHz
IFB
FB Bias Current @ VFB = 3 V
−500
−
500
nA
IControl
Control Pin Bias Current @ FB = 0 V and Control = 4.0 V.
−1
−
1
mA
VEAH
VCONTROL @ IEASOURCE = 0.5 mA, VFB = 2.4 V
4.9
5.3
5.7
V
VEAL
VCONTROL @ IEASINK = 0.5 mA, VFB = 2.6 V
1.85
2.1
2.4
V
VEA(diff) = VEAH − VEAL. Difference between max and min Control voltages
3.0
3.2
3.4
V
Overcurrent Protection Threshold:
NCP1606A
NCP1606B
1.6
0.45
1.7
0.5
1.8
0.55
tLEB
Leading Edge Blanking duration
150
250
350
ns
tCS
Overcurrent protection propagation delay.
40
100
170
ns
ICS
CS bias current @ VCS = 2 V
−1
−
1
mA
VEA(diff)
CURRENT SENSE BLOCK
VCS(limit)
V
ZERO CURRENT DETECTION
VZCDH
Zero Current Detection Threshold (VZCD rising)
2.1
2.3
2.5
V
VZCDL
Zero Current Detection Threshold (VZCD falling)
1.5
1.6
1.8
V
VZCDH − VZCDL
500
700
900
mV
Maximum ZCD bias Current @ VZCD = 5 V
−2
−
+2
mA
VCL(POS)
Upper Clamp Voltage @ IZCD = 2.5 mA
5
5.7
6.5
V
VZCDHYS
IZCD
ICL(POS)
Current Capability of the Positive Clamp at VZCD = VCL(POS) + 200 mV:
5.0
8.5
−
mA
VCL(NEG)
Negative Active Clamp Voltage @ IZCD = −2.5 mA
0.45
0.6
0.75
V
ICL(NEG)
Current Capability of the Negative Active Clamp:
in normal mode (VZCD = 300 mV)
in shutdown mode (VZCD = 100 mV)
2.5
35
3.7
70
5.0
100
mA
mA
3. Parameter characterized and guaranteed by design, but not tested in production.
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NCP1606
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified: For typical values, TJ = 25°C. For min/max values, TJ = −25°C to +125°C, VCC = 12 V, FB = 2.4 V, CDRV =
1 nF, Ct = 1 nF, CS = 0 V, Control = open, ZCD = open)
Symbol
Rating
Min
Typ
Max
Unit
150
200
250
mV
VSDL
Shutdown Threshold (VZCD falling)
VSDH
Enable Threshold (VZCD rising)
−
290
350
mV
Shutdown Comparator Hysteresis
−
90
−
mV
VSDHYS
Zero current detection propagation delay
−
100
170
ns
tSYNC
tZCD
Minimum detectable ZCD pulse width
−
70
−
ns
tSTART
Drive off restart timer
75
180
300
ms
243
270
297
mA
−
−
100
ns
RAMP CONTROL
ICHARGE
tCT(discharge)
Charge Current (VCT = 0 V)
Time to discharge a 1 nF Ct capacitor from VCT = 3.4 V to 100 mV.
VCTMAX
Maximum Ct level before DRV switches off
2.9
3.2
3.3
V
tPWM
Propagation delay of the PWM comparator
−
150
220
ns
34
9.0
8.7
40
10.4
−
45
11.8
12.1
−
−
30
8
−
−
OVER AND UNDERVOLTAGE PROTECTION
IOVP
IOVP(HYS)
Dynamic overvoltage protection (OVP) triggering current:
NCP1606A
NCP1606B @ TJ = 25°C
NCP1606B @ TJ = −25°C to +125°C
Hysteresis of the dynamic OVP current before the OVP latch is released:
NCP1606A
NCP1606B
VOVP
Static OVP Threshold Voltage
VUVP
Undervoltage protection (UVP) threshold voltage
mA
mA
VEAL +
100 mV
V
0.25
0.3
0.4
V
Gate Drive Resistance:
ROH @ ISOURCE = 100 mA
ROH @ ISOURCE = 20 mA
ROL @ ISINK = 100 mA
ROL @ ISINK = 20 mA
−
−
−
−
12
12
6
6
18
18
10
10
trise
Drive voltage rise time from 10% VCC to 90% VCC with CDRV = 1 nF and VCC = 12 V.
−
30
80
ns
tfall
Drive voltage fall time from 10% VCC to 90% VCC with CDRV = 1 nF and VCC = 12 V.
−
25
70
ns
Driver output voltage at VCC = VCC(on) − 200 mV and Isink = 10 mA
−
−
0.2
V
GATE DRIVE SECTION
ROH
ROL
VOUT(start)
W
3. Parameter characterized and guaranteed by design, but not tested in production.
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NCP1606
274
14
272
12
270
10
Ct = 1 nF
ON TIME (ms)
268
266
4
262
2
260
−50
−25
0
25
50
75
100
125
0
150
0
1
2
3
4
5
6
TEMPERATURE (°C)
VCONTROL (V)
Figure 3. Oscillator Charge Current (ICHARGE)
vs. Temperature
Figure 4. Typical On Time (TON) vs. VCONTROL
Level
PWM PROPAGATION DELAY (ns)
170
3.25
3.20
3.15
3.10
3.05
3.00
−50
−25
0
25
50
75
100
125
150
140
−25
0
25
50
75
100
150
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Maximum Ct Level (VCTMAX) vs.
Temperature
Figure 6. PWM Comparator Propagation Delay
(tPWM) vs. Temperature
2.505
100
2.500
80
200
160
GAIN
2.495
60
2.490
2.485
2.480
2.475
2.470
−50
160
130
−50
150
GAIN (dB)
MAXIMUM Ct LEVEL (V)
6
264
3.30
REFERENCE VOLTAGE (V)
8
−25
0
25
50
75
100
125
150
120
PHASE
PHASE (°)
OSCILLATOR CHARGE CURRENT (mA)
TYPICAL CHARACTERISTICS
40
80
20
40
0
0
−20
10E+0 100E+0
1E+3
10E+3
100E+3
−40
1E+6 10E+6
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 7. Reference Voltage (VREF) vs.
Temperature
Figure 8. Error Amplifier Open Loop Gain (GOL)
and Phase
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NCP1606
TYPICAL CHARACTERISTICS
IOVP
40
35
30
IOVP(HYS)
25
20
−50
SWITCHING SUPPLY CURRENT (ICC2) (mA)
DYNAMIC OVP CURRENT (mA)
12
−25
0
25
50
75
100
125
11
IOVP
10
9
IOVP(HYS)
8
7
−50
150
−25
0
25
50
75
100
125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Overvoltage Activation Current vs.
Temperature for the A Version
Figure 10. Overvoltage Activation Current vs.
Temperature for the B Version
2.20
24
2.15
22
STARTUP CURRENT (mA)
DYNAMIC OVP CURRENT (mA)
45
2.10
2.05
2.00
1.95
1.90
−50
−25
0
25
50
75
100
125
20
18
16
14
12
10
−50
150
−25
0
25
50
75
100
125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Supply Current (ICC2) vs.
Temperature
Figure 12. Startup Current (ICC_startup) vs.
Temperature
13
200
RESTART TIMER (ms)
SUPPLY VOLTAGE (V)
VCC(ON)
12
11
10
VCC(OFF)
9
8
−50
−25
0
25
50
75
100
125
150
190
180
170
160
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Supply Voltage Thresholds vs.
Temperature
Figure 14. Restart Timer (tSTART) vs.
Temperature
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150
NCP1606
TYPICAL CHARACTERISTICS
280
16
14
LEB FILTER DURATION (ns)
ROH
12
10
8
ROL
6
4
2
0
−50
−25
0
25
50
75
100
125
270
260
250
240
−50
150
−25
0
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 16. LEB Duration (tLEB) vs. Temperature
A VERSION OVERCURRENT THRESHOLD (V)
TEMPERATURE (°C)
Figure 15. Output Gate Drive Resistance (ROH
and ROL) at 100 mA vs. Temperature
0.520
1.710
0.515
1.705
A
1.700
0.510
0.505
1.695
B
1.690
0.500
1.685
0.495
1.680
0.490
1.675
0.485
1.670
−50
−25
0
25
50
75
100
125
0.480
150
TEMPERATURE (°C)
B VERSION OVERCURRENT THRESHOLD (V)
OUTPUT DRIVE RESISTANCE (W)
18
Figure 17. Overcurrent Threshold (VCS_Limit)
vs. Temperature
0.35
0.320
SHUTDOWN THRESHOLD (V)
UVP THRESHOLD (V)
0.315
0.310
0.305
0.300
0.295
0.290
0.285
0.280
−50
−25
0
25
50
75
100
125
150
0.30
VSDH
0.25
VSDL
0.20
0.15
−50
TEMPERATURE (°C)
−25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 19. Shutdown Thresholds vs.
Temperature
Figure 18. Undervoltage Protection Threshold
(VUVP) vs. Temperature
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150
NCP1606
Introduction
The NCP1606 is a voltage mode power factor correction
(PFC) controller designed to drive cost effective
pre−converters to meet input line harmonic regulations.
This controller operates in critical conduction mode
(CRM) for optimal performance in applications up to about
300 W. Its voltage mode scheme enables it to obtain unity
power factor without the need for a line sensing network.
The output voltage is accurately controlled by a high
precision error amplifier. The controller also implements a
comprehensive array of safety features for robust designs.
The key features of the NCP1606 are as follows:
• Constant on time (Voltage Mode) CRM operation.
High power factor ratios are easily obtained without
the need for input voltage sensing. This allows for
optimal standby power consumption.
• Accurate and Programmable On Time Limitation. The
NCP1606 using an accurate current source and an
external capacitor to generate the on time.
• High Precision Voltage Reference. The error amplifier
reference voltage is guaranteed at 2.5 V ±1.5% over
process, temperature, and VCC levels. This results in
very accurate output voltages.
• Very Low Startup Consumption. The circuit
consumption is reduced to a minimum (< 40 mA)
during the startup phase which allows fast, low loss,
charging of VCC. The architecture of the NCP1606
gives a controlled undervoltage lockout level and
provides ample VCC hysteresis during startup.
• Powerful Output Driver. A −500 mA / +800 mA totem
pole gate driver is used to provide rapid turn on and
turn off times. This translates into improved
efficiencies and the ability to drive higher power
MOSFETs. Additionally, a combination of active and
passive circuitry is used to ensure that the driver
output voltage does not float high while VCC is below
its turn on level.
• Programmable Overvoltage Protection (OVP). The
adjustable OVP feature protects the PFC stage against
excessive output overshoots that could damage the
application. These events can typically occur during
the startup phase or when the load is abruptly
removed. The NCP1606B gives a lower OVP
threshold, which can further reduce the application’s
standby power loss.
• Protection against Open Loop (Undervoltage
Protection). Undervoltage protection (UVP) disables
the PFC stage when the output voltage is excessively
low. This also protects the circuit in case of a failure in
the feedback network: if no voltage is applied to FB
because of a bad connection, UVP is activated and
shuts down the pre−converter.
• Overcurrent Limitation. The peak current is accurately
limited on a pulse by pulse basis. The level is
adjustable by modifying the switch sense resistor. The
•
NCP1606B uses a lower overcurrent threshold, which
can further reduce the application’s power dissipation.
An integrated LEB filter reduces the chance of noise
prematurely triggering the overcurrent limit.
Shutdown Features. The PFC pre−converter can be
easily placed in a shutdown mode by grounding either
the FB pin or the ZCD pin. During this mode, the ICC
current consumption is reduced and the error amplifier
is disabled.
Application information
Most electronic ballasts and switching power supplies
use a diode bridge rectifier and a bulk storage capacitor to
produce a dc voltage from the utility ac line (Figure 20).
This DC voltage is then processed by additional circuitry
to drive the desired output.
Rectifiers
AC
Line
Converter
+
Bulk
Storage
Capacitor
Load
Figure 20. Typical Circuit without PFC
This simple rectifying circuit draws power from the line
when the instantaneous ac voltage exceeds the capacitor
voltage. Since this occurs near the line voltage peak, the
resulting current draw is non sinusoidal and contains a very
high harmonic content. This results in a poor power factor
(typically < 0.6) and consequently, the apparent input
power is much higher than the real power delivered to the
load. Additionally, if multiple devices are tied to the same
input line, the effect is magnified and a “line sag” effect can
be produced (see Figure 21).
Vpk
Rectified DC
0
Line
Sag
AC Line Voltage
0
AC Line Current
Figure 21. Typical Line Waveforms without PFC
Increasingly, government regulations and utility
requirements necessitate control over the line current
harmonic content. To meet this need, power factor
correction is implemented with either a passive or active
circuit. Passive circuits usually contain a combination of
large capacitors, inductors, and rectifiers that operate at the
ac line frequency. Active circuits incorporate some form of
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NCP1606
a high frequency switching converter which regulates the
input current to stay in phase with the input voltage. These
circuits operate at a higher frequency and so they are
smaller, lighter in weight, and more efficient than a passive
circuit. With proper control of an active PFC stage, almost
any complex load can be made to appear in phase with the
PFC Preconverter
Rectifiers
AC Line
ac line, thus significantly reducing the harmonic current
content. Because of these advantages, active PFC circuits
have become the most popular way to meet harmonic
content requirements. Generally, they consist of inserting
a PFC pre−regulator between the rectifier bridge and the
bulk capacitor (Figure 22).
+
High
Frequency
Bypass
Capacitor
Converter
Bulk
Storage
Capacitor
+
NCP1606
Load
Figure 22. Active PFC Pre−Converter with the NCP1606
The boost (or step up) converter is the most popular
topology for active power factor correction. With the
proper control, it produces a constant voltage while
drawing a sinusoidal current from the line. For medium
power (<300 W) applications, critical conduction mode
(also called borderline conduction mode) is the preferred
control method. Critical conduction mode (CRM) occurs at
the boundary between discontinuous conduction mode
Diode Bridge
(DCM) and continuous conduction mode (CCM). In CRM,
the next driver on time is initiated when the boost inductor
current reaches zero. CRM operation is an ideal choice for
medium power PFC boost stages because it combines the
lower peak currents of CCM operation with the zero current
switching of DCM operation. The operation and
waveforms in a PFC boost converter are illustrated in
Figure 23.
Diode Bridge
Icoil
+
Vin
+
IN
L
Vd
+
Vd
L
+
VOUT
−
The power switch is ON
The power switch is OFF
The power switch being about zero, the input voltage
is applied across the coil. The coil current linearly
increases with a (Vin/L) slope.
Vd
Vin
+
IN
−
Coil
Current
Icoil
Vin/L
The coil current flows through the diode. The coil voltage is (VOUT −
Vin) and the coil current linearly decays with a (VOUT − Vin)/L slope.
(VOUT − Vin)/L
Icoil_pk
Critical Conduction Mode:
Next current cycle starts as
soon as the core is reset.
VOUT
Vin
If next cycle does not start
then Vd rings towards Vin
Figure 23. Schematic and Waveforms of an Ideal CRM Boost Converter
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NCP1606
When the switch is closed, the inductor current increases
linearly to its peak value. When the switch opens, the
inductor current linearly decreases to zero. At this point,
the drain voltage of the switch (Vd) is essentially floating
and begins to drop. If the next switching cycle does not
start, then the voltage will ring with a dampened frequency
around Vin. A simple derivation of equations (such as found
in AND8123), leads to the result that good power factor
correction in CRM operation is achieved when the on time
is constant across an ac cycle and is equal to:
Ton +
2 @ P OUT @ L
h @ Vac RMS
ILpk
IL(t)
Iinpk
MOSFET
(eq. 1)
2
Vin(t)
Vinpk
Iin(t)
ON
OFF
Figure 24. Inductor Waveform During CRM Operation
A simple plot of this switching over an ac line cycle is
illustrated in Figure 24. The off time varies based on the
instantaneous line voltage, but the on time is kept constant.
This naturally causes the peak inductor current (ILPK) to
follow the ac line voltage.
The NCP1606 represents an ideal method to implement
this constant on time CRM control in a cost effective and
robust solution. The device incorporates an accurate
regulation circuit, a low power startup circuit, and
advanced protection features.
ERROR AMPLIFIER REGULATION
The NCP1606 is configured to regulate the boost output
voltage based on its built in error amplifier (EA). The error
amplifier ’s negative terminal is pinned out to FB, the
positive terminal is tied to a 2.5 V ± 1.5% reference, and the
output is pinned out to Control (Figure 25).
VOUT
ROUT1
PWM BLOCK
EA
FB
−
+
2.5 V
TON(max)
+
ROUT2
Slope +
CCOMP
VCONTROL
Control
Ct
I CHARGE
TON
TPWM
VEAL
VCONTROL
VEAH
Figure 25. Error Amplifier and On Time Regulation Circuits
A resistor divider from the boost output to the input of the
EA sets the FB level. If the output voltage is too low, then
the FB level will drop and the EA will cause the control
voltage to increase. This increases the on time of the driver,
which increases the power delivered and brings the output
back into regulation. Alternatively, if the output voltage
(and hence FB voltage) is too high, then the control level
decreases and the driver on times are shortened. In this way,
the circuit regulates the output voltage (VOUT) so that the
VOUT portion that is applied to FB through the resistor
divider ROUT1 and ROUT2 is equal to the internal reference
(2.5 V). The output voltage can then be easily set according
to the following equation:
VOUT + 2.5 V @
ROUT1 ) ROUT2
ROUT2
(eq. 2)
A compensation network is placed between the FB and
Control pins to reduce the speed at which the EA responds
to changes in the boost output. This is necessary due to the
nature of an active PFC circuit. The PFC stage absorbs a
sinusoidal current from a sinusoidal line voltage. Hence,
the converter provides the load with a power that matches
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NCP1606
the average demand only. Therefore, the output capacitor
must “absorb” the difference between the delivered power
and the power consumed by the load. This means that when
the power fed to the load is lower than the demand, the
output capacitor discharges to compensate for the lack of
power. Alternatively, when the supplied power is higher
than that absorbed by the load, the output capacitor charges
to store the excess energy. The situation is depicted in
Figure 26.
Iac
Vac
PIN
POUT
VOUT
Figure 26. Output Voltage Ripple for a Constant Output Power
As a consequence, the output voltage exhibits a ripple at
a frequency of either 100 Hz (for 50 Hz mains such as in
Europe) or 120 Hz (for 60 Hz mains in the USA). This
ripple must not be taken into account by the regulation loop
because the error amplifier’s output voltage must be kept
constant over a given ac line cycle for a proper shaping of
the line current. Due to this constraint, the regulation
bandwidth is typically set below 20 Hz. For a simple type 1
compensation network, only a capacitor is placed between
FB and Control (see Figure 1). In this configuration, the
capacitor necessary to attenuate the bulk voltage ripple is
given by:
VDD
ICHARGE
Ct
+
PWM
−
+
TON
DRV
VCt
VCt(off)
G
10 20
CCOMP +
4 @ p fline @ ROUT1
VCONTROL
Control
VEAL
VCONTROL − VEAL
(eq. 3)
where G is the attenuation level in dB (commonly 60 dB)
TON
ON TIME SEQUENCE
Since the NCP1606 is designed to control a CRM boost
converter, its switching pattern must accommodate
constant on times and variable off times. The Controller
generates the on time via an external capacitor connected
to pin 3 (Ct). A current source charges this capacitor to a
level determined by the Control pin voltage. Specifically,
Ct is charged to VCONTROL minus the VEAL offset
(typically 2.1 V). Once this level is exceeded, the drive is
turned off (Figure 27).
DRV
Figure 27. On Time Generation
Since VCONTROL varies with the RMS line level and
output load, this naturally satisfies equation 1. And if the
values of compensation components are sufficient to filter
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NCP1606
out the bulk voltage ripple, then this on time is truly
constant over the ac line cycle.
Note that the maximum on time of the controller occurs
when VCONTROL is at its maximum. Therefore, the Ct
capacitor must be sized to ensure that the required on time
can be delivered at full power and the lowest input voltage
condition. The maximum on time is given by:
tON(max) +
Ct @ VCTMAX
Icharge
DRIVE
VOUT
Drain
(eq. 4)
ZCD
Combining this equation with equation 1, gives:
Ct w
2 @ POUT @ L @ Icharge
Winding
(eq. 5)
h @ Vac RMS 2 @ V CTMAX
5.7 V
2.3 V
1.6 V
where VCTMAX = 2.9 V (min)
Icharge = 297 mA (max)
Pin
OFF TIME SEQUENCE
While the on time is constant across the ac cycle, the off
time in CRM operation varies with the instantaneous input
voltage. The NCP1606 determines the correct off time by
sensing the inductor voltage. When the inductor current
drops to zero, the drain voltage (“Vd” in Figure 23) is
essentially floating and naturally begins to drop. If the
switch is turned on at this moment, then CRM operation
will be achieved. To measure this high voltage directly on
the inductor is generally not economical or practical.
Rather, a smaller winding is taken off of the boost inductor.
This winding, called the zero current detector (ZCD)
winding, gives a scaled version of the inductor output and
is more useful to the controller.
Figure 28. Voltage Waveforms for Zero Current
Detection
Figure 28 gives typical operating waveforms with the
ZCD winding. When the drive is on, a negative voltage
appears on the ZCD winding. And when the drive is off, a
positive voltage appears. When the inductor current drops
to zero, then the ZCD voltage falls and starts to ring around
zero volts. The NCP1606 detects this falling edge and starts
the next driver on time. To ensure that a ZCD event has
truly occurred, the NCP1606’s logic (Figure 29) waits for
the ZCD pin voltage to rise above VZCDH (2.3 V typical)
and then fall below VZCDL (1.6 V typical). In this way,
CRM operation is easily achieved.
NB
NZCD
+
−
+
VDD
RSENSE
VCL−NEG
Active
Clamp
ZCD
VCL−POS
Clamp
S
DRIVE
1.6 V
−
+
+
RZCD
2.3 V
+
−
+
Vin
0.6 V
Shutdown
200 mV
Figure 29. Implementation of the ZCD Winding
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Q
Reset
Dominant
Latch
R
Q
Demag
NCP1606
To prevent negative voltages on the ZCD pin, the pin is
internally clamped to VCLNEG (600 mV typ) when the ZCD
winding is negative. Similarly, the ZCD pin is clamped to
VCLPOS (5.7 V typical), when the voltage rises too high.
Because of these clamps, a resistor (RZCD in Figure 29) is
necessary to limit the current from the ZCD winding to the
ZCD pin.
At startup, there is no energy in the ZCD winding and
therefore no voltage signal to activate the ZCD
comparators. This means that the driver could never turn
on. Therefore, to enable the PFC stage to startup under
these conditions, an internal watchdog timer is integrated
into the controller. This timer turns the drive on if the driver
has been off for more than 180 ms (typical). Obviously, this
feature is deactivated during a fault mode (OVP, UVP, or
Shutdown), and reactivated when the fault is removed.
level, the internal references and logic of the NCP1606 turn
on. The controller has an undervoltage lockout (UVLO)
feature which keeps the part active until VCC drops below
VCC(off) (9.5 V typical). This hysteresis allows ample time
for the auxiliary winding to take over and supply the
necessary power to VCC (Figure 30).
VCC(on)
VCC
VCC(off)
Figure 30. Typical VCC Startup Waveform
When the PFC pre−converter is loaded by a switch mode
power supply (SMPS), then it is often preferable to have the
SMPS controller startup first. The SMPS can then supply
the NCP1606 VCC directly. Advanced controllers, such as
the NCP1230 or NCP1381, can control when to turn on the
PFC stage (see Figure 31) leading to optimal system
performance. This setup also eliminates the startup
resistors and therefore improves the no load power
dissipation of the system.
STARTUP
Generally, a resistor connected between the ac input and
VCC (pin 8) charges the VCC capacitor to the VCC(on) level
(12 V typical). Because of the very low consumption of the
NCP1606 during this stage (< 40 mA), most of the current
goes directly to charging up the VCC capacitor. This
provides faster startup times and reduced standby power
dissipation. When the VCC voltage exceeds the VCC(on)
Dboost
+
8
2
3
4
NCP1606
1
PFC_Vcc
1
8
2
7
6
3
6
5
4
5
7
+
Cbulk
VCC
+
+
+
NCP1230
Figure 31. NCP1606 Supplied by a Downstream SMPS Controller (NCP1230)
QUICK START and SOFT START
At startup, the error amplifier is enabled and Control is
pulled up to VEAL (typically 2.1 V). This is the lowest level
of control voltage which produces output drives. This
feature, called “quick start,” eliminates the delay at startup
associated with charging the compensation network to its
minimum level. This also produces a natural “soft start”
mode where the controller’s power ramps up from zero to
the required power (see Figure 32).
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NCP1606
OUTPUT DRIVER
VCC
The NCP1606 includes a powerful output driver capable
of peak currents of +500 mA and −800 mA. This enables
the controller to efficiently drive power MOSFETs for
medium power (up to 300 W) applications. Additionally,
the driver stage is equipped with both passive and active
pull down clamps (Figure 33). The clamps are active when
VCC is off and force the driver output to well below the
threshold voltage of a power MOSFET.
VCC(on)
VCC(off)
Iswitch
FB
2.5 V
Control
VEAL
Natural Soft Start
VOUT
Figure 32. Startup Timing Diagram Showing the
Natural Soft Start of the Control Pin
VCC
+
−
DRV IN
VDD
UVLO
VddGD
DRV
Ipullup
VDD REG
+
nVDD
GND
Figure 33. Output Driver Stage and Pull Down Clamps
Overvoltage Protection
and disables the driver until the output voltage returns to
nominal levels. This keeps the output voltage within an
acceptable range. The limit is adjustable so that the
overvoltage level can be optimally set. The level must not
be so low that it is triggered by the 100 or 120 Hz ripple of
the output voltage. But it must be low enough so as not to
require a larger voltage rating of the output capacitor.
Figure 34 depicts the operation of the OVP circuitry.
The low bandwidth of the feedback network makes
active PFC stages very slow systems. One consequence of
this is the risk of huge overshoots in abrupt transient phases
(startup, load steps, etc.). For reliable operation, it is
critical that some form of overvoltage protection (OVP)
effectively prevents the output voltage from rising too
high. The NCP1606 detects these excessive VOUT levels
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NCP1606
VOUT
UVP
−
+
ROUT1
+
300 mV
(Enable EA)
E/A
FB
−
+
Dynamic OVP
Icontrol > Iovp
2.5 V
Measure
Icontrol
+
ROUT2
Fault
VDD
CCOMP
Enable
VEAL Static OVP
Clamp Static OVP is triggered
when clamp is activated.
VCONTROL
Control
Icontrol
VEAH
Clamp
Figure 34. OVP and UVP Circuit Blocks
When the output voltage is in steady state, ROUT1 and
ROUT2 regulate the FB voltage to 2.5 V. Also, during this
equilibrium state, no current flows through the
compensation capacitor (“CCOMP” of Figure 1). Therefore:
• The ROUT1 current is:
(V
)nom * 2.5 V
IR
+ OUT
R OUT1
OUT1
• Therefore, the error amplifier sinks:
(eq. 11)
(V
) nom ) DV OUT−2.5 V 2.5 V
IR
−I R
+ OUT
−
R OUT2
R OUT1
OUT1
OUT2
The combination of equations (4) and (7) leads to a very
simple expression of the current sunk by the error
amplifier:
(eq. 6)
where (VOUT)nom is the nominal output voltage.
• The ROUT2 current is:
IR
OUT2
+ 2.5 V
R OUT2
IPIN2 + I R
OUT1
+I R
OUT2
å
(V OUT)nom * 2.5 V
+ 2.5 V
ROUT2
R OUT1
(eq. 8)
+ 2.5 V
R OUT2
OUT2
ROUT1 +
+
DV OUT
R OUT1
(eq. 12)
(V OUT)OVP * (VOUT) nom
I OVP
For instance if implementing the NCP1606B, and
420 V is the maximum output level and 400 V is the
nominal output level, then
(eq. 9)
ROUT1 + 420 * 400 + 1.9 MW
10.4 mA
(eq. 10)
OUT1
+
By simply adjusting ROUT1, the OVP limit can be easily
set. Therefore, one can compute the ROUT1 and ROUT2
resistances using the following procedure:
1. Select ROUT1 to set the desired overvoltage level:
• The ROUT1 current is:
IR
OUT2
(VOUT) OVP + (VOUT) nom ) (R OUT1 @ I OVP)
Under stable conditions, these equations are true.
Conversely when VOUT is not at its nominal level, the
output of the error amplifier sinks or sources the current
necessary to maintain 2.5 V on pin 1. In particular, in the
case of an overvoltage condition:
• The error amplifier maintains 2.5 V on pin 1, and the
ROUT2 current remains:
IR
* IR
Hence, the current absorbed by pin 2 (ICONTROL) is
proportional to the output voltage excess. The circuit
senses this current and disables the drive (pin 7) when
ICONTROL exceeds IOVP (typically 40 mA in NCP1606A,
10.4 mA in NCP1606B). This gives the OVP threshold as:
(eq. 7)
• And since no current flows through CCOMP,
IR
OUT1
V OUT−2.5 V
(V
)nom ) DVOUT−2.5 V
+ OUT
R OUT1
R OUT1
2. Select ROUT2 to adjust the regulation level:
where DVOUT is the output voltage excess.
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NCP1606
ROUT2 +
Furthermore, the NCP1606 incorporates a novel startup
sequence which ensures that undervoltage conditions are
always detected at startup. It accomplishes this by waiting
approximately 180 ms after VCC reaches VCC(on) before
enabling the error amplifier (Figure 19). During this wait
time, it looks to see if the feedback (FB) voltage is greater
than the UVP threshold. If not, then the controller enters a
UVP fault and leaves the error amplifier disabled.
However, if the FB pin voltage increases and exceeds the
UVP level, then the controller will start the application up
normally.
2.5 V @ ROUT1
V OUT(nom) * 2.5 V
For the above example, this leads to:
ROUT2 +
2.5 V
@ 1.9 MW + 12.0 kW.
400 V * 2.5 V
STATIC OVERVOLTAGE PROTECTION
If the OVP condition lasts for a long time, it may happen
that the error amplifier output reaches its minimum level
(i.e. Control = VEAL). It would then not be able to sink any
current and maintain the OVP fault. Therefore, to avoid any
discontinuity in the OVP disabling effect, the circuit
incorporates a comparator which detects when the lower
level of the error amplifier is reached. This event, called
“static OVP”, disables the output drives. Once the OVP
event is over, and the output voltage has dropped to normal,
then Control rises above the lower limit and the driver is
re−enabled (Figure 18).
VCC(on)
VCC
VCC(off)
VOUT(nom)
VOUT
FB
Vout(nom)
Vout
2.5 V
VUVP
VEAH
UVP Fault is “Removed”
Control
VEAL
Drive
UVP Wait
UVP
VeaH
Vcontrol
VeaL
IovpH
Icontrol
IovpL
UVP Wait
Figure 36. The NCP1606’s Startup Sequence with
and without a UVP Fault
The voltage on the output which exits a UVP fault is
given by:
Dynamic OVP
VOUT
Static OVP
(UVP)
+
R OUT1 ) R OUT2
@ 300 mV
R OUT2
(eq. 13)
If ROUT1 = 1.9 MW and ROUT2 = 12.0 kW, then the VOUT
UVP threshold is 48 V. This corresponds to an input voltage
of approximately 34 Vac.
Figure 35. OVP Timing Diagram
NCP1606 Undervoltage Protection (UVP)
Overcurrent Protection (OCP)
When the PFC stage is plugged in, the output voltage is
forced to roughly equate the peak line voltage. The
NCP1606 detects an undervoltage fault when this output
voltage is unusually low, such that the feedback voltage is
below VUVP (300 mV typ). In an UVP fault, the drive
output and error amplifier (EA) are disabled. The latter is
done so that the EA does not source a current which would
increase the FB voltage and prevent the UVP event from
being accurately detected. The UVP feature helps to
protect the application if something is wrong with the
power path to the bulk capacitor (i.e. the capacitor cannot
charge up) or if the controller cannot sense the bulk voltage
(i.e. the feedback loop is open).
A dedicated pin on the NCP1606 senses the peak current
and limits the driver on time if this current exceeds
VCS(limit). This level is 1.7 V (typ) on the NCP1606A and
0.5 V (typ) on the NCP1606B. Therefore, the maximum
peak current can be adjusted by changing Rsense according to:
Ipeak +
V CS(limit)
R sense
(eq. 14)
An internal LEB filter (Figure 20) reduces the likelihood
of switching noise falsely triggering the OCP limit. This
filter blanks out the first 250 ns (typical) of the current
sense signal. If additional filtering is necessary, a small RC
filter can be added between Rsense and the CS pin.
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NCP1606
SHUTDOWN MODE
DRIVE
CS
+
−
LEB
+
RSENSE
The NCP1606 allows for two methods to place the
controller into a standby mode of operation. The FB pin can
be pulled below the UVP level (0.3 V typical) or the ZCD
pin can be pulled below the VSDL level (typically 200 mV).
If the FB pin is used for shutdown (Figure 21(a)), care must
be taken to ensure that no significant leakage current exists
on the shutdown circuitry. This could impact the output
voltage regulation. If the ZCD pin is used for shutdown
(Figure 38(b)), then any parasitic capacitance created by
the shutdown circuitry will add to the delay in detecting the
zero inductor current event.
OCP
Imax
optional
Figure 37. OCP Circuitry with Optional External RC
Filter
LBOOST
VOUT
ROUT1
NCP1606
NCP1606
Ccomp
Shutdown
ROUT2
1 FB
VCC 8
1 FB
2 Ctrl
DRV 7
2 Ctrl
DRV 7
3 Ct
GND 6
3 Ct
GND 6
4 Cs
ZCD 5
4 Cs
ZCD 5
VCC 8
RZCD
Shutdown
Figure 21(a)
Figure 21(b)
Figure 38. Shutting Down the PFC Stage by Pulling FB to GND (A) or Pulling ZCD to GND (B)
To activate the shutdown feature on ZCD, the internal
clamp must first be overcome. This clamp will draw a
maximum of ICLNEG (5.0 mA maximum) before releasing
and allowing the ZCD pin voltage to drop low enough to
shutdown the part (Figure 39). After shutdown, the
comparator includes approximately 90 mV of hysteresis to
ensure noise free operation. A small current source (70 mA
typ) is also activated to pull the unit out of the shutdown
condition when the external pull down is released.
5 mA
IZCD
~70 mA
Shutdown
VSDL VSDH
VCLNEG
~1 V
Figure 39. Shutdown Comparator and Current Draw to Overcome Negative Clamp
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NCP1606
BOOST DESIGN EQUATIONS Components are identified in Figure 1
RMS Input Current
POUT
h @ Vac(rms)
h (the efficiency of only the Boost
PFC stage) is generally in the range
of 90 − 95%
2 @ Ǹ2 @ P OUT
h @ Vac LL
Ipk(max) occurs at the lowest line voltage.
Iac(rms) +
Maximum Inductor Peak
Current
Ipk(max) +
Inductor Value
2 @ Vac 2 @
Lv
ǒ
Off Time
tOFF +
Pin 3 Capacitor
Vac (rms) 2 @ h
2 @ L @ POUT
Ct w
Boost Turns to ZCD Turns
Ratio
@
ǒ
1*
Vac (rms) @ |sin q| @ Ǹ2
V OUT
Ǔ
h @ Vac RMS @ V CTMAX
ROUT1 +
The turns ratio must be low enough
so as to trigger the ZCD comparators
at high line.
V OUT * Vac HL @ Ǹ2
V ZCDH
RZCD must be large enough so that
the shutdown comparator is not inadvertently activated.
Vac HL @ Ǹ2
I CL_NEG @ (N B : N ZCD)
ROUT1 ) ROUT2
ROUT2
IOVP is given in the NCP1606 specification table. IOVP is lower for the
NCP1606B, then for the NCP1606A
version.
V OUT(max) * V OUT(nom)
IOVP
2.5 V @ ROUT1
ROUT2 +
V OUT(nom) * 2.5 V
VOUT
Bulk Cap Ripple
(UVP)
+
Inductor RMS Current
MOSFET RMS Current
IM(rms)
ǒ
Use fLINE = 47 Hz for worst case at
universal lines. The ripple must not
exceed the OVP level for VOUT.
POUT
C bulk @ 2 @ p @ fline @ VOUT
IcoilRMS +
Id MAX(rms) + 4 @
3
VUVP is given in the NCP1606 specification table.
R OUT1 ) R OUT2
@ V UVP
R OUT2
Vripple (pk−pk) +
2 @ P OUT
Ǹ3 @ Vac @ h
LL
Ǹ2 @pǸ2 @
Ǔ
POUT
+4@
3
h @ Vac LL
The off time is greatest at the peak of
the AC line voltage and approaches
zero at the AC line zero crossings.
Theta (q) represents the angle of the
AC line voltage.
Icharge and VCTMAX are given in the
NCP1606 specification table.
2
VOUT(max) + V OUT(nom) ) R OUT1 @ I OVP
Minimum output voltage
necessary to exit undervoltage protection (UVP)
Boost Diode RMS Current
The maximum on time occurs at the
lowest line voltage and maximum
output power.
V
OUT
*1
Vac (rms)@Ťsin(q)Ť@Ǹ2
VOUT + 2.5 V @
Maximum VOUT voltage
prior to OVP activation and
the necessary ROUT1 and
ROUT2.
f(min) is the minimum desired switching frequency. The maximum L must
be calculated at low line and high
line.
2 @ POUT @ L @ Icharge
RZCD w
Boost Output Voltage
Ǔ
t ON
NB : N ZCD v
Resistor from ZCD winding to the ZCD pin (pin 5)
* Vac
2 @ L @ P OUT
h @ Vac LL 2
tON(max) +
fSW +
OUT
Ǹ2
VOUT @ Vac @ I pk(max) @ fSW(min)
Maximum On Time
Frequency
V
2
@
P OUT
h @ ǸVac LL @ VOUT
ƪ ǒ
1*
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19
Ǔƫ
8 @ Ǹ2 @ Vac LL
3 @ p @ V OUT
NCP1606
BOOST DESIGN EQUATIONS Components are identified in Figure 1
MOSFET Sense Resistor
Rsense +
VCS(limit) is given in the NCP1606
specification table. The NCP1606B
has a lower VCS(limit) level.
V CS(limit)
I pk
PRsense + I M(rms) 2 @ Rsense
Bulk Capacitor RMS
Current
IC(rms) +
Type 1 CCOMP
Ǹ
32 @ Ǹ2 @ P OUT 2
* (ILOAD(rms)) 2
9 @ p @ Vac LL @ VOUT @ h2
CCOMP +
G is the desired attenuation in decibels (dB). Typically it is 60 dB.
10 Gń20
4 @ p @ f line @ ROUT1
ORDERING INFORMATION
Device
VcsLIMIT (typ) (Note 4)
IOVP (typ) (Note 4)
Package
Shipping†
NCP1606APG
1.7 V
40 mA
PDIP−8
50 Units / Rail
NCP1606ADR2G
1.7 V
40 mA
SOIC−8
2500 / Tape & Reel
NCP1606BPG
0.5 V
10 mA
PDIP−8
50 Units / Rail
NCP1606BDR2G
0.5 V
10 mA
SOIC−8
2500 / Tape & Reel
4. See the electrical specifications section for complete information on VCS and IOVP.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
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20
NCP1606
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
H
0.10 (0.004)
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
21
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0 _
8 _
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP1606
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE L
8
5
−B−
1
4
F
−A−
NOTE 2
L
C
J
−T−
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10_
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10_
0.030
0.040
N
SEATING
PLANE
D
H
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
K
G
0.13 (0.005)
M
T A
M
B
M
The product described herein (NCP1606), may be covered by the following U.S. patents: 5,073,850 and 6,362,067. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
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time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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22
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For additional information, please contact your local
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NCP1606/D